TEA1781T; TEA1782T GreenChip PC secondary control ICs Rev. 01 — 13 February 2009 Preliminary data sheet 1. General description The TEA1781T and TEA1782T are designed to cooperate with the TEA1771T primary side controller in a unique converter topology based on the active clamp forward converter. On the secondary side the output voltages are regulated via bidirectional switches. A typical application area of this converter is a power supply for a desktop PC. The TEA1781T and TEA1782T are secondary control ICs and regulate each output voltage independently of the primary duty cycle and other secondary output voltages. Because of these separated regulations, the system does not show any cross regulation and makes the design of the transformer easier. As each output can also be completely turned off, the system allows for an integrated standby supply. To maximize the efficiency in Standby mode, the duty cycle and operating frequency are minimized in Standby mode. The TEA1781T and TEA1782T have integrated drivers and individual output voltage regulators. In this way the 3.3 V, 5 V, 12 V and 5 V standby outputs of a typical PC power supply are regulated separately giving accurate output voltages and fast transient response. All requirements according to the Intel ATX specification (V 2.0) are integrated, such as soft start, a PS_ON# connection, a PwrOK signal and all required protections like OverCurrent Protection (OCP) and OverVoltage Protection (OVP). These voltage and current levels are monitored at each output separately. The system also has an OverTemperature Protection (OTP) function. The system fulfills the current and proposed efficiency standards such as 80+ gold, energy star and blue angel. The TEA1781T and TEA1782T are implemented in a high voltage (ABCD) Silicon On Insulator (SOI) process. 2. Features n n n n n n n n Designed for ATX PC power supplies Integrated standby supply Enhanced efficiency in Standby mode No cross regulation Accurate output voltage regulation Fast transient response Integrated soft start for all output voltages Flexible transformer design without the need of a post regulator TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs n n n n n n Overvoltage protection Overcurrent protection Overtemperature protection System failure detection Soft (re)start Low external component count 3. Applications n PC desktop power supply 4. Ordering information Table 1. Ordering information Type number Package Name Description Version TEA1781T SO28 Plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 TEA1782T SO28 Plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 2 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs 10 Enable 9 Temperature protection PWROK PGOOD VNTC ENABLE 5. Block diagram 22 18 PowerGood Soft Start start PowerOK Start-up IENABLE 4 VSTARTUP Vref(5V) Votp Vtrip(ENABLE) start 15 Vref(3V3) PGOOD Control 5 V I-control 5 V Vref(5V) Control 3.3 V I Vtrip I-control 3.3 V GND 13 GND Vref(3V3) V/I S V/I 14 I Q R V/I td VDD Vreg(VDD) Q R S Pull-down Protection 5 V Ipd Drive SR Drive 5 V VDD Protection 3.3 V Ipd 19 IO > Iocp Vovp(VOUT_5V) IO Iocp Vuvp(VOUT_5V) VDD IO > Iocp Vovp(VOUT_3V3) I Drive 3.3 V VSENSE_3V3 O Vuvp(VOUT_3V3) Vref(OCP) 21 20 CS_3V3 VOUT_3V3 GSF_3V3 PGND_3V3 FSB_3V3 DF_3V3 8 24 23 25 17 16 VSENSE_5V GSB_3V3 6 OCP 7 CS_5V VOUT_5V 11 12 6 GSF_5V 1 PGND_5V DF_5V 3 FSB_5V GSR 2 GSB_5V FSR WND_SEC_2 28 26 27 014aaa181 Fig 1. TEA1781T block diagram TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 3 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs EN_NM Pulldown Ipd ENABLE PS_OFF Enable NM VVDD > Vstartup(VDD) Digital control VVDD < Vstop(VDD) Startup VVDD > Vstartup(VDD) IENABLE > Iprot(ENABLE)+ EN_NM NORMAL VENABLE = 11 V PROT/STDB VENABLE = 4 V PS_OFF V/I I V/I OPTO start Vref(stb) start Vref(12V) system restart normal DOWN I-control standby PROT_12V PROT_STB I PGOOD V/I I Protection 12 V PowerGood Vref(stb) UVP_STB Control 12 V Vtrip V/I system failure detection SYSTEM RESTART EN_NM UP Soft Start Control 12 V I Opto control Vstartup(VDD) + PS_OFF+ PROT_12V + UVP_STB Vref(12V) GND GND VDD STARTUP VENABLE = 4 V VENABLE VEN_NM VDD Control standby td Vuvp(VOUT_12V1) 12 V OCP detection Drive 3.3 V Q R S Vovp(VOUT_12V1) Protection standby Q R IVOUT_12V2 Vuvp(VOUT_STB) S Drive SR IVOUT_12V Drive 12 V VDD IVOUT_STB > IOCP_STB IOCP_12V VDD Vovp(VOUT_STB) IVOUT_STB Drive standby IOCP_STB Vref(OCP) FSR GSB_12V DF_12V WND_SEC_1 Fig 2. GSF_12V CS_12V FSB_12V GSR VOUT_12V2 VOUT_12V1 GSB_STB OCP_12V Vref(OCP) FSB_STB DF_STB VOUT_STB PGND_STB GSF_STB OCP_STB CS_STB PGND_12V 014aaa182 TEA1782T block diagram 6. Pinning information 6.1 Pinning FSB_5V 1 28 FSR FSB_12V 1 28 FSR GSB_5V 2 27 GSR GSB_12V 2 27 GSR DF_5V 3 26 WND_SEC_2 DF_12V 3 26 WND_SEC_1 VSTARTUP 4 25 FSB_3V3 OCP_12V 4 25 FSB_STB OCP 5 24 GSB_3V3 CS_12V 5 24 GSB_STB CS_5V 6 23 DF_3V3 VOUT_12V1 6 23 DF_STB VOUT_5V 7 22 PGOOD VOUT_12V2 7 VSENSE_5V 8 21 CS_3V3 EN_NM 8 VNTC 9 20 VOUT_3V3 PS_OFF 9 19 VSENSE_3V3 ENABLE 10 TEA1781T ENABLE 10 18 PWROK PGND_5V 11 16 GSF_3V3 GND 13 GND 14 15 VDD GND 14 014aaa183 Fig 3. TEA1781T pin configuration 18 PGOOD 17 PGND_STB 16 GSF_STB 15 VDD 014aaa184 Fig 4. TEA1782T pin configuration TEA1781_82_1 Preliminary data sheet 21 CS_STB 19 OPTO GSF_12V 12 GND 13 22 OCP_STB 20 VOUT_STB PGND_12V 11 17 PGND_3V3 GSF_5V 12 TEA1782T © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 4 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs 6.2 Pin description Table 2. TEA1781T pin description Symbol Pin Description FSB_5V 1 floating supply switch SB_5V GSB_5V 2 gate driver switch SB_5V DF_5V 3 drain voltage of switch SF_5V VSTARTUP 4 start-up voltage connected to rectified secondary winding voltage OCP 5 overcurrent protection CS_5V 6 current sense 5 V output VOUT_5V 7 output voltage 5 V output VSENSE_5V 8 sense voltage 5 V output VNTC 9 NTC voltage ENABLE 10 enabling Normal mode PGND_5V 11 power ground 5 V output GSF_5V 12 gate driver switch SF_5V GND 13 ground GND 14 ground VDD 15 supply voltage GSF_3V3 16 gate driver switch SF_3V3 PGND_3V3 17 power ground 3V3 output PWROK 18 power OK VSENSE_3V3 19 sense voltage 3.3 V output VOUT_3V3 20 output voltage 3.3 V output CS_3V3 21 current sense 5 V output PGOOD 22 PowerGood (delay setting for power OK) DF_3V3 23 drain voltage of switch SF_3V3 GSB_3V3 24 gate driver switch SB_3V3 FSB_3V3 25 gate driver switch SB_3V3 WND_SEC_2 26 secondary transformer 3.3 V / 5 V winding voltage GSR 27 gate driver switch SR (3.3 V / 5 V) FSR 28 floating supply switch SR (3.3 V / 5 V) Table 3. TEA1782T Pin description Symbol Pin Description FSB_12V 1 floating supply switch SB_12V GSB_12V 2 gate driver switch SB_12V DF_12V 3 drain voltage of switch SF_12V OCP_12V 4 overcurrent protection 12 V output CS_12V 5 current sense 12 V output VOUT_12V1 6 output voltage 12 V1 output VOUT_12V2 7 output voltage 12 V2 output EN_NM 8 enable Normal mode TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 5 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs Table 3. TEA1782T Pin description …continued Symbol Pin Description PS_OFF 9 power supply off (via delay network connected to PS_ON#) ENABLE 10 enabling Normal mode PGND_12V 11 power ground 12 V output GSF_12V 12 gate driver switch SF_12V GND 13 ground GND 14 ground VDD 15 supply voltage GSF_STB 16 gate driver switch SF_stb PGND_STB 17 power ground standby output PGOOD 18 PowerGood (delay setting for power OK) OPTO 19 opto coupler VOUT_STB 20 output voltage standby output CS_STB 21 current sense standby output OCP_STB 22 overcurrent protection standby output DF_STB 23 drain voltage of switch SF_stb GSB_STB 24 gate driver switch SB_stb FSB_STB 25 gate driver switch SB_stb WND_SEC_1 26 secondary transformer 12 V / standby winding voltage GSR 27 gate driver switch SR (12 V) FSR 28 floating supply switch SR (12 V) 7. Functional description 7.1 Introduction A PC power supply has to supply a number of different supply voltages: 12 V, 5 V, 3.3 V, −12 V and 5 V standby. To achieve the required output voltage accuracy, the systems of today require dissipative post regulations. Because the system must be able to switch off the main supplies (12 V, 5 V, 3.3 V, −12 V) in Standby mode but keep the 5 V standby in operation, a separate standby supply is still common practice. With the GreenChip PC chip set (TEA1771T, TEA1781T, TEA1782T) a system configuration is introduced that integrates the post regulation and combines the main and standby converter into a single system. This high level of integration reduces the total cost of the system. Because the output voltages are regulated separately, it makes the design of the converter easier as none of the output voltages is directly related to the number of turns on the transformer. One of the main differences of this topology compared to commonly used solutions is the use of switches instead of Schottky diodes, although the rectifying switch is a so-called bidirectional switch. This switch is built up by two standard FETs in anti-series. TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 6 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs The freewheel switch behaves like an ideal diode so the setup runs in a discontinuous mode at low loads. Negative currents are avoided by the control ICs through this switch. Replacement of the rectifying Schottky diode by two switches in anti-series allows: • Integration of the 5 V standby supply, because in Standby mode the main secondary outputs can be switched off. The supply voltages can be individually and more accurately regulated, eliminating ubiquitous post regulators. • As the output voltages is now regulated by the secondary switches, the duty cycle of the primary control switch can be kept constant, preventing ringing at the primary reset voltage. A lower reset voltage results in lower required breakdown voltages of all applied FETs, both primary and secondary. This reduces costs. • The use of Zero Voltage Switching (ZVS) at the primary side to fulfill the required standby efficiency. To fulfill the ATX12V specification on standby efficiency requirements, the system has a Standby mode in which the frequency, duty cycle and supply currents are reduced. The TEA1781T and TEA1782T are secondary control ICs. Together with the TEA1771T primary controller they form a unique system that fulfills the 80+ gold requirements at minimum costs, eliminating any cross regulation and maximizing standby efficiency. 7.2 Supply When the voltage on the primary side from the rectified input mains reaches its starting value, the primary side starts up and switches the primary main switch. From that moment, the secondary rectified transformer voltage at Vstartup, see Figure 5, is a ratio of the input voltage. 12 V VVOUT_STB Start-up VSTARTUP VDD Start-up UVLO Vstartup(VDD) VDD TEA1781 TEA1782 014aaa185 Fig 5. Start-up sequence TEA1771T TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 7 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs The VDD capacitor is charged and regulated to the Vreg(VDD) level via a linear regulator in the TEA1781T. This VDD voltage is the supply voltage for both secondary ICs. Once the VDD voltage reaches the Vstartup(VDD) level, measured in the TEA1782T, the 5 V standby is started up via a so-called soft start. This implies that during a certain time, tstart(soft), the output voltage slowly ramps up from zero to the required value. Once the system is started up, the VDD voltage is taken over by an auxiliary winding of the 5 V standby output, as shown in Figure 5. This ensures an efficient 12 V VDD voltage during standby and normal operation. As the secondary ICs are supplied via the TEA1781T and measured in the TEA1782T, both ICs are disabled in case of an open connection in the supply chain. If the VDD voltage drops below its Vstop(VDD) level, the system disables all output voltages by actively turning off all switches. This avoids undefined conditions resulting from charged gate capacitances. 7.3 Mode of operation After the system has started up, the TEA1782T defines the mode of operation. It features four operation modes: Start-up mode, Protection/Standby mode, Normal mode and System restart mode, as depicted in Figure 6. Digital control VVDD < Vstop(VDD) STARTUP VENABLE = 4 V VVDD > Vstartup(VDD) IENABLE > Iprot(ENABLE)+ EN_NM + PS_OFF+ PROT_12V + UVP_STB NORMAL VENABLE = 11 V PROT/STDB VENABLE = 4 V PS_OFF SYSTEM RESTART system failure detection 014aaa186 Fig 6. State diagram TEA1771T When the VDD voltage is below its stop level, the TEA1782T enters the Start-up mode and the TEA1781T charges the VDD capacitors to Vreg(VDD) via the start-up pin. When it has charged the VDD capacitor above Vstartup(VDD), the TEA1782T jumps into Protection/Standby mode and the 5 V standby output slowly rises from zero to its required value. When the PS_OFF signal becomes active low, the system switches to Normal mode enabling the main outputs (3.3 V, 5 V, 12 V and −12 V). The 12 V (and −12 V) output is regulated by the TEA1782T itself, whereas the 3.3 V and 5 V output are regulated by the TEA1781T. The TEA1781T activates the 3.3 V and 5 V outputs via the ENABLE signal. TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 8 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs At any failure condition or as soon as the PS_OFF signal is high, the system switches to Protection / Standby mode. When a failure, such as a shorted or overloaded output, is detected, the system enters the Protection mode, disabling the main output circuits but leaving the standby output in operation. However, when, for example, a secondary FET is shorted, the system enters the System restart mode and switches off the primary side. When VDD is discharged below its minimum level, Vstop(VDD), the IC enters the Start-up mode and all switches are disabled. When the system is in Protection / Standby mode, the systems lowers its duty cycle and operating frequency to optimize the system’s efficiency. 7.4 Enable Normal mode In Standby mode, an optional PFC may be switched off. When switched to Normal mode, the system has a programmable delay before the main outputs (3.3 V, 5 V and 12 V) are switched on. During this delay the PFC can be activated. An extra safety feature has been built in when enabling Normal mode. If the input voltage is too low, which can occur when the PFC fails, the system stays in Standby mode. The input voltage is measured on a rectified secondary voltage, reflecting the input voltage; see Figure 7. Np / Ns VWND_SEC_2 Enable NM 1.25 V Digital control EN_NM 014aaa187 Fig 7. Enable Normal mode assures a proper start-up of the forward converter In addition to a minimum input voltage, a delay can also be made to assure a proper start-up of the PFC before the system switches to Normal mode. A circuit according to Figure 8 must be built between the PS_ON# signal from the motherboard and the PS_OFF pin of the TEA1782T. TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 9 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs 5 V standby D1 D2 R1 PS_ON# C1 R2 PS_OFF Digital control VVDD < Vstop(VDD) STARTUP VENABLE = 4 V VVDD > Vstartup(VDD) IENABLE > Iprot(ENABLE)+ EN_NM + PS_OFF+ PROT_12V + UVP_STB NORMAL VENABLE = 11 V PROT/STDB VENABLE = 4 V PS_OFF TEA1782 SYSTEM RESTART system failure detection 014aaa188 Fig 8. Enable Normal mode assures a proper start-up of the PFC 7.5 Soft start When the TEA1782T enters the Protection/Standby mode after start-up, the 5 V standby output is started up via a soft start. The main output voltages, 3.3 V, 5 V, 12 V and −12 V are started up via a soft start when the TEA1782T enters the Normal mode. A soft start implies that the outputs will rise gradually and simultaneously from zero to their required value during a defined period (≈ 15 ms). When PS_OFF is turned low, the main outputs of the TEA178x chip set ensure that power sequencing is applied according to the ATX12V specification of Intel, i.e., the 12 V and 5 V outputs must be equal to, or greater than, the 3.3 V output during power-up and normal operation. 7.6 Enable The TEA1782T is the master of the system. The required duty cycle is communicated to the primary controller TEA1771T via the opto coupler. The TEA1782T communicates to the TEA1781T via the enable signal, see Figure 9, if the main outputs are enabled or disabled. If the system is in Normal mode, the voltage of the enable signal exceeds the trip level, Vtrip(ENABLE), enabling all outputs. Otherwise the main outputs are disabled. TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 10 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs 3.3 V / 5 V outputs are enabled ENABLE Digital control VVDD < Vstop(VDD) Vtrip(ENABLE) VENABLE IENABLE + PS_OFF+ PROT_12V + UVP_STB protection 5 V protection 3.3 V VVDD > Vstartup(VDD) IENABLE > Iprot(ENABLE)+ EN_NM temp.prot TEA1781 STARTUP VENABLE = 4 V NORMAL VENABLE = 11 V PROT/STDB VENABLE = 4 V PS_OFF TEA1782 SYSTEM RESTART system failure detection 014aaa189 Fig 9. The ENABLE signal is for communicating between the secondary control ICs TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 11 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs 7.7 Output drivers Figure 10 shows a part of the secondary side output circuitry and the applied gate drive system. VWND_SEC_x + 12 V VINDC / N VWND_SEC_x VDD 0 Drive DF_x VFSB_x VDF_x 0 FSB_x GSB_x GSR_x FSR_x WND_SEC_x VINDC / N DF_x VVOUT_x SR VWND_SEC_x SB SF 014aaa190 (1) WND_SEC_x: The “x” stands for either 1 or 2 (2) FSR_x,, GSR_x, GSB_x, DF_x, FSB_x: The “x” for these pins and symbols stands for either 3V3, 5V or 12V (3) VOUT_x: The “x” stands for either 3V3, 5V, 12V1 or 12V2. Fig 10. Output driver circuit The freewheel switch SF is turned on and off between the VDD voltage (12 V) and ground level as the source of SF is connected to ground. The source of switch SB varies between zero (actually a small negative voltage when the SF or its back gate diode is conducting) and the maximum secondary transformer voltage. Therefore the driver of SB requires a bootstrap circuit. When VDF_x (VDF_3V3, VDF_5V, or VDF_12V) is (about) zero, the FSB capacitor is charged to the VDD level. Switch SB can then be turned on via this charged capacitor, as it ensures a VDD voltage with respect to DF_x (pins DF_3V3, DF_5V, or DF_12V). As this capacitor will be discharged when charging the gate source capacitance of SB, the driving voltage will be slightly less than the VDD voltage. The source of the rectifying switch SR is connected to the transformer, which can be positive or negative. Therefore the FSR capacitor is charged via a boost circuit with a special voltage source that is about 12 V higher than the secondary transformer voltage at the appropriate time. As the source of the rectifying switch SR is connected to the transformer, which can be either negative or positive, the TEA1781T and TEA1782T are developed in a special process (ABCD - SOI) which is capable of handling these (high) negative and positive voltages. TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 12 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs 7.8 Output voltage regulation The output voltage is regulated to the required voltage level via a current mode control loop. ResetSB VWND_SEC_x 0 −Vrst / N Vref I-control Q R I "1" S ResetSB V/I I Control VINDC / N "0" closed SB closed SF CS_x R C L SR SB open VOUT_x GSF_x DF_x VDD FSB_x GSB_x Drive VWND_SEC_x open VVOUT_x SF 014aaa191 (1) WND_SEC_x: The “x” stands for either 1 or 2 (2) GSB_x, DF_x, FSB_x, GSF_x, CS_x: The “x” for these pins and symbols stands for either 3V3, 5V or 12V (3) VOUT_x: The “x” stands for either 3V3, 5V, 12V1 or 12V2. Fig 11. Output voltage regulation When the secondary side transformer voltage is negative, switch SB is turned off to avoid negative currents, see Figure 11. Once the secondary side transformer voltage is positive and the output current in the secondary coil has dropped below a certain value, switch SB is turned on again. This value is proportional to the difference between the output voltage and the reference voltage, increased with a ramp voltage. This type of regulation is called current mode control. A ramp voltage is required to stabilize the control loop for duty cycles smaller than 0.5 and is called slope compensation. The output current is measured using the output inductor series resistance. When the L parallel RC network is R ⋅ C = ------ the voltage across the parallel capacitor equals the RL voltage across the inductors resistance. L and RL represent the inductance and the resistance value of the output inductor. TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 13 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs 7.9 PowerOK The PowerOK signal is active HIGH when the main output voltages (12 V, 5 V and 3.3 V) are within their regulation limits. Figure 12 shows the corresponding block diagram. VDD 5 V standby PWROK PWROK PGOOD PowerOK PGOOD PowerGood PowerGood VPGOOD TEA1782 Protection 5 V Protection 3.3 V Vuvp VOUT_5V Vuvp VOUT_3V3 Protection 12 V TEA1781 Vuvp VOUT_12V 014aaa192 Fig 12. PowerOK circuit diagram The PGOOD output is pulled down by the TEA1781T when either the 5 V or 3.3 V is below its lower limit, or by the TEA1782T when the 12 V is below its lower limit. When all main outputs are above their minimum value, the PGOOD signal slowly rises from zero to the VDD level. Once the PGOOD signal exceeds VPGOOD, the PWROK signal becomes active high. A delay can be set between the output voltages reaching their end value and the PWROK signal being active high via an RC network connected to the PGOOD pins. 7.10 Pull-down main outputs According to the Intel ATX specification, the main outputs (3.3 V, 5 V and 12 V) must be at ground level in Standby mode. Therefore, these outputs are pulled low when the system is in Standby mode. The pull-down transistors for the 3.3 V and 5 V outputs are integrated in the TEA1781T, whereas the pull-down transistor for the 12 V is integrated in the TEA1782T. 7.11 OPTO control The TEA1782T defines the mode of operation of the system. It communicates with the TEA1781T via the ENABLE pin and with the TEA1771T primary controller via the opto coupler connected to the OPTO control block. Depending on the mode of operation, the current to the opto coupler has the following values: TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 14 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs Table 4. OPTO control modes Mode of operation IOPTO Standby mode 0 mA to ≈ 3.5 mA Normal mode ≈ 3.5 mA System restart ≈ 30 mA In Standby mode, a higher IOPTO current implies a higher duty cycle / frequency of the system. In Normal mode, the systems duty cycle/frequency is defined by the primary controller being related to the inverse of the input voltage. The OPTO control block diagram is given in Figure 13. off PVCC OPTO control UP S1 S3 S4 I DOWN S2 OPTO V/I Normal mode 014aaa193 Fig 13. TEA1782T OPTO control diagram At system start-up, the secondary controllers are supplied via a rectified secondary winding voltage. Therefore the secondary controllers are started up after the primary side has started up. As the voltage at the OPTO pin is zero when the secondary controllers are not yet supplied, the primary side starts up at the minimum duty cycle/frequency. Once the secondary side has started, it increases the operating duty cycle/frequency of the system depending on the standby load and mode of operation. When the system is in Normal mode, switch S3 is closed and the opto coupler current is increased to IOPTO (Normal mode). In this mode, the primary duty cycle is defined by the primary controller TEA1771T and is related to the inverse of the input voltage. When the secondary protection mode fails, switch S4 is closed and a maximum current flows through the opto coupler. This high current triggers the primary controller into Protection mode, switching off the primary main switch. A safe restart of the system will follow. This implies that the system will start up again after all the supply voltages, primary and secondary, are below their UVLO levels resulting in a total reset of the system. In Standby mode, the system minimizes the duty cycle of the primary control switch to reduce the magnetic losses in the transformer to a minimum. As the primary duty cycle has to be at least equal to the secondary duty cycle, the system will equalize both duty cycles in Standby mode. This is regulated in the opto control block. TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 15 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs The opto control compares the primary and secondary standby duty cycle and defines if the primary duty cycle has to be changed, see Figure 14. closed S1 primairy main switch open VINDC / N VWND_SEC_1 0 −Vrst / N closed SB open decreasing prim δ "1" down "0" increasing prim δ "1" up "0" IOPTO 014aaa194 Fig 14. TEA1782T OPTO control duty cycles The primary duty cycle is derived from the secondary transformer voltage. If VWND_SEC_1 is above a certain positive level before the switch SB is turned on, a down pulse is generated. An up pulse is generated when VWND_SEC_1 is high after SB is turned on. The current into the opto coupler is regulated until it reaches a stable value via the down pulse and up pulse. Through the opto coupler, the primary duty cycle and frequency eventually stabilize to provide the duty cycle required by the secondary standby converter. 7.12 Protections 7.12.1 General All outputs have an OVP and an OCP function. The OVP and OCP functions have a delay of td(prot), which is typically 18 µs. If the output voltage or the output current on one of the main outputs (3.3 V, 5 V, 12 V1, or 12 V2) exceeds their upper limit, the system will enter Protection mode. In this mode all main outputs are switched off by switching off all corresponding secondary switches. The system will enter the Normal mode again after toggling the PS_ON# signal or after a mains interruption. A 12 V OVP / OCP is detected in the TEA1782T. When detecting a 12 V OVP or OCP, the pin ENABLE is pulled down and as a result both the TEA1782T and the TEA1781T will disable the main outputs. The 5 V standby output remains on. A 3.3 V or 5 V OVP or OCP is detected in the TEA1781T and communicated to the TEA1782 via the pin ENABLE. As a result the TEA1782T will pull down the pin ENABLE, disabling all main outputs. TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 16 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs When the 5 V standby voltage / current exceeds its upper limit the output will be switched off. It will be turned on again at the next cycle as soon as the output voltage/current level drops below the upper limit. 7.12.2 Undervoltage protection When undervoltage is detected on one of the main outputs (3.3 V, 5 V, 12 V) the pin PGOOD is pulled low which again pulls the PWROK signal low. When undervoltage on the 5 V standby output is detected, the system switches to Standby mode and returns back to Normal mode once the 5 V standby is above its minimum level. 7.12.3 Overvoltage protection As stated previously, all outputs have an OVP function. However, the 12 V1 and 12 V2 have one OVP function. It is assumed that the 12 V2 is directly coupled to the 12 V1 voltage and therefore these voltages are about equal. All OVP levels are integrated and cannot be set externally. 7.12.4 Overcurrent protection The OCP levels can be set externally. The maximum output current of the 12 V1 and 12 V2 are supposed to be about equal, therefore have the same OCP setting. Figure 15 gives the 12 V OCP block diagram. TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 17 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs Protection mode Protection 12 V IVOUT_12V − 2 × IVOUT_12V2 > Iocp_12V or 2 × IVOUT_12V2 > Iocp_12V Vovp(VOUT_12V1) IVOUT_12V2 TEA1782 IVOUT_12V Iocp_12V Vref(OCP) CS_12V VOUT_12V1 VOUT_12V2 OCP_12V VVOUT_12V1 VVOUT_12V2 014aaa195 Fig 15. 12 V output overcurrent protection The total output current (equal to Iout_12V1 + Iout_12V2) is measured via an RC network across the output inductor, using the series resistance of the output inductor. The 12V2 output current is measured using a series resistance. Subtracting these two then gives the 12V1 output current. Both output currents are then compared to the Iocp (12 V output) setting. If one of these currents exceeds the Iocp (12 V output) setting, the system will enter the Protection mode.The system supposes the extra series resistance to be half the value of the inductor series resistance. The Iocp (12 V output) has a default setting of −100 µA, corresponding to 180 mV for 12V1, and 90 mV for 12V2. Applying a series resistance of 5 mΩ and an inductor series resistance of 10 mΩ, the default OCP levels of the 12 V outputs are set at 18 A. The OCP levels of the 12 V outputs can be increased by a resistor from pin OCP_12V to ground and decreased by a resistor from pin VDD to pin OCP_12V. The 3.3 V and 5 V OCP can be adjusted externally, whereas the system assumes identical 3.3 V and 5 V OCP levels, see Figure 16. The output currents are measured via an RC network across the output inductor, making use of the inductor series resistance. If either the 5 V or 3.3 V output exceeds its OCP setting, the system enters the Protection mode. TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 18 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs Protection mode Protection mode Protection 5 V Vovp(VOUT_5V) IVOUT_5V Protection 3.3 V IVOUT_5V > Iocp IVOUT_3V3 > Iocp Vovp(VOUT_3V3) IVOUT_3V3 Iocp CS_3V3 VOUT_3V3 OCP CS_5V VOUT_5V Vref(OCP) VVOUT_5V VVOUT_3V3 014aaa196 Fig 16. 3.3 V / 5 V output overcurrent protection The Iocp has a default setting of −100 µA. Applying an inductor series resistance of 10 mΩ, the default OCP level is set at 19.5 A. The OCP levels of 3.3 V and 5 V can be increased by a resistor from pin OCP to ground and decreased by a resistor from pin VDD to pin OCP. The 5 V standby OCP level is set to approximately 2.5 A, assuming an inductors series resistance of 70 mΩ. The OCP_STB level can be increased by a resistor from pin OCP_STB to ground and decreased by a resistor from pin VDD to pin OCP_STB. Besides changing the OCP level by a resistor connected to the OCP pin, this level can be changed by choosing a different series resistance of the output coil. Whereas an OCP on one of the main outputs results in a latched Protection mode, a 5 V standby OCP also disables the output but resumes switching at the next cycle when the output current drops below the OCP level. When the 5 V standby output voltage drops below its minimum level, because the output current is limited, the system switches to Standby mode. 7.12.5 Overtemperature protection The system will enter the Protection mode at an initialized temperature level via an external NTC network connected to the VNTC pin of the TEA1781T. In this way the system can be protected against overtemperature. TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 19 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs If an OTP is detected all main outputs will be switched off, but the 5 V standby output remains on. 7.12.6 System restart If an OCP, OVP, or OTP is detected on one of the main outputs, all these outputs are switched off and latched. A OCP or OVP detection on the 5 V standby will switch off its output but it will be resumed again at the next cycle. All outputs can be disabled individually by disabling the bidirectional switch (SR / SB). Disabling an output will resolve the reason why Protection mode was entered, which can be an OVP, OCP or OTP. If a certain time after entering Protection mode (td(restart) (≈ 500 µs)) the system still detects an OCP or OVP, the secondary side enters the system restart mode. In this mode the primary side is switched off via the opto coupler, followed by a safe restart. A continuous error could be caused by a shorted SB switch, for example. If a small increase of temperature is detected because of an OTP after entering Protection mode, the system will also turn off the primary side. So normally, an OCP, OVP or OTP will switch off the secondary outputs. Only when an OCP, OVP or OTP remains after the outputs are switched off, will the primary side be switched off. In that case the 5 V standby output will also drop. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit TEA1781T VDF_5V voltage on pin DF_5V −7 +40 V VVSTARTUP voltage on pin VSTARTUP −0.4 +75 V Iocp overcurrent protection current −250 +80 µA VCS_5V voltage on pin CS_5V −0.4 +7 V VVOUT_5V voltage on pin VOUT_5V −0.4 +7 V VVSENSE_5V voltage on pin VSENSE_5V −0.4 +7 V VVNTC voltage on pin VNTC −0.4 +7 V VENABLE voltage on pin ENABLE −0.4 +13 V VPGND_5V voltage on pin PGND_5V -0.8 +0.8 V VDD supply voltage −0.4 +13 V VPGND_3V3 voltage on pin PGND_3V3 −0.8 +0.8 V VPWROK voltage on pin PWROK −0.4 +13 V TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 20 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs Table 5. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VVSENSE_3V3 Conditions Min Max Unit voltage on pin VSENSE_3V3 −0.4 +7 V VVOUT_3V3 voltage on pin VOUT_3V3 −0.4 +7 V VCS_3V3 voltage on pin CS_3V3 −0.4 +7 V VPGOOD voltage on pin PGOOD −0.4 +7 V VDF_3V3 voltage on pin DF_3V3 −7 +40 V VWND_SEC_2 voltage on pin WND_SEC_2 −40 +40 V - <tbd> W −55 +150 °C −20 +145 °C −2000 +2000 V −200 +200 V - 500 V General Ptot total power dissipation Tstg storage temperature Tj junction temperature Vesd Tamb < 45 °C electrostatic discharge human body voltage all pins model:[1] machine model:[2] all pins charged device model TEA1782T VDF_12V voltage on pin DF_12V -7 +73 V IOCP_12V current on pin OCP_12V −250 +80 µA VCS_12V voltage on pin CS_12V with respect to VVOUT_12V1 −0.4 +0.8 V VVOUT_12V1 voltage on pin VOUT_12V1 −0.4 +0.4 V VVOUT_12V2 voltage on pin VOUT_12V2 −0.4 +13.4 V VEN_NM voltage on pin EN_NM −0.4 +13 V VPS_OFF voltage on pin PS_OFF −0.4 +13 V VPGND_12V voltage on pin PGND_12V −0.8 +0.8 V VDD supply voltage −0.4 +13 V VPGND_STB voltage on pin PGND_STB −0.8 +0.8 V VPGOOD voltage on pin PGOOD −0.4 +13 V VVOUT_STB voltage on pin VOUT_STB −0.4 +7 V VCS_STB voltage on pin CS_STB −0.4 +7 V IOCP_STB current on pin OCP_STB −250 +80 µA with respect to VVOUT_12V2 TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 21 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs Table 5. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDF_STB VWND_SEC_1 Conditions Min Max Unit voltage on pin DF_STB −0.8 +73 V voltage on pin WND_SEC_1 −73 +73 V - <tbd> W General Tamb < 45 °C Ptot total power dissipation Tstg storage temperature −55 +150 °C Tj junction temperature −20 +145 °C Vesd electrostatic discharge human body model:[1] voltage all pins −1500 +1500 V machine model:[2] all pins −150 charged device model +150 V +500 V [1] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor. [2] Machine model: equivalent to discharging a 200 pF capacitor through a 0.75 µH coil and a 10 Ω series resistor. [3] Peak voltages up to the OVP level are allowed. 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Rth(j-a) thermal resistance from junction to ambient in free air [1] Typ Unit <tbd> K/W Thermal resistance Rth(j-a) can be lower when pin GND is connected to sufficient copper area on the printed-circuit board. See the TEA1771T application notes for details. TEA1781_82_1 Preliminary data sheet [1] © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 22 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs 10. Characteristics Table 7. TEA1781T characteristics Tamb = 25 °C; no over temperature; all voltages are measured with respect to ground; currents are positive when flowing into the IC; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Vreg(VDD) regulation voltage on pin VDD Vstartup = 14 V to 90 V 9.0 9.5 10.1 V IVDD current on pin VDD Standby mode - 1.2 - mA Normal mode - 1.9 - mA SR / SB drivers; VWND(SEC)_2 = VDF_3V3 = VDF_5V = 40 V; VFSR = VFSB_3V3 = VFSB_5V = 52 V; VGSB_3V3 = VGSB_5V = VGSR = 51.5 V 13 17 21 Ω SF drivers; VDF_3V3 = VDF_5V = −1 V; VVDD − VGSF_3V3 (or VGSF_5V) = 0.5 V - 30 - Ω SR / SB drivers; VWND(SEC)_2 = VDF_3V3 = VDF_5V = 40 V; VFSR = VFSB_3V3 = VFSB_5V = 52 V; VGSB_3V3 = VGSB_5V = VGSR = 40.5 V 3.5 4.5 5.5 Ω SF driver; VDF_3V3 = VDF_5V = 0 V; VGSF_3V3 = VGSF_5V = 0.5 V 3.5 4.5 5.5 Ω undervoltage lockout floating voltage SR/SB driver 5.0 5.4 5.8 V LOW-level trip voltage enable GSB; voltage on pin WND_SEC_2 −4.7 −4.1 −3.5 V enable GSR; voltage on pin DF (3.3 V and 5 V) 3.4 4.5 5.6 V enable GSB; voltage on pin WND_SEC_2 −2.2 −1.9 −1.6 V enable GSR; voltage on pin DF (3.3 V and 5 V) 5.8 7.0 8.2 V delay time enable GSB - 0.9 - µs reference voltage (3.3 V) VCS_3V3 = VVOUT 3.25 3.35 3.45 V VCS_3V3 = VVOUT + 100 mV 3.19 3.29 3.39 V VCS_5V = VVOUT 4.95 5.10 5.25 V VCS_5V = VVOUT + 100 mV 4.85 5.00 5.15 V Standby mode; VVOUT_3V3 = VVOUT_5V = 0.4 V 2 4 6 mA 7.0 8.0 9.0 V Supply Drivers Rpu Rpd Vfloat(UVLO) pull-up resistance pull-down resistance Control Vtrip(L) Vtrip(H) td HIGH-level trip voltage I-Control 3.3 V Vref(3V3) I-Control 5 V Vref(5V) reference voltage (5 V) Pins VOUT_3V3 and VOUT_5V Ipd pull-down current Enable Vtrip(ENABLE) trip voltage on pin ENABLE TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 23 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs Table 7. TEA1781T characteristics …continued Tamb = 25 °C; no over temperature; all voltages are measured with respect to ground; currents are positive when flowing into the IC; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit IENABLE current on pin ENABLE current pulled out of the pin ENABLE to disable, to move to Protection mode 1.0 - - mA 10 15 20 ms 6.0 - - mA Soft start tstart(soft) soft start time PGOOD and PWROK Isink(PGOOD) sink current on pin PGOOD VPGOOD = 0.4 V Vtrip(H)(PGOOD) HIGH-level trip voltage on pin PGOOD 2.5 2.7 3.0 V Vtrip(L)(PGOOD) LOW-level trip voltage on LOW pin PGOOD 2.2 2.4 2.7 V Isink(PWROK) sink current on pin PWROK VPWROK = 0.4 V 16 - - mA 1.21 1.25 1.29 V Overcurrent protection Vref(OCP) reference voltage on pin OCP OCP = n.c. Vocp overcurrent protection voltage VCS_x − VVOUT activating current protection; OCP = n.c. [1] 155 180 205 mV VCS_x − VVOUT activating current protection; Iocp = −100 µA [1] 320 380 440 mV VCS_x − VVOUT activating current protection; Iocp = 50 µA [1] 60 80 105 mV VCS_x − VVOUT activating current protection during soft start; OCP = n.c. [1] 310 360 410 mV Undervoltage/overvoltage protection Vuvp(VOUT_3V3) undervoltage protection voltage on pin VOUT_3V3 2.60 2.80 3.00 V Vuvp(VOUT_5V) undervoltage protection voltage on pin VOUT_5V 4.00 4.25 4.50 V Vovp(VOUT_3V3) overvoltage protection voltage on pin VOUT_3V3 3.76 4.00 4.25 V Vovp(VOUT_5V) overvoltage protection voltage on pin VOUT_5V 6.00 6.40 6.80 V Temperature protection Votp(H) HIGH-level overtemperature protection voltage VENABLE = 12 V 450 505 560 mV Votp(L) LOW-level overtemperature protection voltage VENABLE = 0 V 320 375 430 mV [1] VCS_x: the “x” stand for either “3V3” or ”5V”. TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 24 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs Table 8. TEA1782T characteristics Tamb = 25 °C; no over temperature; all voltages are measured with respect to ground; currents are positive when flowing into the IC; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supply Vstartup(VDD) start-up voltage on pin VDD 8.0 8.5 9.0 V Vstop(VDD) stop voltage on pin VDD 6.9 7.4 7.9 V IVDD current on pin VDD - 3.0 - mA td(startup) start-up delay time 5 7 9 ms Driver SF standby Rpu pull-up resistance SF driver; VDF_12V = VDF_STB = −1 V; VVDD − VGSF_12V (or VGSF_STB) = 0.5 V - 35 - Ω Rpd pull-down resistance SF driver; VDF_12V = VDF_STB = 0 V; VGSF_12V = VGSF_STB = 0.5 V 5.0 6.5 8.0 Ω SR / SB drivers; VWND(SEC)_1 = VDF_12V = VDF_STB = 73 V; VFSR = VFSB_12V = VFSB_STB = 85 V; VGSR = VGSB_12V = VGSB_STB = 84.5 V 13 17 21 Ω SF driver; VDF_12V = VDF_STB = −1 V; VVDD − VGSF_12V (or VGSF_STB) = 0.5 V - 30 - Ω SR / SB drivers; VWND(SEC)_1 = VDF_12V = VDF_STB = 73 V; VFSR = VFSB_12V = VFSB_STB = 85 V; VGSR = VGSF_12V = VGSF_STB = 73.5 V 3.5 4.5 5.5 Ω VDF_12V = VDF_STB = 0 V; VGSF_12V = VGSF_STB = 0.5 V 3.5 4.5 5.5 Ω 5.0 5.4 5.8 V Drivers (12 V and SB standby) Rpu Rpd Vfloat(UVLO) pull-up resistance pull-down resistance undervoltage lockout floating voltage Control standby Vtrip(L) LOW-level trip voltage enable GSB standby; voltage on pin WND_SEC_1 1.0 2.0 3.0 V Vtrip(H) HIGH-level trip voltage enable GSB standby; voltage on pin WND_SEC_1 8.0 9.0 10.0 V LOW-level trip voltage enable GSB 12 V; voltage on pin WND_SEC_1 −12.5 −11 −9.5 V enable GSR; voltage on pin DF 3.8 4.6 5.4 V −5.5 −5.0 −4.5 V Control 12 V Vtrip(L) Vtrip(H) HIGH-level trip voltage enable GSB 12 V; voltage on pin WND_SEC_1 enable GSR; voltage on pin DF 6.4 7.2 8.0 V td delay time enable GSB 12 V 0.7 0.9 1.1 µs 4.85 5.00 5.15 V 4.7 4.9 5.1 V I-control standby Vref(stb) standby reference voltage VCS_x = VVOUT + 100 mV TEA1781_82_1 Preliminary data sheet [1] © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 25 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs Table 8. TEA1782T characteristics …continued Tamb = 25 °C; no over temperature; all voltages are measured with respect to ground; currents are positive when flowing into the IC; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit I-Control 12 V Vref(12V) reference voltage (12 V) 11.7 12.1 12.4 V 11.5 11.9 12.3 V 4 6 8 mA 1.14 1.20 1.26 V system to Standby mode 0.66 0.70 0.74 V Normal mode 1.0 1.2 1.4 V Standby mode 1.4 1.7 2.0 V voltage on pin ENABLE Normal mode 10.5 11.0 11.5 V Standby mode 3.8 4.2 4.6 V protection current on pin ENABLE Normal mode; Protection mode −600 −450 −300 µA 10 15 20 ms 6.0 - - mA Standby mode 0 - IOPTO (Normal mode) mA Normal mode −4.5 −3.5 −2.5 mA system restart −40 −30 −20 mA 1.18 1.23 1.28 V VCS_x = VVOUT + 100 mV [1] Pins VOUT_12V and VOUT_STB Ipd pull-down current Standby mode; VOUT_12V = VOUT_STB = 0.4 V Enable Normal mode VEN_NM voltage on pin EN_NM Digital control pin PS_OFF Vtrip trip voltage Enable VENABLE Iprot(ENABLE) Soft start tstart(soft) soft start time PowerGood and PowerOK Isink(PGOOD) sink current on pin PGOOD VPGOOD = 0.4 V current on pin OPTO VOPTO = 5 V OPTO control IOPTO Overcurrent protection (OCP levels for 12 V2 are half the values given below) Vref(OCP_12V) reference voltage on pin OCP_12V Vref(OCP_STB) reference voltage on pin OCP_STB TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 26 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs Table 8. TEA1782T characteristics …continued Tamb = 25 °C; no over temperature; all voltages are measured with respect to ground; currents are positive when flowing into the IC; unless otherwise specified. Symbol Min Typ Max Unit VCS_x - VVOUT activating current protection; OCP = n.c. (Can VCS be changed to e.g. VCS_12V or VCS_STB here. If so, then that is preferred here.) [1] 155 180 205 mV VCS_x − VVOUT activating current protection; IOCP = −100 mA (Can VCS be changed to e.g. VCS_12V or VCS_STB here. If so, then that is preferred here.) [1] 320 380 440 mV VCS_x − VOUT activating current protection; IOCP = +50 mA (Can VCS be changed to e.g. VCS_12V or VCS_STB here. If so, then that is preferred here.) [1] 60 80 105 mV VCS_STB − VVOUT_STB activating current protection during soft start; OCP_STB = n.c. 230 270 310 mV VCS_12V − VVOUT_12V activating current protection during soft start; OCP_12V = n.c. 310 360 410 mV 3.90 4.25 4.60 V Vuvp(VOUT_12V1) undervoltage protection voltage on pin VOUT_12V1 9.70 10.20 10.70 V Vovp(VOUT_STB) 5.70 6.10 6.50 V 13.7 14.5 15.2 V protection delay time 9 18 27 µs restart delay time 275 550 825 µs Vocp Parameter overcurrent protection voltage Conditions Undervoltage protection/overvoltage protection Vuvp(VOUT_STB) undervoltage protection voltage on pin VOUT_STB overvoltage protection voltage on pin VOUT_STB Vovp(VOUT_12V1) overvoltage protection voltage on pin VOUT_12V1 Protection td(prot) System restart td(restart) [1] VCS_x: The “x” stands for either “12V” or “STB” TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 27 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs 11. Application information SR SB_3V3 VOUT_3V3 PWROK 1 2 3 4 5 6 7 8 GSF_3V3 VDD GND ntc GND PWROK VSENSE_3V3 PGND_3V3 GSF_5V PGND_5V VNTC VSENSE_5V VOUT_5V CS_5V OCP VSTARTUP DF_5V GSB_5V FSB_5V TEA1781 ENABLE CS_3V3 CS_3V3 DF_3V3 PGOOD FSB_3V3 GSB_3V3 WND_SEC_2 FSR GSR 28 27 26 25 24 23 22 21 20 19 18 17 15 14 9 10 11 12 13 14 VOUT_5V SB_5V SF_5V SB_STB SF_STB VOUT_STB GSF_STB VDD GND GND PGND_STB OPTO PGOOD ENABLE CS_STB VOUT_STB PS_OFF DF_STB OCP_STB GSB_STB WND_SEC_1 FSB_STB FSR GSR 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PS_ON# 1 2 3 4 5 6 7 8 GSF_12V PGND_12V EN_NM VOUT_12V2 VOUT_12V1 CS_12V OCP_12V DF_12V SR GSB_12V FSB_12V TEA1782 9 10 11 12 13 14 VOUT_12V2 VOUT_12V1 SB_12V SF_12V 014aaa755 Fig 17. Application diagram TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 28 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs 12. Package outline SO28: plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 D E A X c y HE v M A Z 15 28 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 e bp 0 detail X w M 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 18.1 17.7 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.71 0.69 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT136-1 075E06 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 18. Package outline SOT136-1 (SO28) TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 29 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs 13. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes TEA1781_82_1 20090213 Preliminary data sheet - - TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 30 of 32 TEA1781T; TEA1782T NXP Semiconductors GreenChip PC secondary control ICs 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 14.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. GreenChip — is a trademark of NXP B.V. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] TEA1781_82_1 Preliminary data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 13 February 2009 31 of 32 NXP Semiconductors TEA1781T; TEA1782T GreenChip PC secondary control ICs 16. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.12.1 7.12.2 7.12.3 7.12.4 7.12.5 7.12.6 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Mode of operation. . . . . . . . . . . . . . . . . . . . . . . 8 Enable Normal mode . . . . . . . . . . . . . . . . . . . . 9 Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output drivers . . . . . . . . . . . . . . . . . . . . . . . . . 12 Output voltage regulation . . . . . . . . . . . . . . . . 13 PowerOK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pull-down main outputs . . . . . . . . . . . . . . . . . 14 OPTO control . . . . . . . . . . . . . . . . . . . . . . . . . 14 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Undervoltage protection . . . . . . . . . . . . . . . . . 17 Overvoltage protection . . . . . . . . . . . . . . . . . . 17 Overcurrent protection . . . . . . . . . . . . . . . . . . 17 Overtemperature protection . . . . . . . . . . . . . . 19 System restart . . . . . . . . . . . . . . . . . . . . . . . . 20 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 20 Thermal characteristics. . . . . . . . . . . . . . . . . . 22 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 23 Application information. . . . . . . . . . . . . . . . . . 28 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 30 Legal information. . . . . . . . . . . . . . . . . . . . . . . 31 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 31 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Contact information. . . . . . . . . . . . . . . . . . . . . 31 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 13 February 2009 Document identifier: TEA1781_82_1