INTEGRATED CIRCUITS DATA SHEET TDA8779 10-bit converter interface (ADC/DAC) for quadrature transceiver Objective specification Supersedes data of 1996 Sep 05 File under Integrated Circuits, IC02 1996 Sep 18 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver TDA8779 FEATURES GENERAL DESCRIPTION • Two 10-bit ADCs with multiplexed outputs The TDA8779 contains two 10-bit high speed ADCs and two 10-bit DACs for wireless communication (for use in transceiver modules). This device converts two analog input signals (channels I and Q) and digital inputs (D0 to D9) at a maximum sampling rate of 20 MHz. The input bias voltages for the analog input voltages are provided internally at the middle code. The analog input and output voltages are AC coupled. • Two 10-bit DACs with multiplexed inputs • Sampling rate for the ADCs and DACs up to 20 MHz • Digital outputs (for the ADC) and inputs (for the DAC) are TTL/CMOS compatible (2.7 to 5.5 V) • Internal reference voltage regulator • Power dissipation 520 mW • Standby mode. The data sampling is performed on the rising edge of the clock for ADCs and DACs. APPLICATIONS All reference voltages are generated internally. Wireless communication. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCCA1 analog supply voltage for the ADC part 4.75 5.0 5.5 V VCCD1 digital supply voltage for the ADC part 4.75 5.0 5.5 V VCCA2 analog supply voltage for the DAC part 4.75 5.0 5.5 V VCCD2 digital supply voltage for the DAC part 4.75 5.0 5.5 V VCCO output stage supply voltage 2.7 3.0 5.5 V ICCA analog supply current − 71 − mA ICCD digital supply current − 31 − mA ICCO output stage supply current − 2 − mA fCLK(ADC)max maximum clock frequency for the ADC part 20 − − MHz INLA integral non linearity for the ADC part full-scale; ramp input; fCLK = 20 MHz − ±2 − LSB DNLA differential non linearity for the ADC part 50% full-scale; ramp input; fCLK = 20 MHz − ±0.3 − LSB fCLK(DAC)max maximum clock frequency for the DAC part 20 − − MHz INLD integral non linearity for the DAC part full-scale; ramp input; fCLK = 20 MHz − ±2 − LSB DNLD differential non linearity for the DAC part full-scale; ramp input; fCLK = 20 MHz − ±0.75 − LSB Ptot total power dissipation − 520 − mW 1996 Sep 18 ramp input; fCLK = 20 MHz 2 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver TDA8779 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8779H QFP44 DESCRIPTION VERSION SOT307-2 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm BLOCK DIAGRAM VCCA1 handbook, full pagewidth 7 INPUT BIAS DEC1 DEC2 2 DEC3 3 VCCD1 DGND1 31 28 5 REFERENCE REGULATOR STDBYA 29 TDA8779 32 INI 4 10 10-BIT ADC MUX INQ 6 10 10-BIT ADC 10 BUFFER 10 LATCHES 34-43 44 30 AGND1 1 26 BUFFER OUTI 9 10 10-BIT DAC 10 AGND2 10-BIT DAC 13 REFERENCE REGULATOR VCCA2 10 DEC4 12 DEC5 14 VCCD2 Fig.1 Block diagram. 1996 Sep 18 VCCO CLKA CLKD BUFFER 10 15-24 D0D to D9D 10 11 8 D0A to D9A 33 OGND LATCHES BUFFER OUTQ OE 3 25 DGND2 27 STDBYD MGG075 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver TDA8779 PINNING SYMBOL PIN DESCRIPTION SYMBOL PIN DESCRIPTION AGND1 1 analog ground 1 D9D 24 multiplexed input for the DACs; bit 9 DEC1 2 decoupling input 1 DGND2 25 digital ground 2 DEC2 3 decoupling input 2 CLKD 26 transmission block clock INI 4 I channel ADC input STDBYD 27 DEC3 5 decoupling input 3 power standby for the DAC part (active HIGH) INQ 6 Q channel ADC input DGND1 28 digital ground 1 VCCA1 7 analog supply voltage 1 for ADC part (+5 V) STDBYA 29 power standby for the ADC part (active HIGH) VCCA2 8 analog supply voltage 2 for DAC part (+5 V) CLKA 30 reception block clock VCCD1 31 digital supply voltage 1 for ADC part (+5 V) OE 32 ADCs digital output enable (3-state output); (active LOW) OGND 33 input/output ground D0A 34 I and Q digital outputs; bit 0 D1A 35 I and Q digital outputs; bit 1 D2A 36 I and Q digital outputs; bit 2 37 I and Q digital outputs; bit 3 OUTI 9 I channel DAC analog output DEC4 10 decoupling input 4 OUTQ 11 Q channel DAC analog output DEC5 12 decoupling input 5 AGND2 13 analog ground 2 VCCD2 14 digital supply voltage 2 for DAC part (+5 V) D0D 15 multiplexed input for the DACs; bit 0 D3A D1D 16 multiplexed input for the DACs; bit 1 D4A 38 I and Q digital outputs; bit 4 D2D 17 multiplexed input for the DACs; bit 2 D5A 39 I and Q digital outputs; bit 5 D3D 18 multiplexed input for the DACs; bit 3 D6A 40 I and Q digital outputs; bit 6 41 I and Q digital outputs; bit 7 D4D 19 multiplexed input for the DACs; bit 4 D7A D5D 20 multiplexed input for the DACs; bit 5 D8A 42 I and Q digital outputs; bit 8 D6D 21 multiplexed input for the DACs; bit 6 D9A 43 I and Q digital outputs; bit 9 VCCO 44 output supply voltage (2.7 to 5.5 V) D7D 22 multiplexed input for the DACs; bit 7 D8D 23 multiplexed input for the DACs; bit 8 1996 Sep 18 4 Philips Semiconductors Objective specification 34 D0A AGND1 1 33 OGND DEC1 2 32 OE DEC2 3 31 VCCD1 INI 4 30 CLKA DEC3 5 29 STDBYA INQ 6 VCCA1 7 27 STDBYD VCCA2 8 26 CLKD OUTI 9 25 DGND2 28 DGND1 TDA8779H 5 D7D 22 D6D 21 D5D 20 D4D 19 D3D 18 D2D 17 D1D 16 AGND2 D0D 15 23 D8D VCCD2 14 OUTQ 11 13 24 D9D DEC5 12 DEC4 10 Fig.2 Pin configuration. 1996 Sep 18 35 D1A 36 D2A TDA8779 37 D3A 38 D4A 39 D5A 40 D6A 41 D7A 42 D8A handbook, full pagewidth 43 D9A 44 VCCO 10-bit converter interface (ADC/DAC) for quadrature transceiver MGG074 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver TDA8779 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCCA1 analog supply voltage for ADC part −0.3 +7.0 V VCCA2 analog supply voltage for DAC part −0.3 +7.0 V VCCD1 digital supply voltage for ADC part −0.3 +7.0 V VCCD2 digital supply voltage for DAC part −0.3 +7.0 V VCCO output stage supply voltage −0.3 +7.0 V ∆VCC voltage difference between: VCCA − VCCD −1.0 +1.0 V VCCA − VCCO −1.0 +4.0 V VCCD − VCCO −1.0 +4.0 V − 10 mA Io output current Vi input voltage −0.3 +7.0 V Vclk(p-p) AC input switching voltage (peak-to-peak value) referenced to DGND − VCCD V Tstg storage temperature −55 +150 °C Tamb operating ambient temperature −20 +75 °C Tj junction temperature − 150 °C referenced to AGND THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER CONDITIONS thermal resistance from junction to ambient in free air VALUE UNIT 75 K/W CHARACTERISTICS VCCA = V7 and V8 to V1 and V13 = 4.75 to 5.5 V; VCCD = V31 and V14 to V28 and V25 = 4.75 to 5.5 V; VCCO = V44 to V33 = 2.7 to 5.5 ; AGND1, AGND2, OGND, DGND1 and DGND2 are shorted together; Tamb = −20 to +70 °C; measured typically at VCCA = VCCD = 5 V and VCCO = 3 V; CL = 15 pF; Tamb = 25°C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VCCA1 analog supply voltage for ADC part 4.75 5.0 5.5 V VCCD1 digital supply voltage for ADC part 4.75 5.0 5.5 V VCCA2 analog supply voltage for DAC part 4.75 5.0 5.5 V VCCD2 digital supply voltage for DAC part 4.75 5.0 5.5 V VCCO output stage supply voltage 2.7 3.0 5.5 V ∆VCC voltage difference between VCCA − VCCD −0.2 − +0.2 V VCCA − VCCO −0.2 − +2.5 V −0.2 − +2.5 V ICCA analog supply current VCCD − VCCO − 71 − mA ICCD digital supply current − 31 − mA 1996 Sep 18 6 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver SYMBOL PARAMETER TDA8779 CONDITIONS MIN. TYP. MAX. UNIT − 2 − mA analog standby current for ADC part − 5 − mA analog standby current for DAC part − 5 − mA V ICCO output stage supply current ICCA1(stb) ICCA2(stb) ramp input; fCLK = 20 MHz ADC PART CLOCK INPUT VIL LOW level input voltage 0 − 0.6 VIH HIGH level input voltage 2.2 − VCCD1 V IIL LOW level input current −10 − +10 µA IIH HIGH level input current −10 − +10 µA V DIGITAL INPUTS: PINS OE AND STDBYA VIL LOW level input voltage 0 − 0.6 VIH HIGH level input voltage 2.2 − VCCD1 V IIL LOW level input current −1 0 +1 µA IIH HIGH level input current − − 1 µA ANALOG INPUTS IIL LOW level input current for code 0 − tbf − µA IIH HIGH level input current for code 1023 − tbf − µA Vi(p-p) analog input voltage (peak-to-peak value) full-scale tbf 1.5 tbf V Vi(p-p)over maximum analog input over voltage (peak-to-peak value) overvoltage − − 4.5 V ZI input impedance − 10 − kΩ CI input capacitance − 3 − pF − 0.5 V DIGITAL OUTPUTS: D0A TO D9A VOL LOW level output voltage Io = 1 mA 0 VOH HIGH level output voltage Io = −1 mA VCCO − 0.5 − VCCO V IoZ output current in 3-state mode 0.5 V < Vo < VCCO − 0.5 V −20 − +20 µA SWITCHING CHARACTERISTICS (see Fig.3) fCLKmax maximum clock frequency 20 − − MHz tCH clock pulse width HIGH 20 − − ns tCL clock pulse width LOW 20 − − ns tr clock rise time − 4 − ns tf clock fall time − 4 − ns 1996 Sep 18 7 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver SYMBOL PARAMETER TDA8779 CONDITIONS MIN. TYP. MAX. UNIT ANALOG SIGNAL PROCESSING Linearity INLA integral non linearity ramp input; fCLK = 20 MHz − ±2 − LSB DNLA differential non linearity full-scale; ramp input; fCLK = 20 MHz − ±0.5 − LSB 50% full-scale; ramp input; fCLK = 20 MHz − ±0.3 − LSB fin = 5.1 MHz; 20 Msps − −60 − dB fi = 5.1 MHz; 20 Msps − −54 − dB fi = 5.1 MHz; 20 Msps 45 56 − dB Noise floor; note 2 NF noise floor Harmonics; note 3 THD total harmonic distortion Spurious free dynamic range SFDR spurious free dynamic range Matching between the I and Q channels ∆V amplitude matching fin = 5.1 MHz; fCLK = 20 MHz; Tamb = 25°C − − 6 % ∆ϕ phase matching fin = 5.1 MHz; fCLK = 20 MHz; Tamb = 25°C − − 2 Deg bandwidth maximum attenuation of −0.3 dB full-scale sine wave; Tamb = 25°C; 5.5 − − MHz 50% full-scale sine wave; Tamb = 25°C; tbf − − MHz Bandwidth B TIMING: (THE OUTPUT DATA IS AVAILABLE AFTER THE MAXIMUM DELAY TIME td); CL = 15 pF; see Fig.3 tds sampling delay time − − 5 ns th output hold time 5 − − ns td output delay time VCCO = 4.75 V − 12 15 ns VCCO = 3.15 V − 17 20 ns VCCO = 2.7 V − 21 24 ns 3-STATE OUTPUT DELAY TIMES; see Fig.4 tdZH output delay enable HIGH − 14 18 ns tdZL output delay enable LOW − 16 20 ns tdHZ output delay disable HIGH − 16 20 ns tdLZ output delay disable LOW − 14 18 ns 1996 Sep 18 8 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver SYMBOL PARAMETER TDA8779 CONDITIONS MIN. TYP. MAX. UNIT STANDBY MODE OUTPUT DELAY TIMES; STDBYA td(stb)LH standby (LOW-to-HIGH transition) − − 100 µs td(stb)HL start-up (HIGH-to-LOW transition) − − 100 µs fCLK(DAC) = 16.384 MHz; − fCLK(ADC) = 8.192 MHz; Tamb = 25°C; both DACs switching between input codes 0 and 1023; one ADC 1 V (p-p) sine wave at 4 MHz and the other ADC set at the middle code − −55 dB − 0.6 V CROSSTALK ON THE ADC αct crosstalk into the ADC DAC PART DIGITAL INPUTS: D0D TO D9D AND CLKD VIL LOW level input voltage 0 VIH HIGH level input voltage 2.2 − VCCD2 V IIL LOW level input current −200 −120 0 µA IIH HIGH level input current −10 − +10 µA − 0.6 V DIGITAL INPUT; STDBYD VIL LOW level input voltage 0 VIH HIGH level input voltage 2.2 − VCCD2 V IIL LOW level input current −1 0 +1 µA IIH HIGH level input current − − 1 µA TIMING: see Fig.5 fCLK(max) maximum clock frequency 20 − − MHz tCH clock pulse width HIGH 20 − − ns tCL clock pulse width LOW 20 − − ns tr clock rise time − 4 − ns tf clock fall time − 4 − ns ts input data set-up time 10 tbf − ns th input data hold time 0 tbf − ns ANALOG OUTPUTS; note 1 Vo(p-p) output voltage (peak-to-peak value) full-scale tbf 1 tbf V ZoL output load impedance see Fig.6 − 15 − pF − 0.3 − kΩ TRANSFER FUNCTION INLD integral non linearity ramp input; fCLK = 20 MHz − ±3 − LSB DNLD differential non linearity ramp input; fCLK = 20 MHz; − ±0.75 − LSB B maximum bandwidth full scale; Tamb = 25°C 5.5 − − MHz 1996 Sep 18 9 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver SYMBOL PARAMETER TDA8779 CONDITIONS MIN. TYP. MAX. UNIT Matching between channel I and Q ∆V amplitude matching fo = 5.1 MHz; fCLK = 20 MHz; Tamb = 25°C − − 6 % ∆ϕ phase matching fo = 5.1 MHz; fCLK = 20 MHz; Tamb = 25°C − − 2 Deg fo = 5.1 MHz; fCLK = 20 MHz − −60 − dB fo = 5.1 MHz; fCLK = 20 MHz − 50 − dB DYNAMIC RANGE; NF note 2 noise floor SPURIOUS FREE DYNAMIC RANGE SFDR spurious free dynamic range STANDBY MODE OUTPUT DELAY; STDBYD td(stb)LH standby (LOW-to-HIGH transition) − − 100 µs td(stb)HL start-up (HIGH-to-LOW transition) − − 100 µs fCLK(DAC) = 16.384 MHz; − fCLK(ADC) = 8.192 MHz; Tamb = 25°C; one DAC switching between input codes 0 and 1023 the other DAC set at the middle code; both ADCs 1 V (p-p) sine wave at 4 MHz; incoherent − −55 dB CROSSTALK ON THE DAC αct crosstalk into the DAC Notes 1. It is recommended that the DAC output voltage is AC coupled in order to achieve optimum performance. 2. The noise floor is the maximum value of the output spectrum without taking into account fundamental and harmonics of the input signal. 3. Harmonics are obtained via a Fast Fourier Transformer (FFT) treatment taking 8K acquisition points per period. 1996 Sep 18 10 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver Table 1 TDA8779 Output coding and input voltage (typical value, referenced to AGND) BINARY OUTPUT BITS Vi − V512 (V) D9A D8A D7A D6A D5A D4A D3A D2A D1A D0A underflow <−0.75 0 0 0 0 0 0 0 0 0 0 STEP 0 −0.75 0 0 0 0 0 0 0 0 0 0 ... ... ... ... ... ... ... ... ... ... ... ... 512 0 1 0 0 0 0 0 0 0 0 0 ... ... ... ... ... ... ... ... ... ... ... ... 1023 0.75 1 1 1 1 1 1 1 1 1 0 overflow >0.75 1 1 1 1 1 1 1 1 1 1 Table 2 Input coding and output voltage (typical value, referenced to DGND) BINARY INPUT BITS D0D Vo − V512 (V) STEP D9D D8D D7D D6D D5D D4D D3D D2D D1D 0 0 0 0 0 0 0 0 0 0 0 −0.5 ... ... ... ... ... ... ... ... ... ... ... ... 512 1 0 0 0 0 0 0 0 0 0 0 ... ... ... ... ... ... ... ... ... ... ... ... 1023 1 1 1 1 1 1 1 1 1 0 0.5 Table 3 Table 4 Mode selection OE D0A TO D9A 1 high impedance 0 active; binary Standby selection STDBYA D0 TO D9 ICCA + ICCD (typ.) 1 − 5 mA 0 active 64 mA STDBYD OUTI AND OUTQ ICCA + ICCD (typ.) 1 − 5 mA 0 active 38 mA Table 5 Standby selection 1996 Sep 18 11 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver handbook, full pagewidth TDA8779 tCL tCH n CLKA 50% I CHANNEL ADC OUTPUT In − 2 In − 1 In In + 1 Q CHANNEL ADC OUTPUT Qn − 2 Qn − 1 Qn Qn + 1 Q CHANNEL LATCHED DATA MULTIPLEXED OUTPUTS Qn − 2 In − 2 Qn − 1 Qn − 2 In − 1 Qn Qn − 1 Qn + 1 Qn In In + 1 td tds ViI or ViQ th sample N MGG078 Fig.3 Timing diagram for the ADC. 1996 Sep 18 12 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver TDA8779 VCCD handbook, full pagewidth 50% OE tdHZ tdZH HIGH 90% output data 50% tdLZ LOW tdZL HIGH VCCD output data 50% LOW 3.3 kΩ 10% S1 TDA8779 10 pF OE tOE = 100 kHz. Fig.4 Timing diagram and test conditions of 3-state output delay time. Table 6 Test conditions for Fig.4 TEST SWITCH S1 tdLZ VCCD tdZL VCCD tdHZ DGND tdZH DGND 1996 Sep 18 13 MGG077 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver th handbook, full pagewidth TDA8779 tCL tCH 50% CLKD n ts MULTIPLEXED INPUTS I CHANNEL LATCHED DATA In Qn In + 1 In In + 2 Qn + 1 Qn + 2 In + 1 In + 2 In + 3 In + 3 I CHANNEL DAC OUTPUT In − 1 In In + 1 In + 2 Q CHANNEL DAC OUTPUT Qn − 1 Qn Qn + 1 Qn + 2 MGG079 Fig.5 DACs multiplexed inputs timing diagram. handbook, halfpage TDA8779 9,11 I, Q 1 µF 300 Ω 15 pF MGG076 Fig.6 Equivalent DACs output load. 1996 Sep 18 14 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver TDA8779 APPLICATION INFORMATION handbook, full pagewidth 100 nF VCCA1 7 INPUT BIAS 10 nF DEC1 DEC2 47 VCCD1 nF DEC3 2 5 3 STDBYA DGND1 31 29 28 REFERENCE REGULATOR TDA8779H 32 100 nF INI 4 10-BIT ADC 10 MUX 100 nF INQ 6 10-BIT ADC 10 10 BUFFER 10 LATCHES 34-43 44 30 AGND1 1 µF 15 pF 26 BUFFER OUTI 9 10-BIT DAC 10 10 BUFFER 11 10-BIT DAC 13 REFERENCE REGULATOR OUTQ 300 Ω AGND2 8 VCCA2 10 nF VCCO CLKA CLKD BUFFER 10 15-24 D0D to D9D 10 12 10 DEC4 DEC5 22 nF 14 VCCD2 Fig.7 Application diagram. 1996 Sep 18 D0A to D9A 33 OGND LATCHES 300 Ω 1 µF 15 pF 1 OE 15 25 DGND2 27 STDBYD MBH581 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver TDA8779 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 c y X A 33 23 34 22 ZE e Q E HE A A2 wM (A 3) A1 θ bp Lp pin 1 index L 12 44 1 detail X 11 wM bp e ZD v M A D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp Q v w y mm 2.10 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 10.1 9.9 0.8 12.9 12.3 12.9 12.3 1.3 0.95 0.55 0.85 0.75 0.15 0.15 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-02-04 SOT307-2 1996 Sep 18 EUROPEAN PROJECTION 16 o 10 0o Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver TDA8779 SOLDERING Wave soldering Introduction Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. If wave soldering cannot be avoided, the following conditions must be observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. Reflow soldering Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9397 750 00192). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. 1996 Sep 18 17 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver TDA8779 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Sep 18 18 Philips Semiconductors Objective specification 10-bit converter interface (ADC/DAC) for quadrature transceiver NOTES 1996 Sep 18 19 TDA8779 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 926 5361, Fax. +7 095 564 8323 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 825 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1996 SCA51 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/1200/02/pp20 Date of release: 1996 Sep 18 Document order number: 9397 750 01181