INTEGRATED CIRCUITS DATA SHEET TDA8050A QPSK transmitter Product specification File under Integrated Circuits, IC02 1999 Nov 05 Philips Semiconductors Product specification QPSK transmitter TDA8050A FEATURES Two PLLs are incorporated, the first PLL includes: • Programmable gain • A fixed main divider • PLL controlled carrier frequency • A crystal oscillator and its programmable reference divider • 3-wire transmission bus • A phase/frequency detector, combined with a fixed charge pump. • 5 V supply voltage. The second PLL includes: APPLICATIONS • A divide-by-four preamplifier • QPSK modulation. • A 12-bit programmable divider GENERAL DESCRIPTION • A crystal oscillator and its programmable reference divider The Quadrature Phase Shift Keying (QPSK) transmitter IC is a monolithic bipolar IC dedicated to quadrature modulation of the I and Q signals. It includes: • A phase/frequency detector, combined with a programmable charge pump which drives the tuning amplifier, including 30 V output. • Two double balanced mixers • A balanced voltage controlled oscillator (VCO) with 0 to 90 degrees signal generation for modulation • A phase locked loop (PLL) for IF frequency control • A conversion mixer • A PLL for RF frequency control • A gain controlled output amplifier • A 3-wire bus and an output buffer. QUICK REFERENCE DATA SYMBOL PARAMETER VCC supply voltage fc Vo(max) MIN. TYP. MAX. UNIT 4.75 5.00 5.25 V output centre frequency 5 − 65 MHz maximum output level − 55 − dBmV fxtal crystal frequency 1 − 4 MHz fref(MOD) reference frequency for modulator synthesizer − 250 − kHz fstep frequency step size for converter synthesizer 100 − 500 kHz Tamb ambient temperature 0 − 70 °C ORDERING INFORMATION TYPE NUMBER TDA8050A 1999 Nov 05 PACKAGE NAME SO32 DESCRIPTION plastic small outline package; 32 leads; body width 7.5 mm 2 VERSION SOT287-1 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 26 9 RF_OUTC RF_OUT 24 25 RF_INC RF_IN SW_CAP 28 27 30 31 MODULATOR I_IN I_INC 5 Q_INC DVCC DGND CLK 3 DATA EN LOCK 32 29 AGND2 4 CONVERTER × 6 1 7 3 × Σ Q_IN AVCC2 Philips Semiconductors IF_FILT AGND1 QPSK transmitter BLOCK DIAGRAM 1999 Nov 05 IF_FILTC AVCC1 2 OUTEN BUF_OUTC BUF_OUT × 8 13 18 90 14 0 DAC 1/2 15 3-WIRE BUS TRANCEIVER 16 TDA8050A 23 CHARGE PUMP 12 DIGITAL PHASE COMPARATOR FIXED MAIN DIVIDER PROGRAMMABLE MAIN DIVIDER PROGRAMMABLE REF DIVIDER PROGRAMMABLE REF DIVIDER 10 11 17 22 21 DIGITAL PHASE COMPARATOR 20 PROGRAMMABLE CHARGE PUMP 19 FCE433 CP_MOD TKAMOD OSC_IN TUNECONV CP_CONV TKACONV TDA8050A Fig.1 Block diagram. Product specification TKBMOD TKBCONV Philips Semiconductors Product specification QPSK transmitter TDA8050A PINNING SYMBOL PIN DESCRIPTION OUTEN 1 output enable BUF_OUT 2 output amplifier balanced output BUF_OUTC 3 output amplifier balanced output AGND2 4 converter analog ground 2 I_IN 5 I balanced input I_INC 6 I balanced input Q_IN 7 Q balanced input Q_INC 8 Q balanced input AGND1 9 modulator analog ground 1 TKA_MOD 10 modulator VCO tank circuit input 2 TKB_MOD 11 modulator VCO tank circuit input 1 CP_MOD 12 modulator charge pump output for PLL loop filter VCCD 13 digital supply voltage CLK 14 3-wire bus serial control clock DATA 15 3-wire bus serial control data EN 16 3-wire bus serial control enable OSC_IN 17 crystal oscillator input DGND 18 digital ground CP_CONV 19 converter charge pump output for PLL loop filter TUNE_CONV 20 tuning voltage output for converter VCO TKB_CONV 21 converter VCO tank circuit input 1 TKA_CONV 22 converter VCO tank circuit input 2 LOCK 23 lock detect signal IF_FILT 24 IF balanced output to filter IF_FILTC 25 IF balanced output to filter VCCA1 26 modulator analog supply voltage RF_OUTC 27 RF balanced output to filter RF_OUT 28 RF balanced output to filter VCCA2 29 converter analog supply voltage RF_IN 30 RF balanced input to programmable amplifier RF_INC 31 RF balanced input to programmable amplifier SW_CAP 32 switch capacitor 1999 Nov 05 4 Philips Semiconductors Product specification QPSK transmitter TDA8050A FUNCTIONAL DESCRIPTION The I and Q signals are balanced analog signals of 400 mV (p-p). These are mixed by two double balanced mixers with the output signal generated by a first local oscillator, to provide the modulated signal. The modulated signal is then filtered by an IF filter. This filtered signal, together a signal generated by a second local oscillator, is converted by a balanced mixer to produce the QPSK signal. OUTEN 1 The QPSK signal is amplified by a gain controlled output amplifier to a level suitable for transmission. The gain of the amplifier is bus controlled and this amplifier can be disabled when not transmitting, to provide signal attenuation. 32 SW_CAP BUF_OUT 2 The amplified signal is applied to an on-chip amplifier with two balanced outputs (open collector) connected to two off-chip resistors (values 150 Ω), in turn connected to 9 V. The balanced outputs drive a 2 : 1 transformer (Siemens V944) loaded with 75 Ω, which gives an output level of 55 dBmV. The output frequency range of the transmitter is 5 to 65 MHz. 31 RF_INC BUF_OUTC 3 30 RF_IN AGND2 4 29 AVCC2 I_IN 5 28 RF_OUT I_INC 6 27 RF_OUTC Q_IN 7 26 AVCC1 Q_INC 8 The frequency of the first local oscillator operates at twice the frequency (i.e. 280 MHz), fixed by a PLL implemented in the circuit. 25 IF_FILTC TDA8050A AGND1 9 24 IF_FILT TKAMOD 10 23 LOCK TKBMOD 11 22 TKACONV CP_MOD 12 21 TKBCONV DVCC 13 The frequency of the second local oscillator operates in the 145 to 205 MHz bandwidth and can be programmed through the PLL implemented in the circuit. The VCOs of both the first and second local oscillators need an external LC tank circuit with two varicap diodes. 20 TUNECONV CLK 14 The data sent to the PLL is loaded in bursts framed by signal EN. Programming rising clock edges and their appropriate data bits are ignored until EN goes active (LOW). The internal latches are updated with the latest programming data when EN returns to inactive (HIGH). Only the last 14 bits are stored in the programming register. 19 CP_CONV DATA 15 18 DGND EN 16 17 OSC_IN FCE434 No check is made on the number of clock pulses received during the time that programming is enabled. If EN goes high while CLK is still LOW, a wrong active clock edge will be generated, causing a shift of the data bits. At power up, EN should be HIGH. The lock detector output LOCK is HIGH when both PLLs are in lock. The main divider ratio and the reference divider ratios are provided via the serial bus. A control register controls the Digital-to-Analog-Converter (DAC), the output amplifier and the charge pump currents (see Tables 1, 2 and 3). Fig.2 Pin configuration. 1999 Nov 05 5 Philips Semiconductors Product specification QPSK transmitter TDA8050A LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VCC supply voltage −0.3 +6.0 V tsc short-circuit time (every pin to VCC or GND) − 10 s VMAX voltage on all pins except BUF_OUT, BUF_OUTC and TUNE_CONV −0.3 VCC V Vo(tune) output tuning voltage −0.3 +30 V VO(buf) output buffer voltage on pins BUF_OUT and BUF_OUTC − 10 V Ptot maximum power dissipation − 940 mW Tamb ambient temperature 0 70 °C Tstg storage temperature −40 +150 °C Tj(max) maximum junction temperature − 150 °C HANDLING Human Body Model (HBM): The IC pins withstand 2 KV, except pins 27 and 28 (1750 V). Machine Model (MM): The IC pins withstand 100 V. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS VALUE UNIT 63 K/W thermal resistance from junction to ambient in free air CHARACTERISTICS Measured in application circuit with the following conditions; VCC = 5 V, Tamb = 25 °C; all AC units are RMS values, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VCCA1 modulator analog supply voltage 4.75 5 5.25 V ICCA1 modulator analog supply current 33 39 45 mA VCCA2 converter analog supply voltage 4.75 5 5.25 V ICCA2 converter analog supply current 39 47 55 mA ICC(buf) buffer output supply current 39 43 47 mA VCCD digital supply voltage 4.75 5 5.25 V ICCD digital supply current 20.5 23.5 26.5 mA VCC(tune) tuning supply voltage − − 30 V 1999 Nov 05 6 Philips Semiconductors Product specification QPSK transmitter SYMBOL PARAMETER TDA8050A CONDITIONS MIN. TYP. MAX. UNIT Quadrature modulator I and Q inputs Vi(DC) input DC level Vi(p-p) signal input level (balanced) (peak-to-peak) fi(max) I and Q maximum input frequency Zi(dif) differential input impedance B(1 dB) 1 dB bandwidth amplifier − 0.5 × VCC − V indicative − 400 500 mV indicative − 10 − MHz − 4.4 − kΩ − 10 − MHz − − 140 MHz − − ±1 dB − − ±2 deg − −28 − dBc − 1.8 − kΩ − − 280 MHz indicative Modulator fc output centre frequency ∆A amplitude imbalance ∆Φ phase imbalance LO(sup) LO suppression Zo(dif) differential output impedance see Fig.3 see Fig.3 Modulator VCO FOSC(mod) oscillation frequency Converter output VO output level f = 5 MHz; Vi = 100 mVdif at I and Q inputs 37.5 40 42.5 dBmV ∆VO output flatness f = 5 to 65 MHz; Vi = 100 mVdif at I and Q inputs − − 2 dB fc output centre frequency 5 − 65 MHz Zo(dif) differential output impedance − 150 − Ω IP3 3rd order interception point at I input see Fig.4 − − 52 dBmV H2 2nd order harmonic of 5 to 65 MHz signal f = 10 to 130 MHz; Vi = 100 mVdif at I and Q inputs − − −40 dBc H3 3rd order harmonic of 5 to 65 MHz signal f = 15 to 195 MHz; Vi = 100 mVdif at I and Q inputs − − −40 dBc SO mixer spurious outputs of 5 to 65 MHz signal f = 5 to 65 MHz; Vi = 100 mVdif at I and Q inputs − − −45 dBc Converter VCO fosc(min) minimum oscillation frequency − − 145 MHz fosc(max) maximum oscillation frequency 205 − − MHz 1999 Nov 05 7 Philips Semiconductors Product specification QPSK transmitter SYMBOL TDA8050A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Programmable gain and output buffer; note 1 Zi(dif) differential input impedance − 5.6 − kΩ ∆G output level step size − − 2 dB ∆bufO output level adjust range 32 39 − dB Vo operational output level − 55 − dBmV ∆Vo output flatness f = 5 to 65 MHz; Vi = 30 dBmV sine wave; DAC = 28 − 3 5 dB Vi = 30 dBmV sine wave 65 MHz at pins RF_IN and RF_INC; DAC = 0 to 31 VIL(ENL) output controlled enable low output buffer on − − 0.8 V VIH(ENH) output controlled enable high output buffer off 2.4 − − V ISO disable isolation Vi = 100 mVdif; DAC = 28; f = 65 MHz; OE = 0,5 V −35 −90 − dBc GV(max) maximum gain see Fig.5 17 18.5 − dB Vo(1dB) 1 dB compression point see Fig.5 58 − − dBmV H2 2nd order harmonic of 5 to 65 MHz signal f = 10 to 65 MHz; see Fig.6 − − −45 dBc f = 65 to 120 MHz; see Fig.6 − − −35 dBc 3rd order harmonic of 5 to 65 MHz signal f = 15 to 65 MHz; see Fig.6 − − −45 dBc f = 65 to 120 MHz; see Fig.6 − − −35 dBc at 10 kHz; note 2 − −75 − dBc/Hz at 100 kHz; note 2 − −95 − dBc/Hz H3 Overall; note 1 Φosc phase noise H2 2nd order harmonic of 5 to 65 MHz signal f = 10 to 130 MHz; Vin = 100 mVdif at I and Q inputs; Vout = 55 dBmV − − −40 dBc H3 3rd order harmonic of 5 to 65 MHz signal f = 15 to 195 MHz; Vin = 100 mVdif at I and Q inputs; Vout = 55 dBmV − − −40 dBc So spurious signals of 5 to 65 MHz f = 5 to 65 MHz; Vin = 100 mVdif signal at I and Q inputs; Vout = 55 dBmV − − −45 dBc IP3 3rd order interception point at I input − − 49 dBmV ISOtot total isolation at I/Q midrange see Fig.7 − −90 −65 dBc C/N carrier to noise ratio at final output at 2 MHz from carrier Vin = 100 mVdif; Vout = 35 to 55 dBmV; f = 65 MHz − 113 − dBc/Hz 1999 Nov 05 8 Philips Semiconductors Product specification QPSK transmitter SYMBOL TDA8050A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Crystal oscillator fxtal crystal frequency note 3 1 − 4 MHz Zi input impedance fxtal = 4 MHz 600 1200 − Ω Vi(DC) DC input level − 2.9 − V kHz Modulator synthesizer fref(mod) reference frequency − 250 − RDR1 programmable reference divider ratio 4 − 16 ND1 fix main divider ratio − 1120 − I(cp) charge-pump current − 0.30 − mA kHz fixed Converter synthesizer fstep step size 100 − 500 RD2 fix reference divider ratio − 2 − RDR2 programmable reference divider see Tables 4 and 5 ratio 4 − 160 ND2 fix main divider ratio − 4 − NDR2 programmable main divider ratio 290 − 1800 see Tables 4 and 5 3-wire bus VIL input LOW level − − 0.8 V VIH input HIGH level 2.4 − − V Lock detect pin VO(lock) output voltage (LOCK) − 5 − V VO(unlock) output voltage (UNLOCK) − 0.02 − V Serial control clock fclk clock frequency − 330 − kHz tsu input data to CLK set-up time see Fig.8 − 2 − µs th(CLK) input data to CLK hold time see Fig.8 − 1 − µs td(strt) delay to rising clock edge see Fig.8 − 3 − µs td(stp) delay from last clock edge see Fig.8 − 3 − µs Notes 1. All specification points of the output section and the overall circuit are measured after the 2 : 1 transformer (Siemens V944) loaded with 75 Ω. 2. Overall phase noise: a) Converter: I(cp) = 0.36 mA; fref = 25 kHz. b) I and Q = 100 mVdif. c) DAC = 28. d) f = 65 MHz. 3. The crystal oscillator uses a 4, 2 or 1 MHz crystal in series with a capacitor. The crystal is serial resonant with a load capacitance of 18 to 20 pF. The connection to VCC is preferred but it might also be to GND. 1999 Nov 05 9 Philips Semiconductors Product specification QPSK transmitter TDA8050A FCE435 IF_FILT imbalance LO(sup) measure 2 f lo(2) measure 1 f lo(2) frequency The amplitude imbalance and the LO suppression are measured in the spectrum of the signal measured at the output IF_FILT and are defined in the following conditions: measure 1: I input frequency = 500 kHz; I input level = 400 mV (p-p) sine wave; unused input as 0 V differential. measure 2: Q input frequency = 500 kHz; Q input level = 400 mV (p-p) sine wave; unused input as 0 V differential. Fig.3 Imbalance and LO suppression. 1999 Nov 05 10 Philips Semiconductors Product specification QPSK transmitter TDA8050A handbook, full pagewidth I_IN 50 Ω I_INC 50 Ω 500 kHz RF_OUT SPECTRUM ANALYZER RF_OUTC Q_IN Q_INC 300 kHz IM3 64.1 64.5 64.7 65 40 65.1 65.3 65.5 65.7 f (MHz) FCE436 f1 = 300 kHz, f2 = 500 kHz and frf = 65 MHz. Fig.4 IP3 set-up measurement. 1999 Nov 05 11 Philips Semiconductors Product specification QPSK transmitter TDA8050A Siemens V944 handbook, full pagewidth 50 Ω RF_IN BUF_OUT 150 Ω BUF_OUTC 150 Ω 75 Ω/50 Ω ADAPTER SPECTRUM ANALYZER 75 Ω/50 Ω ADAPTER SPECTRUM ANALYZER 9V RF_INC gain (dB) Gmax Gmax − 1 Vo(−1 dB) Vo FCE437 DAC = 31. f = 65 MHz. Vi variable to have a variable output voltage. Fig.5 Maximum gain and compression point. handbook, full pagewidth Siemens V944 RF_IN BUF_OUT 150 Ω BUF_OUTC 150 Ω 9V RF_INC FCE438 DAC = 28. f = 5 to 65 MHz. Vi such that Vo = 55 dBmV (rms) at 5 MHz. Fig.6 Harmonics of output sections H2 and H3. 1999 Nov 05 12 Philips Semiconductors Product specification QPSK transmitter handbook, full pagewidth TDA8050A OUTEN = 0 V Siemens V944 I_IN Vi(dif) = 100 mVdif BUF_OUT 150 Ω BUF_OUTC 150 Ω 75 Ω/50 Ω ADAPTER SPECTRUM ANALYZER 75 Ω/50 Ω ADAPTER SPECTRUM ANALYZER 9V I_INC Q_IN Vi(dif) = 100 mVdif Q_INC DAC = 28 OUTEN = 5 V Siemens V944 I_IN 150 Ω BUF_OUT 0V 9V I_INC 150 Ω BUF_OUTC Q_IN 0V Q_INC DAC = 28 FCE439 ISOtot = Vout1(dB) − Vout2(dB). frf = 65 MHz. Fig.7 Total isolation (ISOtot). 1999 Nov 05 13 Philips Semiconductors Product specification QPSK transmitter TDA8050A APPLICATION INFORMATION t h(CLK) t su T cy CLK DATA EN t d(strt) t d(stp) FCE440 Fig.8 3-wire bus timing. Table 1 Data format; note 1 DATA D11 D10 first in D9 D8 Modulator reference divider ratio X X D7 D6 D5 ADDRESS D4 D3 D2 D1 D0 AD1 AD0 last in R3 R2 R1 R0 0 1 Converter reference divider ratio MP1(2) MP0(2) R7 R6 R5 R4 Control register X X X OEN(3) CR2(4) CR1 CR0(4) DAC4(5) DAC3 DAC2 DAC1 DAC0 1 0 P8 P5 P2 P1 P0 1 1 Main divider ratio P11 P10 P9 P7 P6 P4 P3 Notes 1. X = don’t care. 2. MP1 and MPO: modulator reference divider ratio (see Table 2). 3. When OEN (output enable) is at logic 0, output is disabled; at logic 1, output is enabled. 4. CR2 and CRO: converter synthesizer charge pump current (see Table 3). 5. When DAC4 to DAC0 is at logic 0, minimum gain is programmed; at logic 1, maximum gain is programmed. 1999 Nov 05 14 Philips Semiconductors Product specification QPSK transmitter Table 2 Table 3 TDA8050A Modulator reference divider ratio MP1 MP0 PROGRAMMED RATIO 1 1 4 1 0 8 0 1 16 Converter synthesizer charge pump current CR2 CR1 CR0 LOCK_CONV(1) 0 0 0 0 1.2 0 0 0 1 0.36 0 0 1 0 0.36 0 0 1 1 0.1 0 1 0 X 0.1 0 1 1 X 0.36 1 0 0 X 1.2 ICP(mA) Note 1. LOCK_CONV is an internal signal. When at logic 0, converter PLL is out-of-lock. When at logic 1, converter PLL is in-lock. Table 4 Converter synthesizer fcomp = fosc/RD. fosc\fcomp 25 kHz 50 kHz 125 kHz 1 MHz 40 20 8 4 MHz 160 80 32 200 kHz 500 kHz Table 5 Converter synthesizer; ND = 4 f_lo = ND × NDR × fcomp = NDR × step. flo\step 100 kHz 145 MHz 1450 725 290 205 MHz 2050 1025 410 1999 Nov 05 15 Philips Semiconductors Product specification QPSK transmitter handbook, full pagewidth TDA8050A +5 V OUTEN 1 32 2 31 SW_CAP Siemens V944 150 Ω BUF_OUT RF_INC 100 nF +9 V 150 Ω BUF_OUTC 30 3 680 Ω RF_IN 100 nF AGND2 100 nF I_IN 4 29 5 28 AVCC2 47 pF +5 V 390 nH RF_OUT 100 nF 100 Ω 100 nF I_INC 27 6 390 nH 27 pF RF_OUTC 100 nF 100 nF Q_IN 7 26 8 25 AVCC1 +5 V 100 Ω 100 nF Q_INC IF_FILTC 68 nH TDA8050A AGND1 10 kΩ 22 kΩ 140 MHz 10 pF TKAMOD 22 nH TKBMOD 10 kΩ 23 10 LOCK BB132 10 kΩ (2×) 22 11 TKACONV 22 kΩ 39 pF CP_MOD 12 21 13 20 22 kΩ 4.7pF 56 nH 15 pF 330 pF 18 pF IF_FILT BB133 (2×) 15 pF 22 kΩ 24 9 TKBCONV 39 pF 10 kΩ 820 pF 22 kΩ 10 kΩ 330 pF 8.2 nF DVCC 10 kΩ TUNECONV +30 V 27 kΩ 100 nF 330 pF CLK DATA EN 14 19 15 18 16 17 10 nF CP_CONV DGND OSC_IN 4 MHz FCE441 Fig.9 Application diagram. 1999 Nov 05 16 Philips Semiconductors Product specification QPSK transmitter TDA8050A INTERNAL PIN CONFIGURATION SYMBOL PIN DESCRIPTION DC VOLTAGE OUTEN 1 n.a. SW_CAP 32 1.7 V 1 32 FCE442 BUF_OUT BUF_OUTC 2 5.8 V 2 3 3 5.8 V FCE443 AGND2 4 0 4 FCE444 I_IN 5 2.5 V I_INC 6 2.5 V 5 6 FCE445 1999 Nov 05 17 Philips Semiconductors Product specification QPSK transmitter SYMBOL TDA8050A PIN DESCRIPTION DC VOLTAGE Q_IN 7 2.5 V Q_INC 8 2.5 V 7 8 FCE446 AGND1 9 0 9 FCE447 TKA_MOD 10 3.1 V TKB_MOD 11 3.1 V 10 CP_MOD 11 FCE448 12 2.1 V 12 FCE449 VCCD 1999 Nov 05 13 supply voltage 5V 18 Philips Semiconductors Product specification QPSK transmitter SYMBOL CLK TDA8050A PIN DESCRIPTION 14 DC VOLTAGE n.a. 14 FCE450 DATA 15 n.a. 15 FCE451 EN 16 n.a. 16 FCE452 OSC_IN 17 2.9 V VCC 17 FCE453 DGND 18 0V 18 FCE454 1999 Nov 05 19 Philips Semiconductors Product specification QPSK transmitter SYMBOL CP_CONV TDA8050A PIN DESCRIPTION DC VOLTAGE 19 2.1 V down VCC 19 up FCE455 TUNE_CONV 20 VVT 20 FCE456 TKB_CONV 21 3.1 V TKA_CONV 22 3.1 V 21 LOCK FCE457 22 23 0V 5V 23 FCE458 1999 Nov 05 20 Philips Semiconductors Product specification QPSK transmitter SYMBOL TDA8050A PIN DESCRIPTION DC VOLTAGE IF_FILT 24 2.1 V IF_FILTC 25 2.1 V 25 24 FCE459 VCCA1 26 RF_OUTC 27 3.7 V RF_OUT 28 3.7 V supply voltage 5V 28 27 FCE460 VCCA2 29 RF_IN 30 2.1 V RF_INC 31 2.1 V supply voltage 5V 30 31 FCE461 1999 Nov 05 21 Philips Semiconductors Product specification QPSK transmitter TDA8050A PACKAGE OUTLINE SO32: plastic small outline package; 32 leads; body width 7.5 mm SOT287-1 D E A X c y HE v M A Z 17 32 Q A2 A (A 3) A1 pin 1 index θ Lp L 16 1 0 detail X w M bp e 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.27 0.18 20.7 20.3 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.2 1.0 0.25 0.25 0.1 0.95 0.55 inches 0.10 0.012 0.096 0.004 0.086 0.01 0.02 0.01 0.011 0.007 0.81 0.80 0.30 0.29 0.050 0.419 0.394 0.055 0.043 0.016 0.047 0.039 0.01 0.01 0.004 0.037 0.022 θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-01-25 97-05-22 SOT287-1 1999 Nov 05 EUROPEAN PROJECTION 22 Philips Semiconductors Product specification QPSK transmitter TDA8050A • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: 1999 Nov 05 23 Philips Semiconductors Product specification QPSK transmitter TDA8050A Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable suitable(2) HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Nov 05 24 Philips Semiconductors Product specification QPSK transmitter TDA8050A NOTES 1999 Nov 05 25 Philips Semiconductors Product specification QPSK transmitter TDA8050A NOTES 1999 Nov 05 26 Philips Semiconductors Product specification QPSK transmitter TDA8050A NOTES 1999 Nov 05 27 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545004/25/01/pp28 Date of release: 1999 Nov 05 Document order number: 9397 750 06123