INTEGRATED CIRCUITS DATA SHEET TDA8051 QPSK receiver Product specification Supersedes data of 1998 Jan 08 File under Integrated Circuits, IC02 1999 Aug 20 Philips Semiconductors Product specification QPSK receiver TDA8051 FEATURES GENERAL DESCRIPTION • High operating input sensitivity This TDA8051 is a monolithic bipolar IC intended for Quadrature Phase Shift Key (QPSK) demodulation. It includes: • Gain controlled amplifier • PLL controlled carrier frequency • Low noise RF and gain controlled amplifier • Low crosstalk between I and Q channel outputs • Two matched mixers • 3-wire transmission bus • Symmetrical Voltage Controlled Oscillator (VCO) with 0 to 90° signal generator whose frequency is controlled by an integrated Phase Lock Loop (PLL) circuit. • 5 V supply voltage. • Two matched amplifiers for output base-band active filtering and output buffers APPLICATIONS • BPSK/QPSK demodulation. The gain control is produced by output level detection compared with an external pre-fixed reference. The PLL consists of: • Divide by four preamplifier • 12-bit programmable main divider • Crystal oscillator with 8-bit programmable reference divider • Phase/frequency detector combined with charge pump to drive tuning amplifier • 30 V output QUICK REFERENCE DATA All AC units are RMS values unless otherwise specified. SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCC supply voltage range 4.75 5.00 5.25 V fI(LNA) input carrier frequency at LNA input 44 − 130 MHz VI(LNA) input level at LNA input −30 − 0 dBmV ∆ΦI-Q phase error between I and Q channels − ±3 − deg ∆GI-Q gain error between I and Q channels − ±1 − dB αCT(I-Q) crosstalk between I and Q channels − −30 − dBc IM3 3rd-order intermodulation distortion in I and Q channels (0 dBmV at LNA_IN) − − −45 dBc Vo voltage output on pin I_OUT and Q_OUT − 48 − dBmV fstep step at output 50 − 250 kHz fxtal crystal frequency 1 − 4 MHz Tamb operating ambient temperature 0 − 70 °C ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8751T 1999 Aug 20 SO32 DESCRIPTION plastic small outline package; 32 leads; body width 7.5 mm 2 VERSION SOT287-1 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors QPSK receiver BLOCK DIAGRAM 1999 Aug 20 Q_OUT1 I_IN1 A1VCC 6 A2VCC A3VCC DVCC 23 25 13 OUTVCC AGC_IN 27 I_OUT1 11 5 Q_IN1 28 29 4 9 3 8 1 2 I_OUT 32 31 Q_OUT LNA_IN × LNA_OUT DEMOD_IN CLK DATA EN × 14 15 3-WIRE BUS TRANSCEIVER 16 90¡ TDA8051 30 0¡ I_OUTC Q_OUTC Q_OUT2 1/2 19 18 CP CHARGE DIGITAL PHASE COMPARATOR 21 PROGRAMMABLE MAIN DIVIDER 1/4 PROGRAMMABLE REF DIVIDER 22 12 1/2 17 10 TEST n.c. A1GND 24 26 TKB TKA OSC_IN 20 FCE112 DGND Product specification Fig.1 Block diagram. A2GND OUTGND TDA8051 handbook, full pagewidth 3 TUNE 7 I_OUT2 Philips Semiconductors Product specification QPSK receiver TDA8051 PINNING SYMBOL PIN DESCRIPTION I_OUT 1 I data buffered balanced output I_OUTC 2 I data buffered balanced output I_OUT2 3 I data filtered output I_IN1 4 input to active filter amplifier for I data I_OUT1 5 I data raw output A1VCC 6 analog supply voltage 1 DEMOD_IN 7 demodulator RF input LNA_OUT 8 low noise amplifier RF output LNA_IN 9 low noise amplifier RF input I_OUTC 2 31 Q_OUTC A1GND 10 analog ground 1 I_OUT2 3 30 Q_OUT2 AGC_IN 11 AGC control voltage input OSC_IN 12 oscillator input DVCC 13 digital supply voltage CLK 14 3-wire bus serial control clock DATA 15 3-wire bus serial control data EN 16 3-wire bus serial control enable (active LOW) LNA_IN 9 24 A2GND TEST 17 not connected A1GND 10 23 A2VCC CP 18 charge pump output for PLL loop filter AGC_IN 11 22 TKA TUNE 19 tuning voltage output OSC_IN 12 21 TKB DGND 20 digital ground TKB 21 TKA handbook, halfpage I_OUT 1 32 Q_OUT I_IN1 4 29 Q_IN1 I_OUT1 5 28 Q_OUT1 A1VCC 6 27 OUTVCC DEMOD_IN 7 26 OUTGND LNA_OUT 8 25 A3VCC TDA8051 DVCC 13 20 DGND VCO tank circuit input CLK 14 19 TUNE 22 VCO tank circuit input DATA 15 A2VCC 23 analog supply voltage 2 A2GND 24 analog ground 2 A3VCC 25 analog supply voltage 3 OUTGND 26 output amplifiers ground OUTVCC 27 output amplifiers supply voltage Q_OUT1 28 Q data raw output Q_IN1 29 input to active filter amplifier for Q data Q_OUT2 30 Q data filtered output Q_OUTC 31 Q data buffered balanced output Q_OUT 32 Q data buffered balanced output 1999 Aug 20 18 CP EN 16 17 TEST FCE171 Fig.2 Pin configuration. 4 Philips Semiconductors Product specification QPSK receiver TDA8051 FUNCTIONAL DESCRIPTION The raw I and Q generated signals contain spurious spikes, therefore each signal is passed through a third order active low-pass filter (RC cell + Sallen-Key structure), whose cut-off frequency is set by external components. The filtered I and Q data signals are then amplified to provide balanced buffer outputs. The QPSK modulated signal is applied to the input as an asymmetrical RF signal in the bandwidth 44 to 130 MHz. The spectrum extension to this waveform must be limited by a band-pass filter superseding the IC. The RF input is either the LNA input, if the level is −30 to 0 dBmVrms, or the DEMOD input if the level is −20 to +10 dBmVrms. The amplified RF signal is then mixed with two clocks in quadrature to provide the base-band demodulated In-phase (I) and Quad-phase (Q) signals. The data sent to the PLL is loaded in bursts, framed by signal EN. Programming clock edges, together with their relevant data bits, are ignored until EN becomes active (LOW). The internal latches are updated with the latest programming data when EN returns to inactive (HIGH). The last 14 bits only are retained within the programming register. No check is made on the number of clock pulses received while programming is enabled. An active clock edge causing a shift of the data bits is generated when EN goes HIGH while CLOCK is still LOW. The main divider ratio and the reference divider ratio are provided via the serial bus (see Table 1). The VCO operates at twice the RF carrier frequency in the bandwidth 88 - 260 MHz (one octave), therefore the 0 to 90° clocks are generated by a divider by 2. The VCO frequency can be programmed by an integrated PLL that tunes the external LC tank circuit. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VCC supply voltage −0.3 6.0 V V(max) maximum voltage on all pins except pin 9 (5 V) −0.3 VCC V tsc maximum short circuit duration on outputs − 10 s Tstg storage temperature −40 +150 °C Tj(max) maximum junction temperature − 150 °C Tamb operating ambient temperature 0 70 °C VCC(tune) tuning voltage supply −0.3 30 V HANDLING HBM ESD: The IC pins withstand 2 kV except pin 26 (1750 V). MM ESD: The IC pins withstand 100 V except pins 2 and 31 (75 V). THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 1999 Aug 20 PARAMETER CONDITIONS thermal resistance from junction to ambient in free air 5 VALUE UNIT 65 K/W Philips Semiconductors Product specification QPSK receiver TDA8051 CHARACTERISTICS Measured in application circuit with the following conditions: VCC = 5 V; Tamb = 25°C. All AC units are RMS values, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VCCA1 analog supply voltage 4.75 5 5.25 V ICCA1 analog supply current − 23 − mA VCCA2 analog supply voltage 4.75 5 5.25 V ICCA2 analog supply current − 18 − mA VCCA3 analog supply voltage 4.75 5 5.25 V ICCA3 analog supply current − 29 − mA Vcc(o) output supply voltage 4.75 5 5.25 V Icc(o) output supply current − 17 − mA VCCD digital supply voltage 4.75 5 5.25 V ICCD digital supply current − 13 − mA VCC(tune) tuning supply voltage − − 30 V − 0.85 − V −30 − 0 dBmV Low noise amplifier: Rs = 75 Ω/Ri = 75 Ω unless otherwise specified VI(DC) DC input level Vi input level internally set fi input carrier frequency 44 − 130 MHz Ri input resistance − 75 − Ω Ci input capacitance − 2.5 − pF RLLNA input return loss − −15 − dB NFLNA noise figure − 7 11 dB Vleak(LO) LO leakage on pin at LNA_IN fN × LO = 140 − 860 MHz; pin LNA_OUT connected to DEMOD_IN − − −15 dBmV fLO/2 = 70 − 130 MHz; pin LNA_OUT connected to DEMOD_IN − −35 −30 dBmV GLNA LNA gain f = 100 MHz; VI(LNA) = 0 dBmV 8 10 − dB Vo output level − −20 − +10 dBmV ∆Vo output flatness in 1 MHz bandwidth; VI(LNA) = 0 dBmV − 0.25 0.5 dB 44 to 70 MHz; VI(LNA) = 0 dBmV − 0.50 − dB 70 to 130 MHz; VI(LNA) = 0 dBmV − 1.3 1.5 dB − −60 dBc IM3 3rd-order intermodulation 2 carriers at +10 dBmV each − at pin LNA_IN at 103 to 105 MHz 1999 Aug 20 6 Philips Semiconductors Product specification QPSK receiver SYMBOL PARAMETER TDA8051 CONDITIONS MIN. TYP. MAX. UNIT Vo(DC) DC output level − 1.3 − V Ro output resistance − 75 − Ω − 1 − V −20 − +10 dBmV Quadrature demodulator: Rs = 75 Ω/Ri = 20 kΩ unless otherwise specified VI(DC) DC input level Vi input level internally set fi input carrier frequency 44 − 130 MHz Ri input resistance − 75 − Ω Ci input capacitance − 2.5 − pF RLI input Return Loss − −12 − dB Vo(I-Q) output level on pin I_OUT1 or Q_OUT1 − 22 − dBmV Bo(I-Q) output 3 dB bandwidth LO = 200 MHz; RF = 100 to 130 MHz − 35 38 MHz C/N carrier to noise ratio at 500 kHz on pin at I_OUT1 or Q_OUT1 VI = −20 dBmV; Vo(I and Q) = 22 dBmV − 88 − dBc/Hz VI = 10 dBmV; Vo(I and Q) = 22 dBmV − 93 − dBc/Hz Vleak(LO) LO leakage on pin DEMOD_IN fLO = 140 to 260 MHz; fLO/2 = 70 to 130 MHz − − −15 dBmV VAGC(r) AGC range fLO = 200 MHz; fRF = 100.25 MHz at −20 to +10 dBmV; fBF = 250 kHz at 22 dBmV 30 − − dB VAGC(s) AGC slope maximum fLO = 200 MHz; fRF = 100.25 MHz at −20 to +10 dBmV; fBF = 250 kHz at 22 dBmV − 30 − dB/V VAGC gain control voltage at AGC_IN Gmax max. conversion gain fLO = 260 MHz; fRF = 130.25 MHz at −20 dBmV; VAGC = 4.5 V 42 − − dB Gmin min. conversion gain fLO = 140 MHz; fRF = 70.25 MHz at 10 dBmV VAGC = 0.5 V − − 12 dB ∆ΦI-Q phase error between I and Q channels fLO = 140 to 260 MHz; fRF = 70.25 to 130.25 MHz; fBF = 250 kHz at 22 dBmV over specified input range − ±3 − deg ∆GI-Q gain error between I and Q channels fLO = 140 to 260 MHz; fRF = 70.25 to 130.25 MHz; fBF = 250 kHz at 22 dBmV over specified input range − ±1 − dB 1999 Aug 20 10% VCCA − 7 90% VCCA V Philips Semiconductors Product specification QPSK receiver SYMBOL TDA8051 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT ∆ΦI-Q phase error between I and Q channels fLO = 88 to 140 MHz; fRF = 44.25 to 70.25 MHz; fBF = 250 kHz at 22 dBmV over specified input range − ±3 − deg ∆GI-Q gain error between I and Q channels fLO = 88 to 140 MHz; fRF = 44.25 to 70.25 MHz; fBF = 250 kHz at 22 dBmV over specified input range − ±1 − dB IM3 3rd-order intermodulation in I and Q channels see Fig.3 − − −45 dBc IM2 2nd-order intermodulation in I and Q channels see Fig.3 − − −40 dBc AMREJ AM rejection at I and Q channels guaranteed by design; see Fig.4 − − −38 dBc ∆Vo(I/Q) output flatness at I and Q outputs in 1 MHz bandwidth − 0.25 − dB f = 40 to 70 MHz − 3 − dB f = 70 to 130 MHz − 3 − dB Vo(DC) DC output level − 2.5 − V Ro output resistance − 400 − Ω Output section: Rs = 400 Ω/Ri = 4 kΩ/R on pin I_OUT2 or Q_OUT2 = 20 kΩ unless otherwise specified VI(DC) DC input voltage − 3.6 − V Vi input level − 22 − dBmV Ri input resistance − 17.5 − kΩ Ci input capacitance − 0.4 − pF GO gain from I-Q_IN1 to I-Q_OUT2 fBF = 1 MHz at 22 dBmV − 3.8 − dB fBF = 0 to 1.5 MHz − 0.25 − dB 1 − dB − 2.6 − V ∆Vo(I-Q_out2) output flatness on pins I_OUT2 and Q_OUT2 fBF = 0 to 6 MHz at 22 dBmV − input Vo(flt) DC output level at filter output Ro output resistance f < 20 MHz − 250 − Ω H2 2nd harmonic fBF = 1 MHz at 48 dBmV output − −40 −35 dBc H3 3rd harmonic fBF = 1 MHz at 48 dBmV − −45 −40 dBc output IM3 3rd-order intermodulation at pins I_OUT and Q_OUT see Fig.5 − −50 −45 dBc αCT(I-Q) crosstalk between I and Q channels f = 5 MHz; see Fig.6 − −40 −30 dBc No output noise power at 500 kHz from carrier see Fig.7 − −56 − dBmv/Hz GI-Q gain from I-Q_IN1 to I-Q_OUT fBF = 1 MHz at 22 dBmV input − 27 − dB 1999 Aug 20 8 Philips Semiconductors Product specification QPSK receiver SYMBOL TDA8051 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V1(I-Q) DC output level on pin I-Q_OUT − 3.1 − V Ro(dif) output differential resistance − 460 − Ω Overall: Rs = 75 Ω/Ri = 4 kΩ unless otherwise specified Vo voltage output on pins I_OUT and Q_OUT see Fig.8 − 48 − dBmV LOlev LO level on pins I_OUT and Q_OUT see Fig.8 − − −45 dBc So spurious emission on pins I_OUT and Q_OUT f = 0 to 5 MHz; see Fig.8 − −40 − dBc ∆GI-Q gain error on pins I_OUT and Q_OUT see Fig.8 − ±1 − dB AMR AM rejection in I and Q channels guaranteed by design; see Fig.9 − − −40 dBc IM3 3rd-order intermodulation guaranteed by design; see Fig.10 − − −45 dBc Voltage Controlled Oscillator (VCO) fvco(min) min. oscillation frequency note 1 − 88 − MHz fvco(max) max. oscillation frequency note 1 − 260 − MHz αN(osc) oscillator phase noise at 10 kHz − −75 − dBc/Hz at 100 kHz − −95 − dBc/Hz Phase Locked Loop (PLL) Step frequency step size 100 − 500 kHz RD fixed reference divider ratio − 2 − − RDR programmable reference divider ratio 2 − 80 − ND programmable fix main divider ratio − 4 − − NDR main divider ratio 128 − 2600 − I(CP) charge pump current − 300 − µA at pin VCO output Crystal oscillator fxtal crystal frequency rxtal = 25 to 200 Ω 1 − 4 MHz Zi crystal oscillator input impedance (absolute value) fxtal = 4 MHz 600 120 0 − Ω VI(DC) DC input level − 2.9 − V Vi input level − 30 − mVrms 1999 Aug 20 9 Philips Semiconductors Product specification QPSK receiver SYMBOL TDA8051 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 3-wire bus VIL input Low level guaranteed by design − − 0.8 V VIH input High level guaranteed by design 2.4 − − V fclk clock frequency guaranteed by design − 330 − kHz tsu input data to CLK set-up time guaranteed by design − 2 − µs th input data to CLK hold time guaranteed by design − 1 − µs td(strt) delay to rising clock edge guaranteed by design − 3 − µs td(stp) delay from last clock edge guaranteed by design − 3 − µs Notes 1. The frequency range of the receiver is 44 to 130 MHz. The local oscillator (LO) operates at twice the output frequency (88 to 260 MHz). Frequency control by varicap diodes allows a variation over one octave. 2. Crystal oscillator. The crystal oscillator uses a 4, 2 or 1 MHz crystal in series with a capacitor. The crystal is parallel resonant with load capacitance of 18 to 20 pF. Connection to VCC is preferred but can also be to GND. Note to characteristics × handbook, full pagewidth DEMOD_IN I_OUT1 VCO 200 MHz 0¡ 90¡ +5 V 105 MHz × 103 MHz 10 dB above max. input level = 20 dBmVrms each tone +10 dB = 32 dBmVrms each tone nominal output level = 22 dBmVrms each tone maximum input level 103 105 Q_OUT1 IM3 IM2 1 f (MHz) 2 3 5 7 f (MHz) FCE172 Fig.3 IM2 and IM3 measurement of the demodulator. 1999 Aug 20 10 Philips Semiconductors Product specification QPSK receiver TDA8051 × handbook, full pagewidth DEMOD_IN I_OUT1 VCO 200 MHz 0¡ 90¡ +5 V 105 MHz × 103 MHz 10 dB above max. input level = 20 dBmVrms Q_OUT1 + 22 dBmVrms maximum input level AM_REJ 103 105 f (MHz) 3 baseband demodulated AM (15 KHz spacing) f (MHz) AM sidebands (15 KHz offset) FCE173 Fig.4 AM rejection test. I_OUT2 handbook, full pagewidth I_OUT I_OUTC Q_OUT 22 dBmV 300 kHz 22 dBmV 500 kHz Q_OUTC Q_OUT2 Fig.5 IM3 measurement of the output section. 1999 Aug 20 11 FCE174 Philips Semiconductors Product specification QPSK receiver TDA8051 I_OUT2 handbook, halfpage I_OUT I_OUTC Q_OUT Q_OUTC 22 dBmV 5 MHz Q_OUT2 FCE175 (1) Measure I and Q, α is the difference between the two carriers. Fig.6 Crosstalk measurement. Q_OUT handbook, halfpage RS 2 kΩ Q_OUTC Q_OUT2 FCE176 Fig.7 Noise measurement. Q_OUT handbook, full pagewidth 10 nF 1.2 kΩ Q_OUT1 100 pF Q_OUTC Q_OUT2 FCE177 LNA input: −15 dBmV; AGC set in order to have a 250 kHz output sine wave at 48 dBmV; fref = 70 to 130 MHz; flo = 140 to 260 MHz. Fig.8 LO level, spurious, I/Q gain error and Vo measurements. 1999 Aug 20 12 Philips Semiconductors Product specification QPSK receiver TDA8051 × handbook, full pagewidth LNA_IN I_OUT1 VCO 200 MHz 0¡ 90¡ +5 V 100.3 MHz 102 MHz × Q_OUT1 100 % AM modulation square wave 15 kHz input signals at LNA_IN I_OUT or Q_OUT +42 dBm(Vrms) +10 dBmV AM_REJ 0 dBmV 100.3 102 f (MHz) baseband demodulated AM (15 KHz spacing) 300 f (MHz) AM sidebands (15 KHz offset) FCE178 Fig.9 Overall AM rejection measurement. × handbook, full pagewidth LNA_IN 0° 90° +5 V 100.5 MHz 100.3 MHz × I_OUT1 VCO 200 MHz Q_OUT1 +42 dB dBm(Vrms) each tone 0 dB dBm(Vrms) each tone IM3 IM2 100.3 100.5 100 200 300 f (MHz) 500 700 f (kHz) FCE179 Fig.10 Overall IM3 measurement. 1999 Aug 20 13 Philips Semiconductors Product specification QPSK receiver TDA8051 TIMING CHARACTERISTICS tH t sup handbook, full pagewidth t xtal CLK DATA EN t strt t stp FCE180 Fig.11 Logic interface signals. DATA FORMAT Table 1 FIRST LAST Data D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 AD1 AD0 X X R7 R6 R5 R4 R3 R2 R1 R0 0 1 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 1 1 Reference ratio X X Principal ratio P11 P10 1999 Aug 20 14 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 32 Q_OUT 31 Q_OUTC TDA8051 I_OUT2 3 30 Q_OUT2 29 Q_IN1 I_IN1 4 Q CHANNEL FILTERING 28 Q_OUT1 I_OUT1 5 A1VCC Philips Semiconductors I_OUT 1 QPSK receiver Q DATA BUFFERED BALANCED OUTPUT I_OUTC 2 I CHANNEL FILTERING APPLICATION INFORMATION 1999 Aug 20 I DATA BUFFERED BALANCED OUTPUT 27 × 6 DEMOD_IN 7 0¡ 15 LNA_OUT 8 OUTVCC 26 × 25 90¡ 23 OUTGND A3VCC 24 A2GND A2VCC 1/2 22 LNA_IN 9 RF INPUT A1GND 10 1/4 AGC_IN 11 CLK DATA EN 1/2 1/RDR CMP 20 14 16 Voltage Controlled Oscillator 1/NDR 13 15 21 TKB OSC_IN 12 DVCC TKA DGND 19 TUNE BUS CHARGE PUMP 18 CP handbook, full pagewidth +30 V TDA8051 Fig.12 Application diagram. FCE113 TEST n.c. Product specification 17 3-WIRE BUS Philips Semiconductors Product specification QPSK receiver TDA8051 INTERNAL PIN CONFIGURATIONS SYMBOL PIN DESCRIPTION DC VOLTAGE I_OUT 1 3.1 V I_OUTC 2 3.1 V 2 1 OUTGND I_OUT2 FCE025 3 2.6 V 3 OUTGND I_IN1 FCE026 4 3.6 V 4 OUTGND I_OUT1 FCE027 2.5 V 5 OUTGND A1VCC 1999 Aug 20 6 Analog supply voltage 1 16 FCE028 5V Philips Semiconductors Product specification QPSK receiver SYMBOL DEMOD_IN TDA8051 PIN DESCRIPTION DC VOLTAGE 7 1V 7 FCE127 LNA_OUT A1GND 8 1.3 V 8 A1GND LNA_IN FCE128 9 0.9 V 9 A1GND A1GND 10 AGC_IN 11 FCE129 analog ground 1 0. V − 11 FCE030 A2GND 1999 Aug 20 17 Philips Semiconductors Product specification QPSK receiver SYMBOL OSC_IN TDA8051 PIN DESCRIPTION DC VOLTAGE 12 3.0 V DVCC 12 FCE031 DVCC 13 CLK 14 digital supply voltage 5V n.a. 14 FCE032 DATA 15 n.a. 15 FCE033 EN 16 n.a. 16 FCE034 TEST 17 CP 18 not connected n.a. 1.9 V DVCC DOWN 18 UP FCE035 1999 Aug 20 18 Philips Semiconductors Product specification QPSK receiver SYMBOL TUNE TDA8051 PIN DESCRIPTION DC VOLTAGE 19 VVT 19 FCE036 DGND 20 0V 20 SUB FCE037 TKB 21 2.4 V TKA 22 2.4 V 21 22 FCE038 A2GND A2VCC 23 analog DC supply voltage 2 5V A2GND 24 analog ground 2 0V A3VCC 25 analog supply voltage 3 5V OUTGND 26 0V 26 DGND OUTVCC 27 Q_OUT1 28 FCE040 output amplifiers supply voltage 2.5 V 28 OUTGND 1999 Aug 20 5V 19 FCE041 Philips Semiconductors Product specification QPSK receiver SYMBOL Q_IN1 TDA8051 PIN DESCRIPTION DC VOLTAGE 29 3.6 V 29 OUTGND Q_OUT2 FCE042 30 2.6 V 30 OUTGND FCE043 Q_OUTC 31 3.1 V Q_OUT 32 3.1 V 31 OUTGND 1999 Aug 20 32 OUTGND 20 FCE044 Philips Semiconductors Product specification QPSK receiver TDA8051 PACKAGE OUTLINE SO32: plastic small outline package; 32 leads; body width 7.5 mm SOT287-1 D E A X c y HE v M A Z 17 32 Q A2 A (A 3) A1 pin 1 index θ Lp L 16 1 0 detail X w M bp e 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.27 0.18 20.7 20.3 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.2 1.0 0.25 0.25 0.1 0.95 0.55 inches 0.10 0.012 0.096 0.004 0.086 0.01 0.02 0.01 0.011 0.007 0.81 0.80 0.30 0.29 0.050 0.419 0.394 0.055 0.043 0.016 0.047 0.039 0.01 0.01 0.004 0.037 0.022 θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-01-25 97-05-22 SOT287-1 1999 Aug 20 EUROPEAN PROJECTION 21 Philips Semiconductors Product specification QPSK receiver TDA8051 • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: 1999 Aug 20 22 Philips Semiconductors Product specification QPSK receiver TDA8051 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE not suitable(2) HLQFP, HSQFP, HSOP, SMS PLCC(3), SO suitable suitable suitable LQFP, QFP, TQFP not recommended(3)(4) suitable SQFP not suitable suitable SSOP, TSSOP, VSO not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Aug 20 23 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545004/25/02/pp24 Date of release: 1999 Aug 20 Document order number: 9397 750 04691