INTEGRATED CIRCUITS DATA SHEET SAA7197 Clock Generator Circuit for desktop video systems (CGC) Product specification File under Integrated Circuits, IC22 August 1996 Philips Semiconductors Product specification Clock Generator Circuit for desktop video systems (CGC) SAA7197 FEATURES GENERAL DESCRIPTION • Suitable for Desktop Video systems The SAA7197 generates all clock signals required for a digital TV system suitable for the SAA719x family. The circuit operates in either the phase-locked loop mode (PLL) or voltage controlled oscillator mode (VCO). • Two different sync sources selectable • PLL frequency multiplier to generate 4 times of input frequency • Dividers to generate clocks LLCA, LLCB, LLC2A and LLC2B (2nd and 4th multiples of input frequency) • PLL mode or VCO mode selectable • Reset control and power fail detection QUICK REFERENCE DATA SYMBOL PARAMETER MIN. 4.5 TYP. 5.0 MAX. 5.5 UNIT VDDA analog supply voltage (pin 5) V VDDD digital supply voltage (pins 8, 17) 4.5 5.0 5.5 V IDDA analog supply current 3 − 9 mA IDDD digital supply current 10 − 60 mA VLFCO LFCO input voltage (peak-to-peak value) 1 − VDDA V fi input frequency range 5.5 − 8.0 MHz VI input voltage LOW 0 − 0.8 V input voltage HIGH 2.0 − VDDD V output voltage LOW 0 − 0.6 V output voltage HIGH 2.6 − VDDD V operating ambient temperature range 0 − 70 °C VO Tamb ORDERING INFORMATION PACKAGE EXTENDED TYPE NUMBER PINS PIN POSITION MATERIAL CODE SAA7197P 20 DIP plastic SOT146-1 SAA7197T 20 SO plastic SOT163-1 August 1996 2 Philips Semiconductors Product specification Clock Generator Circuit for desktop video systems (CGC) SAA7197 BLOCK DIAGRAM handbook, full pagewidth V DDA V DDD1 V DDD2 5 MS 8 17 1 SAA7197 LOOP FILTER 7 VCO PHASE DETECTOR 10 FREQUENCY DIVIDER 1:2 MS = LOW 14 FREQUENCY DIVIDER 1:2 20 DELAY LFCO 11 PRE-FILTER AND PULSE SHAPER 15 POWER-ON RESET 12 LFCO2 19 CE LLCA LLCB LLC2A LLC2B CREF RESN 2 16 LFCOSEL 4 6, 9, 13, 18 V SSA V SSD 3 PORD MEH461 Fig.1 Block diagram. The input signal LFCO or LFCO2 is multiplied by factors 2 or 4 in the PLL (including phase detector, loop filter, VCO and frequency divider) and output on LLCA (pin7), LLCB (pin 10), LLC2A (pin 14) and LLC2B (pin 20). The rectangular output signals have 50% duty factor. Outputs with equal frequency may be connected together externally. The clock outputs go HIGH during power-on reset (and chip enable) to ensure that no output clock signals are available the PLL has locked-on. FUNCTION DESCRIPTION The SAA7197 generates all clock signals required for a digital TV system suitable for the SAA719x family consisting of an 8-bit analog-to-digital converter (ADC8), digital video multistandard decoder, square pixel (DMSD-SQP), digital video colour space converter (DCSC) and optional extensions. The SAA7197 completes a system for Desktop Video applications in conjunction with memory controllers. Mode select MS The input signal LFCO is a digital-to-analog converted signal provided by the DMDS-SQPs horizontal PLL. It is the multiple of the line frequency: The LFCO input signal is directly connected to the VCO at MS = HIGH. The circuit operates as an oscillator and frequency divider. This function is not tested. 7.38 MHz = 472 × fH in 50 Hz systems 6.14 MHz = 360 × fH in 60 Hz systems LFCO2 (TTL-compatible signal from an external reference source) can be applied to pin 19 (LFCOSEL = HIGH). August 1996 3 Philips Semiconductors Product specification Clock Generator Circuit for desktop video systems (CGC) SAA7197 Source select LFCOSEL Power-on reset Line frequency control signal LFCO (pin 11) is selected by LFCOSEL = LOW. LFCOSEL = HIGH selects LFCO2 input signal (pin 19). This function is not tested. Power-on reset is activated at power-on, when the supply voltage decreases below 3.5 V (Fig.4) or when chip enable is done. The indicator output RESN is LOW for a time determined by capacitor on pin 3. The RESN signal can be applied to reset other circuits of this digital TV system. The LFCO or LFCO2 input signals have to be applied before RESN becomes HIGH. Chip enable CE The buffer outputs are enabled and RESN set HIGH by CE = HIGH (Fig.4). CE = LOW sets the clock outputs HIGH and RESN output LOW. CREF output 2 fLFCO output to control the clock dividers of the DMSD-SQP chip family. PINNING SYMBOL PIN CONFIGURATION PIN DESCRIPTION MS 1 mode select input (LOW = PLL mode)(1) CE 2 chip enable /reset (HIGH = outputs enabled) PORD 3 power-on reset delay, dependent on external capacitor VSSA 4 analog ground (0 V) MS 1 20 LLC2B VDDA 5 analog supply voltage (+5 V) CE 2 19 LFCO2 VSSD1 6 digital ground 1 (0 V) PORD 3 18 VSSD4 LLCA 7 line-locked clock output signal (4 times fLFCO) 17 VDDD2 8 digital supply voltage 1 (+5 V) VSSA 4 VDDD1 VSSD2 9 digital ground 2 (0 V) VDDA 5 LLCB 10 line-locked clock output signal (4 times fLFCO) LFCO 11 line-locked frequency control input signal 1 RESN 12 VSSD3 LLC2A halfpage 16 LFCOSEL SAA7197 VSSD1 6 15 CREF LLCA 7 14 LLC2A reset output (active-LOW, Fig.4) VDDD1 8 13 VSSD3 13 digital ground 3 (0 V) VSSD2 9 12 RESIN 14 line-locked clock output signal 2A (2 times fLFCO) CREF 15 clock reference output, qualifier signal (2 times fLFCO) LFCOSEL 16 LFCO source select (LOW = LFCO selected)(1) VDDD2 17 digital supply voltage 2 (+5 V) VSSD4 18 digital ground 4 (0 V) LFCO2 19 line-locked frequency control input signal 2(1) LLC2B 20 line-locked clock output signal 2B (2 times fLFCO) Note 1. MS and LFCO2 functions are not tested. LFCO2 is a multiple of horizontal frequency. August 1996 4 LLCB 10 11 LFCO MGL505 Fig.2 Pin configuration. Philips Semiconductors Product specification Clock Generator Circuit for desktop video systems (CGC) SAA7197 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); ground pins as well as supply pins together connected. SYMBOL PARAMETER MIN. MAX. UNIT VDDA analog supply voltage (pin 5) −0.5 7.0 V VDDD digital supply voltage (pins 8 and 17) −0.5 7.0 V Vdiff GND difference voltage VDDA − VDDD − ±100 mV VO output voltage (IOM = 20 mA) −0.5 VDDD V Ptot total power dissipation (DIL20) 0 1.1 W Tstg storage temperature range −65 150 °C Tamb operating ambient temperature range 0 70 °C VESD handling(1) − tbf V electrostatic for all pins Note 1. Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is recommended to take normal handling precautions appropriate to “Handling MOS devices”. CHARACTERISTICS VDDA = VDDD = 4.5 to 5.5 V; fLFCO = 5.5 to 8.0 MHz and Tamb = 0 to 70 °C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDDA analog supply voltage (pin 5) 4.5 5.0 5.5 V VDDD digital supply voltage (pins 8 and 17) 4.5 5.0 5.5 V IDDA analog supply current (pin 5) 3 − 9 mA IDDD digital supply current (I8 + I17) note 1 10 − 60 mA Vreset power-on reset threshold voltage Fig.4 − 3.5 - V Input LFCO (pin 11) V11 DC input voltage 0 − VDDA V Vi input signal (peak-to-peak value) 1 − VDDA V fLFCO input frequency range 5.5 − 8.0 MHz C11 input capacitance − − 10 pF Inputs MS, CE, LFCOSEL and LFCO2 (pins 1, 2, 16 and 19); note 3 VIL input voltage LOW 0 − 0.8 V VIH input voltage HIGH 2.0 − VDDD V fLFCO2 input frequency range for LFCO2 5.5 − 8.0 MHz ILI input leakage current LFCOSEL 50 − 150 µA others − − 10 µA − − 5 pF CI input capacitance Output RESN (pin 12) VOL output voltage LOW IOL = 2 mA 0 − 0.4 V VOH output voltage HIGH IOH = −0.5 mA 2.4 − VDDD V td RESN delay time C3 = 0.1 µF; Fig.4 20 − 200 ms August 1996 5 Philips Semiconductors Product specification Clock Generator Circuit for desktop video systems (CGC) SYMBOL PARAMETER CONDITIONS SAA7197 MIN. TYP. MAX. UNIT Output CREF (pin 15) VOL output voltage LOW IOL = 2 mA 0 − 0.6 V VOH output voltage HIGH IOH = −0.5 mA 2.4 − VDDD V fCREF output frequency CREF Fig.3 − 2 fLFCO(2) CL output load capacitance 15 − 40 pF tSU set-up time Fig.3; note 1 12 − − ns tHD hold time Fig.3; note 1 4 − − ns MHz Output signals LLCA, LLCB, LLC2A and LLC2B (pins 7, 10, 14, and 20); note 3 VOL output voltage LOW IOL = 2 mA 0 − 0.6 V VOH output voltage HIGH IOH = −0.5 mA 2.6 − VDDD V tcomp composite rise time Fig.3; notes 1 and 2 − − 8 ns output frequency LLCA Fig.3 fLL − 4 fLFCO(2) MHz output frequency LLCB − 4 fLFCO(2) MHz output frequency LLC2A − 2 fLFCO(2) MHz − 2 fLFCO(2) tr, tf rise and fall times Fig.3 − − 5 ns tLL duty factor LLCA, LLCB, LLC2A and LLC2B (mean values) note 1; Fig.3; at 1.5 V level 40 50 60 % output frequency LLC2B MHz Notes 1. fLFCO = 7.0 MHz and output load 40 pF (Fig.3). VSSA and VSSD short connected together. 2. tcomp is the rise time from LOW of all clocks to HIGH of all clocks (Fig.3) including rise time, skew and jitter components. Measurements taken between 0.6 V and 2.6 V. Skew between two LLx clocks will not deviate more than ±2 ns if output loads are matched within 20%. 3. MS and LFCO2 functions not tested. August 1996 6 Philips Semiconductors Product specification Clock Generator Circuit for desktop video systems (CGC) SAA7197 handbook, full pagewidth 2.4 V CREF 0.6 V t HD t HD t SU t LLC t LLC L t LLC H 2.6 V LLCA LLCB 1.5 V 0.6 V tf tr t LLC2 t LLC2 L t LLC2 H 2.6 V LLC2A LLC2B 1.5 V 0.6 V t comp tf tr MEH466 Fig.3 Output timing. August 1996 7 Philips Semiconductors Product specification Clock Generator Circuit for desktop video systems (CGC) SAA7197 handbook, full pagewidth +3.5 V V DDA V DDD 0V power-on oscillation disturbed LFCO oscillation RESN td td normal operation normal operation LLCA LLCB LLC2A LLC2B power failure starts a new reset procedure PLL lock-on clock HIGH during internal reset reset time MEH467 Fig.4 Reset procedure. handbook, full pagewidth 1 2 16 19 VDDD VDDD 7 10 14 15 20 MS CE LFCOSEL LFCO2 LLCA LLCB LLC2A LLC2B CREF VSSD VSSD VDDD 11 12 LFCO RESN VSSD Fig.5 Internal circuit. August 1996 8 MEH469 Philips Semiconductors Product specification Clock Generator Circuit for desktop video systems (CGC) SAA7197 PACKAGE OUTLINES DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 ME seating plane D A2 A A1 L c e Z b1 w M (e 1) b MH 11 20 pin 1 index E 1 10 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 inches 0.17 0.020 0.13 0.068 0.051 0.021 0.015 0.014 0.009 1.060 1.045 D e e1 L ME MH w Z (1) max. 6.40 6.22 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.0 0.25 0.24 0.10 0.30 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.078 (1) E (1) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT146-1 August 1996 REFERENCES IEC JEDEC EIAJ SC603 9 EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-05-24 Philips Semiconductors Product specification Clock Generator Circuit for desktop video systems (CGC) SAA7197 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.050 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013AC August 1996 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-24 97-05-22 10 Philips Semiconductors Product specification Clock Generator Circuit for desktop video systems (CGC) Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. WAVE SOLDERING This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Wave soldering techniques can be used for all SO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. DIP SOLDERING BY DIPPING OR BY WAVE • The longitudinal axis of the package footprint must be parallel to the solder flow. The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. • The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. REPAIRING SOLDERED JOINTS A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. August 1996 SAA7197 11 Philips Semiconductors Product specification Clock Generator Circuit for desktop video systems (CGC) SAA7197 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. August 1996 12 Philips Semiconductors Product specification Clock Generator Circuit for desktop video systems (CGC) NOTES August 1996 13 SAA7197 Philips Semiconductors Product specification Clock Generator Circuit for desktop video systems (CGC) NOTES August 1996 14 SAA7197 Philips Semiconductors Product specification Clock Generator Circuit for desktop video systems (CGC) NOTES August 1996 15 SAA7197 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 657027/00/01/pp16 Date of release: August 1996 Document order number: 9397 750 02438