PHILIPS TDA9845T

INTEGRATED CIRCUITS
DATA SHEET
TDA9845
TV and VTR stereo/dual sound
processor with digital identification
Preliminary specification
Supersedes data of January 1993
File under Integrated Circuits, IC02
Philips Semiconductors
1995 Mar 20
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9845
FEATURES
GENERAL DESCRIPTION
• Supply voltage 5 to 8 V
The TDA9845 is a stereo/dual sound processor for TV and
VTR sets. Its identification ensures safe operation by using
internal digital PLL technique with extremely small
bandwidth, synchronous detection and digital integration
(switching time maximum 2.1 s; identification concerning
the main functions).
• Source selector
• Stereo matrix
• AF input for mono source
• AF outputs for Main
• LED operation mode indication (stereo and dual)
• High identification reliability.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
VP
supply voltage (pin 18)
IP
supply current (pin 18)
without LED current
Vi(rms)
nominal input signal voltage
(Vi 1, Vi 2, Vi 3) (RMS value)
54% modulation
Vo(rms)
nominal output signal voltage
(RMS value)
54% modulation
Vo(rms)
clipping level of the output signal
voltages (RMS value)
THD ≤1.5%
B/G
MIN.
TYP.
MAX.
UNIT
4.5
5
8.8
V
12
13
16.5
mA
−
250
−
mV
−
500
−
mV
−
500
−
mV
VP = 5 V
1.4
1.6
−
V
VP = 8 V
2.4
2.65
−
V
L (only for Vi 1)
ILON
input current
LED ON
−
−
12
mA
Vi pil
input voltage sensitivity of pilot
frequency
unmodulated
5
−
100
mV
S/N(W)
weighted signal-to-noise ratio
“CCIR468-3”
66
75
−
dB
THD
total harmonic distortion
−
0.2
0.3
%
Tamb
operating ambient temperature range
fident
identification window width
tident ON
total identification time ON
Vi tuner
identification voltage sensitivity
∆fpil
pull-in frequency range of pilot PLL
0
−
+70
°C
STEREO
2.2
−
2.2
Hz
DUAL
2.3
−
2.3
Hz
0.35
−
2.1
s
−
28
−
dBµV
lower side
−296
−
−296
Hz
upper side
302
−
302
Hz
fω = 10.008 MHz
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
TDA9845
DIP20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
TDA9845T
SO20
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
1995 Mar 20
DESCRIPTION
2
VERSION
1995 Mar 20
2.2 k Ω
3
100 nF
2.5
mH
47 pF
30 kΩ
4
3
5
6
9
8
15 kΩ
35 kΩ
35 kΩ
15 kΩ
3 dB
0 dB
−6 dB
−3 dB
25 k Ω
25 k Ω
10 k Ω
XTAL
19
OSCILLATOR
DIGITAL
PLL
5 kΩ
10 MHz
TDA9845
10 k Ω
A/MONO
L
L/A/MONO
250 mV RMS
100 µF/
16 V
7
C ref
Cref +
1/2 V P
VP
18
mute
16
500 mV RMS
500 mV RMS
20
2
1
14
15
11
12
MED644 - 1
CONTROL
LOGIC
STEREO
bit
117 Hz
274 Hz
DUAL bit
6 dB
6 dB
POWER-ON
RESET
DIGITAL
INTEGRATOR
DIGITAL
INTEGRATOR
GND
SUPPLY
DIGITAL PLL
AND
DEMODULATOR
2.2 µF
10
AM
250 mV RMS
R/B
250 mV RMS
−6 dB
17
DIGITAL PLL
AND
DEMODULATOR
Vref
5 kΩ
50 k Ω
250 mV RMS
Fig.1 Block diagram of the bipolar TV/VTR-stereo decoder.
0 dB
13
10 nF 10 nF
Vi 3
MAIN
C3
C2
C1
dual transmission
LEDDU
LEDST
1 kΩ
VP
stereo transmission
Vo 2
Vo 1
TV and VTR stereo/dual sound processor
with digital identification
Input and output levels are nominal values.
They are related to the SCART norm.
(AM: m = 0.54, FM: ∆f = ±27 kHz).
10 nF
10 µF
+
CLP
CAGC
CDCL
3.3 nF
2.2 µF
2.2 k Ω
+
V i pil
250 mV RMS
R, B
Vi 2
250 mV RMS
(AM: 500 mV RMS)
2.2 µF
+
L+R , A
2
Vi 1
AM
CD2
+
full pagewidth
CD1
Philips Semiconductors
Preliminary specification
TDA9845
BLOCK DIAGRAMS
1995 Mar 20
2.2 k Ω
4
100 nF
4.7
mH
±5%
4
3
5
6
9
15 kΩ
35 kΩ
35 kΩ
15 kΩ
3 dB
0 dB
25 k Ω
25 k Ω
10 k Ω
XTAL
19
OSCILLATOR
DIGITAL
PLL
5 kΩ
10 MHz
TDA9845
10 k Ω
A/MONO
AM
L
L/A/MONO
250 mV RMS
100 µF /
16 V
+
7
C ref
1/2 VP
GND
16
CONTROL
LOGIC
STEREO
bit
117 Hz
274 Hz
POWER-ON
RESET
DIGITAL
INTEGRATOR
20
2
1
14
15
11
12
MED645 - 1
500 mV RMS
500 mV RMS
DUAL bit
6 dB
6 dB
MAIN
C3
C2
C1
dual transmission
LEDDU
LEDST
1 kΩ
VP
stereo transmission
Vo 2
Vo 1
The components of the external LC band-pass filter have the following order-No.:
Philips Germany only No: 431202017525 or Fastron Sdn. Bha., Malaysia type
SMCC 472 J for L = 4.7 MHz (±5%)
Philips Components No: 2222 429 71802, C = 1.8 nF (±2%).
VP
18
SUPPLY
DIGITAL PLL
AND
DEMODULATOR
DIGITAL
INTEGRATOR
mute
AM
250 mV RMS
50 k Ω
R/B
250 mV RMS
−6 dB
17
DIGITAL PLL
AND
DEMODULATOR
Vref
5 kΩ
10
Fig.2 Block diagram of the bipolar TV/VTR-stereo decoder with fixed coil (alignment-free).
0 dB
−6 dB
−3 dB
250 mV RMS
2.2 µF
Vi 3
TV and VTR stereo/dual sound processor
with digital identification
Input and output levels are nominal values.
They are related to the SCART norm.
(AM: m = 0.54, FM: ∆f = ±27 kHz).
10 nF
10 µF
+
CLP
CAGC
C DCL
18 nF
±2%
180 pF
27 kΩ
+
V i pil
250 mV RMS
R, B
2.2 µF
2.2 k Ω
8
book, full pagewidth
Vi 2
250 mV RMS
(AM: 500 mV RMS)
2.2 µF
+
L+R , A
2
Vi 1
13
10 nF 10 nF
CD2
+
CD1
Philips Semiconductors
Preliminary specification
TDA9845
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9845
PINNING
SYMBOL
PIN
DESCRIPTION
C1
1
control input Port C1
C2
2
control input Port C2
CAGC
3
AGC capacitor of pilot frequency amplifier
CLP
4
identification low-pass capacitor
CDCL
5
DC loop capacitor
Vi pil
6
pilot frequency input voltage
Cref
7
capacitor of reference voltage (1⁄2VP)
Vi 1
8
AF input signal voltage 1 (from sound carrier 1 or
AM sound (standard L)
lfpage
C1
1
20 C3
C2
2
19 XTAL
CAGC
3
18 V P
CLP
4
17 CD2
CDCL
5
16 GND
TDA9845
Vi 2
9
AF input signal voltage 2 (from sound carrier 2)
V i pil
6
15 LEDST
Vi 3
10
AF input signal voltage 3 (Mono sound)
Cref
7
14 LEDDU
Vi 1
8
13 CD1
Vi 2
9
12 Vo 1
Vi 3 10
11 Vo 2
Vo 2
11
AF output signal voltage 2 (Main)
Vo 1
12
AF output signal voltage 1 (Main)
CD1
13
50 µs de-emphasis capacitor of AF Channel 1
LEDDU
14
LED (dual)
LEDST
15
LED (stereo)
GND
16
ground (0 V)
CD2
17
50 µs de-emphasis capacitor of AF Channel 2
VP
18
supply voltage (+5 to +8 V)
XTAL
19
10 MHz crystal input
C3
20
control input Port C3
1995 Mar 20
MED646
Fig.3 Pin configuration.
5
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9845
The identification signal is amplified and fed through an
AGC low-pass filter with external capacitor CAGC (pin 3) to
obtain the AGC voltage for controlling the gain of the pilot
signal amplifier.
FUNCTIONAL DESCRIPTION
AF signal handling
The input AF signals, derived from the two sound carriers,
are processed in analog form using operational amplifiers.
Dematrixing uses the technique of two amplifiers
processing the AF signals. Finally, a source selector
provides the facility to route the mono signal through to the
outputs (‘forced mono’).
The identification stages consist of two digital PLL circuits
with digital synchronous demodulation and digital
integrators to generate the stereo or dual sound
identification bits which can be indicated via LEDs.
A 10 MHz crystal oscillator provides the reference clock
frequency. The corresponding detection bandwidth is
larger than ±50 Hz for the pilot carrier signal, so that
fp-variations from the transmitter can be tracked in the
event of missing synchronization with the horizontal
frequency fH. However the detection bandwidth for the
identification signal is made small (±1 Hz) to reduce
mis-identification.
De-emphasis is performed by two RC low-pass filter
networks with internal resistors and external capacitors.
This provides a frequency response with the tolerances
given in Fig.4.
A source selector, controlled via the control input ports
allows selection of the different modes of operation in
accordance with the transmitted signal. The device was
designed for a nominal input signal (FM: 54% modulation
is equivalent to ∆f = ±27 kHz) of 250 mV RMS (Vi 1, Vi 2)
and for a nominal input signal (AM: m = 0.54) of 500 mV
RMS (Vi 1), respectively 250 mV RMS (Vi 3). A nominal
gain of 6 dB for Vi 1 and Vi 2 signals (0 dB for Vi 1 signal
(AM sound)) and 6 dB for Vi 3 signal is built-in. By using
rail-to-rail operational amplifiers, the clipping level
(THD ≤1.5%) is 1.60 V RMS for VP = 5 V and 2.65 V RMS
for VP = 8 V at outputs Vo 1, Vo 2. Care has been taken to
minimize switching plops. Also total harmonic distortion
and random noise are considerably reduced.
Figure 2 shows an example of the alignment-free fp
band-pass filter. To achieve the required QL of around 12,
the Q0 at fp of the coil was chosen to be around 25
(effective Q0 including PCB influence). Using coils with
other Q0, the RC-network (RFP, CFP) has to be adapted
accordingly. It is assumed that the loss factor tanδ of the
resonance capacitor is ≤0.01 at fp.
Copper areas under the coil might influence the loaded Q
and have to be taken into account. Care has also to be
taken in environments with strong magnetic fields when
using coils without magnetic shielding.
Identification
Control input ports
The pilot signal is fed via an external RC high-pass filter
and single tuned LC band-pass filter to the input of a gain
controlled amplifier. The external LC band-pass filter in
combination with the external RC high-pass filter should
have a loaded Q-factor of approximately 40 to 50 to
ensure the highest identification sensitivity. By using a
fixed coil (±5%) to save the alignment (see Fig.2), a
Q-factor of approximately 12 is proposed. This may cause
a loss in sensitivity of approximately 2 to 3 dB. A digital
PLL circuit generates a reference carrier, which is
synchronized with the pilot carrier. This reference carrier
and the gain controlled pilot signal are fed to the
AM-synchronous demodulator. The demodulator detects
the identification signal, which is fed through a low-pass
filter with external capacitor CLP (pin 4) to a Schmitt-trigger
for pulse shaping and suppression of low level spurious
signal components. This is a measure against
mis-identification.
1995 Mar 20
The complete IC is controlled by the three control input
ports C1, C2 and C3 (TTL-level). With these ports the user
can select between different AF sources according to the
transmitter status (see Table 1). Finally Schmitt-triggers
are added in the input port interfaces to suppress spikes
from the control lines C1, C2 and C3.
After a power-on reset, the logic is reset (mute mode for
the AF channel). After some time (≤1 ms), when the
power-on reset is automatically deactivated, the switch
position of the Main channel is changed according to the
control input port levels C1, C2 and C3.
For standard L, the AM sound is fed via the AF input (Vi 1)
to the two AF outputs (Vo 1,Vo 2). This can also be
achieved by feeding at AF input Vi 3.
The logic level combination 111 of the control input ports
(C3, C2 and C1) is not allowed (see Table 1).
6
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9845
Power supply
ESD protection
The different supply voltages and currents required for the
analog and digital circuits are derived from an internal
band-gap reference circuit. The AF reference voltage is
1⁄ V . For a fast setting to 1⁄ V an internal start-up circuit
2 P
2 P
is added. A good ripple rejection is achieved with the
external capacitor Cref = 100 µF/16 V in conjunction with
the high ohmic input of the 1⁄2VP pin (pin 7). No additional
DC load on this pin is allowed.
All pins are ESD protected. The protection circuits
represent the latest state of the art.
Internal circuit
The internal pin loading diagram is given in Fig.7.
Power-on reset
When a power-on reset is activated by switching on the
supply voltage or because of a supply voltage breakdown,
the 117/274 Hz DPLL, the 117/274 Hz integrator and the
logic will be reset. The AF channel (Main) is muted
(≤1 ms).
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VP
supply voltage (pin 18)
−0.3
10
V
Vi
voltage at pins 1, 2 and 20
−0.3
9.0
V
Vi
voltage at pins 3 to 13, 17 and 19
−0.3
VP
V
Vi
voltage at pins 14 and 15
−0.3
10
V
Tstg
storage temperature
−25
+150
°C
Tamb
operating ambient temperature
0
+70
°C
Vesd
electrostatic handling for all pins
−500
+500
V
note 1
Note
1. Charge device model class A: discharging a 200 pF capacitor through a Ω series resistor.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
1995 Mar 20
PARAMETER
VALUE
UNIT
thermal resistance from junction to ambient in free air
DIP20
73
K/W
SO20
90
K/W
7
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9845
CHARACTERISTICS
VP = 5 V; Tamb = +25 °C; nominal input signal Vi 1, 2 = 0.25 V RMS value (FM: 54% modulation is equivalent to
∆f = ±27 kHz); nominal input signal Vi 1 = 0.5 V RMS value (AM: m = 0.54); nominal input signal Vi 3 = 0.25 V RMS
value (AM: m = 0.54); nominal output signal Vo 1, 2 = 0.5 V RMS value; fAF = 1 kHz; Vi pil = 16 mV RMS value;
fpil = 54.6875 kHz (identification frequencies: stereo = 117.48 Hz, dual = 274.12 Hz), 50 µs pre-emphasis;
noise measurement in accordance with “CCIR468-3”, working oscillator frequency fω = 10008 MHz;
currents into the IC positive; measured in test circuit Fig.5 unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VP
supply voltage (pin 18)
4.5
IP
supply current (pin 18)
12
13
16.5
mA
Ptot
total power dissipation
54
65
145.2
mW
Vn(DC)
DC voltage
(pins 8 to 13 and 17)
1⁄ V
2 P
− 0.1
1⁄ V
2 P
1⁄
2VP
+ 0.1
V
Vref(DC)
DC reference voltage (pin 7)
1⁄ V
2 P
− 0.1
1⁄ V
2 P
1⁄
2VP
+ 0.1
lL(DC)
DC leakage current (pin 7)
−
−
±1
without LED current
5
8.8
V
V
µA
AF Inputs; Vi 1 and Vi 2 (pins 8 and 9)
Vi(rms)
Vi(rms)
Gv
nominal input signal voltage
(RMS value)
clipping voltage level
(RMS value)
AF signal voltage gain
54% modulation
B/G
−
0.25
−
V
L (only Vi 1)
−
0.5
−
V
THD ≤ 1.5%
VP = 5 V; B/G
0.625
0.715
−
V
VP = 8 V; B/G
1.050
1.200
−
V
VP = 5 V; L (only Vi 1)
1.200
1.600
−
V
VP = 8 V; L (only Vi 1)
2.100
2.356
−
V
5
6
7
dB
G = Vo/Vi; note 1
B/G
−1
0
+1
dB
Ri
input resistance
40
50
60
kΩ
Rdeem
internal de-emphasis resistor see Fig.4
(pins 13 and 17)
4.25
5.0
5.75
kΩ
−
0.25
−
V
−
V
L (only Vi 1)
Additional AF input pin (pin 10)
Vi(rms)
nominal input signal voltage
(RMS value)
54% modulation
Vi(rms)
clipping voltage level
(RMS value)
THD ≤ 1.5%
Gv
AF signal voltage gain
Ri
input resistance
1995 Mar 20
VP = 5 V
0.625
0.715
VP = 8 V
1.050
1.200
5
6
7
dB
40
50
60
kΩ
G = Vo/Vi; note 1
8
V
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
SYMBOL
PARAMETER
TDA9845
CONDITIONS
MIN.
TYP.
MAX.
UNIT
AF outputs (pins 11 and 12)
Vo(rms)
nominal output signal voltage THD ≤ 0.3%;
(RMS value)
54% modulation
Vo(rms)
clipping voltage level
(RMS value)
−
0.5
−
V
1.4
1.6
−
V
THD ≤ 1.5%
VP = 5 V
2.4
2.65
−
V
Ro
output resistance
150
250
350
Ω
CL
load capacitor on output
−
−
1.5
nF
RL
load resistor on output
(AC-coupled)
10
−
−
kΩ
B
frequency response
(bandwidth)
fi = 40 to 20000 Hz;
note 2
−0.5
−
+0.5
dB
B−3 dB
frequency response
−3 dB; note 2
300
350
400
kHz
THD
total harmonic distortion
note 1
−
0.2
0.3
%
S/N(W)
weighted signal-to-noise
ratio
“CCIR468-3”
(quasi-peak)
66
75
−
dB
αcr
crosstalk attenuation for
notes 1 and 3
VP = 8 V
DUAL
Zs ≤ 1 kΩ
70
75
−
dB
STEREO
Zs ≤ 1 kΩ
40
45
−
dB
αmute
mute attenuation
Zs ≤ 1 kΩ; note 1
76
80
−
dB
∆VDC
change of DC level output
voltage between any two
modes of operation
after switching
−
−
±10
mV
PSRR
power supply ripple rejection fr = 70 Hz; see Fig.6
50
65
−
dB
IO(DC)
DC output current
−
−
±20
µA
10 MHz crystal oscillator (pin 19)
fr
series resonant frequency of
crystal (fundamental mode)
CL = 20 pF
9.995
10.008
10.021
MHz
fω
working oscillator frequency
(running in parallel
resonance mode)
over operating
temperature range
including ageing and
influence of drive circuit
9.988
10.008
10.028
MHz
Rr
equivalent crystal series
resistance
even at extremely low
drive level (<1 pW) over
operating temperature
range with C0 = 6 pF
−
60
200
Ω
Rn
crystal series resistance of
unwanted mode
2 × Rr
−
−
Ω
C0
crystal parallel capacitance
−
6
10
pF
C1
crystal motional capacitance
−
25
50
fF
PXTAL
level of drive in operation
−
−
5
µW
VOSC(p-p)
oscillator operating voltage
(peak-to-peak value)
500
550
600
mV
1995 Mar 20
with Rr ≤100 Ω
9
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
SYMBOL
PARAMETER
TDA9845
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Pilot processing
5
−
100
mV
pilot input resistance
500
1000
−
kΩ
Ci pil
pilot input capacitance
−
−
3
pF
m
modulation depth
AM
25
50
75
%
∆fpil
pilot PLL pull-in frequency
range (referenced to
fpil = 54.6875 kHz)
fω = 9.988 MHz
lower side
−405
−
−405
Hz
upper side
192
−
192
Hz
lower side
−296
−
−296
Hz
upper side
302
−
302
Hz
lower side
−188
−
−188
Hz
upper side
411
−
411
Hz
0
−
1.7
ms
450
600
750
Hz
Vi pil(rms)
pilot input voltage level at
pin 6 (RMS value)
Ri pil
unmodulated
fω = 10.008 MHz
fω = 10.028 MHz
tpil
pilot PLL pull-in time
fLP
low-pass frequency
response
R4
low-pass output resistance
18.75
25
31.25
kΩ
V4(rms)
identification threshold
voltage (RMS value)
−
−
70
mV
QL
loaded quality factor of
resonance circuit
HIGH sensitivity;
see Fig.1
40
−
50
loaded quality factor of
resonance circuit with fixed
coil
sensitivity loss 2 to 3 dB;
see Fig.2
−
12
−
AGC acquisition time
Vi pil(rms) switched from
0 to 100 mV RMS value
−
−
0.1
s
tacqui AGC
−3 dB
Identification (internal functions)
Vi tuner
identification voltage
sensitivity
note 4
−
28
−
dBµV
C/N
pilot carrier-to-noise ratio for
start of identification
note 5
−
33
−
dB/Hz
H
hysteresis
note 4
−
−
2
dB
fdet
pull-in frequency range of
identification PLL
(referenced to
fdet STEREO = 117.48 Hz and
fdet DUAL = 274.12 Hz)
lower side
STEREO
−0.63
−
−0.63
Hz
DUAL
−0.69
−
−0.69
Hz
STEREO
0.63
−
0.63
Hz
DUAL
0.69
−
0.69
Hz
1995 Mar 20
upper side
10
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
SYMBOL
tdet
fident
PARAMETER
pull-in time of identification
PLL (referenced to
fdet STEREO = 117.48 Hz and
fdet DUAL = 274.12 Hz)
identification window
frequency width (referenced
to fdet STEREO = 117.48 Hz
and fdet DUAL = 274.12 Hz)
tintegr
integrator time constant
tident(on)
total identification time on
tident(off)
total identification time off
TDA9845
CONDITIONS
MIN.
TYP.
MAX.
UNIT
STEREO
0
−
0.8
s
DUAL
0
−
0.8
s
STEREO; note 6
2.2
−
2.2
Hz
DUAL; note 6
2.3
−
2.3
Hz
0.94
−
0.94
s
STEREO; note 7
0.35
−
2.0
s
DUAL; note 7
0.35
−
2.0
s
STEREO; note 8
0.60
−
1.5
s
DUAL; note 8
0.60
−
1.5
s
LED (pins 14 and 15)
VL(off)
output voltage
LED off
−
−
8.8
V
VL(on)
output voltage
LED on
−
−
0.7
V
IL(off)
input current
LED off
−
−
1
µA
IL(on)
input current
LED on
−
−
12
mA
Control input ports C1, C2 and C3 (pins 1, 2 and 20)
VCL
LOW level input voltage
0
−
0.8
V
VCH
HIGH level input voltage
2.4
−
8.8
V
ICL
LOW level input current
−
−
−1
µA
ICH
HIGH level input current
−
−
1
µA
Notes
1. Vo = 0.5 V RMS value; f = 1 kHz.
2. Without de-emphasis capacitors with respect to nominal gain.
3. In dual mode: A (B)-signal into B (A) channel.
In stereo mode: R-signal into left channel; L-signal = 0.
4. Tuner input signal, measured with PCALH reference front end (1⁄2EMF, 75 Ω, 2T/20T/white bar, 100% video) and
PC/SC1 = 13 dB; PC/SC2 = 20 dB. The pilot band-pass has to be aligned.
5. Bandwidth of the pilot BP-filter B−3 dB = 1.2 kHz. Vi 2 input driven with identification-modulated pilot carrier and white
noise.
6. Identification window is defined as twice the pull-in frequency range (lower plus upper side) of identification PLL
(steady detection) plus window increase due to integrator (fluctuating detection).
7. The maximum total system identification time ON is equal to tident(on) plus tacqui AGC.
8. The maximum total system identification time OFF is equal to tident(off).
1995 Mar 20
11
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
Table 1
TDA9845
Control input port matrix to select AF inputs and AF outputs
INPUT SIGNAL
INPUT/OUTPUT
ST/DS/M
MODE
OUTPUT SIGNAL
CONTROL INPUT
MAIN
PORT(1)
EXT
Vi 1
Vi 2
Vi 3
PIN 8 PIN 9 PIN 10
Vo 1
PIN 12
Vo 2
PIN 11
LED
C3
C2
C1
PIN 20 PIN 2 PIN 1
DUAL
PIN 14
STEREO
PIN 15
Mute; note 2
−
−
−
−
no signal
0
0
0
OFF
OFF
Sound mute
−
−
−
−
no signal
1
0
0
note 3
note 3
Mono
M
M
−
−
M
M
0
0
1
OFF
OFF
M
−
−
M
M
0
1
0
OFF
OFF
AM
−
−
AM
AM
0
1
1
OFF
OFF
S
R
−
L
R
0
0
1
OFF
ON
S
R
−
S
S
0
1
0
OFF
ON
S
R
−
S
S
0
1
1
OFF
ON
A
B
−
A
B
0
0
1
ON
OFF
A
B
−
A
A
0
1
0
ON
OFF
A
B
−
B
B
0
1
1
ON
OFF
−
−
C
C
C
1
0
1
note 3
note 3
−
−
C
C
C
1
1
0
OFF
OFF
Stereo
ST
Dual
DS
External; note 4
−
Notes
1. The combination 111 is not allowed.
2. In mute mode the content of the 117 Hz/274 Hz integrator will be reset. The LEDs are switched OFF.
3. The LED show the identification status.
4. In external mode, in the combination 110 only the LEDs are switched OFF.
Table 2
Explanation of Table 1
SIGNAL
DESCRIPTION
R
right
L
left
S
( L + R)
-------------------2
A and B
dual sound A/B
C
external sound source
AM
AM sound (standard L)
M
mono sound
DS
dual sound
ST
stereo sound
1995 Mar 20
12
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9845
MED647
+2
R: −15%;
C: −5%
VoAF
(dB)
+1
0
−1
R: +15%;
C: +5%
−2
10
Fig.4
1995 Mar 20
10 2
10 3
10 4
foAF (Hz)
Tolerance scheme of AF frequency response; de-emphasis with CD1, CD2 = 10 nF (±5%),
Rinternal = 5 kΩ (±15%).
13
10 5
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
handbook, full pagewidth
TDA9845
C1
1
20
C2
2
19
control input
ports
C3 control input port
XTAL
1/2 V P
C AGC
10 µF
C LP
10 nF
3
18
10 MHz
VP
CVP
10 µF
4
17
50 µs
de-emphasis
5%
C D2
10 nF
100 nF
C DCL
5
16
TDA9845
stereo transmission
15
7
14
8
13
1 kΩ
2.5
mH
3.3
nF
47 pF
6
dual transmission
30 kΩ
AF from 5.5 MHz
or from AM demodulator (L)
2.2 kΩ
Vi 1
AF from 5.742 MHz
Vi 2
from external sound source
Vi 3
2.2 kΩ
9
VP
5%
C D1
10 nF
12
Vo 1
11
Vo 2
50 µs
de-emphasis
main
10
3 x 2.2 µF
MED648 - 1
Fig.5 Test circuit of the stereo decoder TDA9845.
handbook, full pagewidth
VB
VP
12
18
measurements
on outputs
TDA9845
10 k Ω
11
8
7
100 µF
Vo 1
9
10
Vo 2
16
5 V modulated
with 200 mV (p-p)
70 Hz
100 µF/
16 V
100 µF
MED650 - 1
Fig.6 Test circuit for measurement of ripple rejection.
1995 Mar 20
14
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9845
INTERNAL CIRCUITRY
handbook, full pagewidth
VP
VP
3 µA
3 µA
C1
2 k Ω 20
2 kΩ
1
–
VP
13 k Ω
+5 V
5 kΩ
18
VP
2 kΩ
2
5 kΩ
+
D2
+
VP
VP
C
–
VP
CAGC
17
–
TDA9845
60 µA
25 kΩ
3
CLP
XTAL
3 pF
+
3 µA
C2
19
C3
16
GND
4
40 µA
25 kΩ
VP
15
VP
LEDST
60 µA
1/2 VP
5
CDCL
VP
25 kΩ
14
40 µA
6
7
5 kΩ
5 kΩ
22.5 kΩ
IB
D1
+
VP
IB
AF inputs
100 Ω
1/2 VP
12
9
50 k Ω
IB
AF outputs
1/2 VP
Vi 3
200 µA
100 Ω
IB
11
200 µA
1/2 VP
MED649 - 1
VP
ESD protection diode
for pins 3 to 13, 17 and 19
zener diode protection
for pins 1, 2, 14, 15, 18 and 20
Fig.7 Internal circuitry.
15
Vo 1
VP
10
50 k Ω
1995 Mar 20
C
8
50 k Ω
Vi 2
13
–
VP
Vi 1
5 kΩ
+
Cref
LEDDU
5 kΩ
–
Vi pil
5 kΩ
Vo 2
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9845
PACKAGE OUTLINES
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
ME
seating plane
D
A2
A
A1
L
c
e
Z
b1
w M
(e 1)
b
MH
11
20
pin 1 index
E
1
10
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
mm
4.2
0.51
3.2
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
inches
0.17
0.020
0.13
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
D
(1)
e
e1
L
ME
MH
w
Z (1)
max.
6.40
6.22
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
2.0
0.25
0.24
0.10
0.30
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.078
E
(1)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT146-1
1995 Mar 20
REFERENCES
IEC
JEDEC
EIAJ
SC603
16
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-05-24
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9845
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
HE
y
v M A
Z
11
20
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
10
e
bp
detail X
w M
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.30
0.10
2.45
2.25
0.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.9
0.4
0.012 0.096
0.004 0.089
0.01
0.019 0.013
0.014 0.009
0.51
0.49
0.30
0.29
0.050
0.42
0.39
0.055
0.043
0.016
0.043
0.039
0.01
0.01
0.004
0.035
0.016
inches
0.10
Z
(1)
θ
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT163-1
075E04
MS-013AC
1995 Mar 20
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-01-24
17
o
8
0o
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9845
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
SOLDERING
Plastic dual in-line packages
BY DIP OR WAVE
The maximum permissible temperature of the solder is
260 °C; this temperature must not be in contact with the
joint for more than 5 s. The total contact time of successive
solder waves must not exceed 5 s.
BY SOLDER PASTE REFLOW
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified storage maximum. If the printed-circuit board has
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within
the permissible limit.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron below the seating plane
(or not more than 2 mm above it). If its temperature is
below 300 °C, it must not be in contact for more than 10 s;
if between 300 and 400 °C, for not more than 5 s.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON 4OR PULSE-HEATED SOLDER TOOL)
Plastic small outline packages
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
BY WAVE
1995 Mar 20
18
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with digital identification
TDA9845
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1995 Mar 20
19
Philips Semiconductors – a worldwide company
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SCD39
© Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
Printed in The Netherlands
533061/50/02/pp20
Document order number:
Date of release: 1995 Mar 20
9397 750 00107