INTEGRATED CIRCUITS DATA SHEET TDA9840 TV and VTR stereo/dual sound processor with digital identification and I2C-bus control Product specification Supersedes data of 1995 Mar 21 File under Integrated Circuits, IC02 1998 Jul 03 Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control TDA9840 FEATURES • Supply voltage 5 to 8 V • De-emphasis • Source selector • Level and stereo matrix adjustment possible via the I2C-bus GENERAL DESCRIPTION • I2C-bus transceiver The TDA9840 is a stereo/dual sound processor for TV and VTR sets. Its identification ensures safe operation by using internal digital PLL technique with extremely small bandwidth, synchronous detection and digital integration (switching time maximum 2.3 s; identification concerning the main functions). • AF inputs for NICAM or AM sound (standard L) • AF outputs for Main and SCART • AF input and output signals selectable via the I2C-bus • Information for identified transmission mode is readable via I2C-bus • Software is compatible with the TDA8415/16/17 • Quartz oscillator and clock generator • Three digital PLL, alignment-free • Two digital integrators, alignment-free • Stabilizer circuit for ripple rejection and constant output signals • ESD protection of all pins. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION TDA9840 DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1 TDA9840T SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 1998 Jul 03 2 Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control TDA9840 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VP supply voltage (pin 18) 4.5 5 8.8 V IP supply current (pin 18) 15.5 16.5 20.5 mA Vi(rms) nominal input signal voltage (Vi 1, Vi 2, Vi 3) (RMS value) 54% modulation − 250 − mV Vo(rms) nominal output signal voltage (RMS value) THD ≤ 0.3% 54% modulation − 500 − mV Vo(rms) clipping level of the output signal voltages (RMS value) THD ≤ 1.5% 1.4 1.6 − V VP = 5 V VP = 8 V ∆Gv stereo control range for Vi 1 (0.1 dB steps) level control range for Vi 2 (0.5 dB steps) 2.4 2.65 − V +2.4 +2.5 +2.6 dB −2.3 −2.4 −2.5 dB +2.4 +2.5 +2.6 dB −1.9 −2.0 −2.1 dB Vi pil input voltage sensitivity of pilot frequency unmodulated 5 − 100 mV S/N(W) weighted signal-to-noise ratio “CCIR468-3” 66 75 − dB THD total harmonic distortion − 0.2 0.3 % Tamb operating ambient temperature range 0 − +70 °C fident identification window width STEREO 2.0 − 2.0 Hz DUAL 2.3 − 2.3 Hz STEREO 3.8 − 3.8 Hz DUAL 5.8 − 5.8 Hz STEREO 0.35 − 2.3 s DUAL 0.35 − 2.0 s STEREO 0.175 − 1.1 s DUAL 0.175 − 1.0 s − 28 − dBµV lower side −296 − −296 Hz upper side 302 − 302 Hz normal mode fast mode tident(on) total identification time ON normal mode fast mode Vi tuner identification voltage sensitivity ∆fpil pull-in frequency range of pilot PLL 1998 Jul 03 fω = 10.008 MHz 3 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 10 k Ω 250 mV RMS (from 1st SC) 10 nF 2.2 µF ±5% 15 17 0 to 4.5 dB L/A/MONO 250 mV RMS 0 to −0.4 dB A/MONO 40 kΩ Vi 2 10 k Ω 2.2 µF 5 kΩ stereo Vo 1 500 mV RMS 13 Vo 2 500 mV RMS 12 Vo 3 500 mV RMS 11 Vo 4 MAIN 6 dB R/B 250 mV RMS SCART 6 dB level 14 25 k Ω 0 to 4.5 dB 30 kΩ 500 mV RMS 25 k Ω 10 k Ω −2 dB 8 R, B 10 k Ω 6 dB 6 dB L 250 mV RMS (from 2nd SC) 10 25 k Ω 25 k Ω 5 kΩ 40 kΩ 2.2 µF 9 TDA9840 mute 4 LEVEL AND STEREO ADJUSTMENT DIGITAL PLL AND DEMODULATOR 47 pF DIGITAL INTEGRATOR DUAL bit I 2 C-BUS V i pil 3.3 nF tanδ ≤ 0.002 CDCL CONTROL 5 DIGITAL PLL 2.5 mH Q0 = 70 4 DIGITAL PLL AND DEMODULATOR DIGITAL INTEGRATOR 20 SCL 1 SDA Philips Semiconductors −2 dB 7 500 mV RMS CD2 TV and VTR stereo/dual sound processor with digital identification and I2C-bus control 2.2 µF Vi 1 BLOCK DIAGRAMS andbook, full pagewidth 1998 Jul 03 10 nF ±5% L+R , A 2 Vi 3 Vi 4 CD1 STEREO bit 25 k Ω 100 nF 2 CAGC 25 k Ω OSCILLATOR GENERATION OF REFERENCE VOLTAGES Vref 10 µF POWER-ON RESET CONTROL LOGIC 3 CLP 1/2 VP 16 GND Cref 100 µF / 16 V VP Fig.1 Block diagram of the bipolar TV/VTR-stereo decoder. MBE457 TDA9840 10 MHz 18 Product specification XTAL Input and output levels are nominal values. They are related to the SCART norm. (AM: m = 0.54, FM: ∆f = ±27 kHz). 6 19 10 nF This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Vi 1 −2 dB 7 10 k Ω 250 mV RMS (from 1st SC) 10 nF ±5% 15 17 0 to 4.5 dB L/A/MONO 250 mV RMS 0 to −0.4 dB A/MONO 40 kΩ Vi 2 10 k Ω 10 k Ω R, B 2.2 µF 5 kΩ 25 k Ω 25 k Ω 6 dB stereo Vo 1 500 mV RMS 13 Vo 2 500 mV RMS 12 Vo 3 500 mV RMS 11 Vo 4 MAIN 6 dB R/B 250 mV RMS SCART 6 dB level 14 25 k Ω 0 to 4.5 dB 27 k Ω 500 mV RMS 25 k Ω 10 k Ω −2 dB 8 10 6 dB L 250 mV RMS (from 2nd SC) 9 5 kΩ 40 kΩ 2.2 µF 2.2 µF TDA9840 mute 5 LEVEL AND STEREO ADJUSTMENT DIGITAL PLL AND DEMODULATOR 180 pF DIGITAL INTEGRATOR DUAL bit I 2 C-BUS V i pil 1.8 nF ±2% tanδ ≤ 0.01 CDCL CAGC 4.7 mH ±5% Q0 = 25 CONTROL 5 DIGITAL PLL 4 DIGITAL PLL AND DEMODULATOR DIGITAL INTEGRATOR 20 SCL 1 SDA Philips Semiconductors 2.2 µF 10 nF ±5% 500 mV RMS CD2 TV and VTR stereo/dual sound processor with digital identification and I2C-bus control ok, full pagewidth 1998 Jul 03 L+R , A 2 Vi 3 Vi 4 CD1 STEREO bit 25 k Ω 100 nF 25 k Ω 2 OSCILLATOR GENERATION OF REFERENCE VOLTAGES Vref 10 µF POWER-ON RESET CONTROL LOGIC 3 CLP 6 19 10 nF XTAL VP MBE458 The components of the external LC band-pass filter have the following order-No.: Philips Germany only No: 4312 020 17525 or Fastron Sdn. Bha., Malaysia type SMCC 472 J for L = 4.7 mHz (±5%) Philips Components No: 2222 429 71802, C = 1.8 nF (±2%). Fig.2 Block diagram of the bipolar TV/VTR-stereo decoder with fixed coil (alignment-free). Product specification Input and output levels are nominal values. They are related to the SCART norm. (AM: m = 0.54, FM: ∆f = ±27 kHz). GND Cref 100 µF / 16 V 16 TDA9840 10 MHz 18 1/2 VP Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control TDA9840 PINNING SYMBOL PIN DESCRIPTION SDA 1 I2C-bus CAGC 2 AGC capacitor of pilot frequency amplifier CLP 3 identification low-pass capacitor CDCL 4 DC loop capacitor Vi pil 5 pilot frequency input voltage data input/output (1⁄ fpage 2VP) SDA 1 20 SCL CAGC 2 19 XTAL CLP 3 18 V P 17 CD2 Cref 6 capacitor of reference voltage Vi 1 7 AF input signal Vi 1 (from 1st sound carrier) CDCL 4 Vi 2 8 AF input signal Vi 2 (from 2nd sound carrier) V i pil 5 Vi 3 9 AF input signal Vi 3 (NICAM or AM sound (standard L)) Vi 4 10 AF input signal Vi 4 (NICAM) Vo 4 11 AF output signal Vo 4 (SCART) Vo 3 12 AF output signal Vo 3 (SCART) Vo 2 13 Vo 1 16 GND TDA9840 Cref 6 15 CD1 Vi 1 7 14 Vo 1 Vi 2 8 13 Vo 2 AF output signal Vo 2 (main) Vi 3 9 12 Vo 3 14 AF output signal Vo 1 (main) Vi 4 10 11 Vo 4 CD1 15 50 µs de-emphasis capacitor of AF Channel 1 GND 16 ground (0 V) CD2 17 50 µs de-emphasis capacitor of AF Channel 2 VP 18 supply voltage (+5 to +8 V) XTAL 19 10 MHz crystal input SCL 20 I2C-bus clock input 1998 Jul 03 MBE459 Fig.3 Pin configuration. 6 Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control are fed to the AM-synchronous demodulator. The demodulator detects the identification signal, which is fed through a low-pass filter with external capacitor CLP (pin 3) to a Schmitt-trigger for pulse shaping and suppression of low level spurious signal components. This is a measure against mis-identification. FUNCTIONAL DESCRIPTION The TDA9840 (see Fig.1) receives the signals from the FM-demodulators in a TV two sound-carrier system. The circuit is realized by the H00485 bipolar process. The IC is intended for use in economic TV and VTR receivers. Therefore optimum relationship between integration of functions and use of external components has been striven for. Additionally a new type of identification circuit has been developed. The identification signal is amplified and fed through an AGC low-pass filter with external capacitor CAGC (pin 2) to obtain the AGC voltage for controlling the gain of the pilot signal amplifier. The identification stages consist of two digital PLL circuits with digital synchronous demodulation and digital integrators to generate the stereo or dual sound identification bits which can be read out via the I2C-bus. AF signal handling The input AF signals, derived from the two sound carriers, are processed in analog form using operational amplifiers.The circuit incorporates level- and stereo-adjustment to correct the spreading in the FM detector output levels. Dematrixing uses the technique of two amplifiers processing the AF signals. Finally, a source selector provides the facility to route the mono signal through to the outputs (‘forced mono’). A 10 MHz quartz crystal oscillator provides the reference clock frequency. The corresponding detection bandwidth is larger than ±50 Hz for the pilot carrier signal, so that fp-variations from the transmitter can be tracked in case of missing synchronisation with the horizontal frequency fH. However the detection bandwidth for the identification signal is made small (approximately ±1 Hz) to reduce mis-identification. De-emphasis is performed by two RC low-pass filter networks with internal resistors and external capacitors. This provides a frequency response with the tolerances given in Fig.4. Figure 2 shows an example of the alignment-free fp band-pass filter. To achieve the required QL of approximately 12, the Q0 at fp of the coil was chosen to be approximately 25 (effective Q0 including PCB influence). Using coils with other Q0, the RC-network (RFP, CFP) has to be adapted accordingly. It is assumed that the loss factor tanδ of the resonance capacitor is ≤0.01 at fp. A source selector, controlled via the I2C-bus, allows selection of the different modes of operation in accordance with the transmitted signal. The device was designed for a nominal input signal (FM: 54% modulation is equivalent to ∆f = ±27 kHz / AM: m = 0.54) of 250 mV RMS (Vi 1, Vi 2), respectively 500 mV RMS (Vi 3,Vi 4). A nominal gain of 6 dB for Vi 1 and Vi 2 signals and 0 dB for Vi 3 and Vi 4 signals is built-in. By using rail-to-rail operational amplifiers, the clipping level (THD ≤1.5%) is 1.6 V RMS for VP = 5 V and 2.65 V RMS for VP = 8 V at outputs Vo 1, Vo 2,Vo 3 and Vo 4. Care has been taken to minimize switching plops. Also total harmonic distortion and random noise are considerably reduced. Copper areas under the coil might influence the loaded Q and have to be taken into account. Care has also to be taken in environments with strong magnetic fields when using coils without magnetic shielding. I2C-bus transceiver The complete IC is controlled by a microcomputer via the I2C-bus. The built-in I2C-bus transceiver transmits the identification result to the I2C-bus and receives the control data for the source selector and level control. The I2C-bus protocol is given in Tables 2 to 12 respectively. Identification The pilot signal is fed via an external RC high-pass filter and single tuned LC band-pass filter to the input of a gain controlled amplifier. The external LC band-pass filter in combination with the external RC high-pass filter should have a loaded Q-factor of about 40 to 50 to ensure the highest identification sensitivity. By using a fixed coil (±5%) to save the alignment (see Fig.2), a Q-factor of about 12 is proposed. This may cause a loss in sensitivity of about 2 to 3 dB. A digital PLL circuit generates a reference carrier, which is synchronized with the pilot carrier. This reference carrier and the gain controlled pilot signal 1998 Jul 03 TDA9840 The data transmission between the microcontroller and the other I2C-bus controlled ICs is not disturbed, when the supply voltage of the TDA9840 is not connected or when powering up or down. Finally, a Schmitt-trigger is built-in the SDA/SCL interface to suppress spikes from the I2C-bus. 7 Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control TDA9840 Power supply Fast mode / test mode The different supply voltages and currents required for the analog and digital circuits are derived from an internal band-gap reference circuit. The AF reference voltage is 1⁄ V . For a fast setting to 1⁄ V an internal start-up circuit 2 P 2 P is added. A good ripple rejection is achieved with the external capacitor Cref = 100 µF/16 V in conjunction with the high ohmic input of the 1⁄2VP pin (pin 6). Additional DC-load on this pin is prohibited. The TDA9840 has a fast mode (test mode) to reduce the integration time of the 117/274 Hz integrator from approximately 1 to 0.5 s. ESD protection All pins are ESD protected. The protection circuits represent the latest state of the art. Internal circuit Power-on reset The internal pin loading diagram is given in Fig.7. When a power-on reset is activated by switching on the supply voltage or because of a supply voltage breakdown, the 117/274 Hz DPLL, the 117/274 Hz integrator and the registers will be reset. Both AF channels (Main and SCART) are muted. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VP supply voltage (pin 18) −0.3 10 V Vi voltage at pins 1 and 20 −0.3 5.5 V Vi voltage at pins 2 to 15, 17 and 19 −0.3 VP V Tstg storage temperature −25 +150 °C Tamb operating ambient temperature 0 +70 °C Vesd electrostatic handling for all pins − ±300 V note 1 Note 1. Charge device model class B: discharging a 200 pF capacitor through a 0 Ω series resistor. THERMAL CHARACTERISTICS SYMBOL Rth j-a 1998 Jul 03 PARAMETER VALUE UNIT DIP20 73 K/W SO20 90 K/W thermal resistance from junction to ambient in free air 8 Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control TDA9840 CHARACTERISTICS VP = 5 V; Tamb = +25 °C; nominal input signal Vi 1, 2 = 0.25 V RMS value (FM: 54% modulation is equivalent to ∆f = ±27 kHz); nominal input signal Vi 3, 4 = 0.5 V RMS value (AM: m = 0.54); nominal output signal Vo 1, 2, 3, 4 = 0.5 V RMS value; fAF = 1 kHz; Vi pil = 16 mV RMS value; fpil = 54.6875 kHz (identification frequencies: stereo = 117.48 Hz, dual = 274.12 Hz), 50 µs pre-emphasis; noise measurement in accordance with “CCIR468-3”, working oscillator frequency fω = 10.008 MHz; currents into the IC positive; measured in test circuit according to Fig.5; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VP supply voltage (pin 18) IP supply current (pin 18) 15.5 16.5 20.5 mA Ptot total power dissipation 69.75 82.5 180.4 mW Vn(DC) DC voltage (pins 7 to 15 and 17) 1⁄ 2VP − 0.1 1⁄ 2VP 1⁄ 2VP + 0.1 V Vref(DC) DC reference voltage (pin 6) 1⁄ 2VP − 0.1 1⁄ 2VP 1⁄ 2VP + 0.1 V lL(DC) DC leakage current (pin 6) − − ±1 µA − 0.25 − V VP = 5 V 0.625 0.715 − V VP = 8 V 1.050 1.200 − V VP = 5 V 0.780 0.900 − V VP = 8 V 1.300 1.500 − V G = Vo/Vi; note 3 5 6 7 dB only at pin 7 +2.4 +2.5 +2.6 dB −2.3 −2.4 −2.5 dB maximum 49 steps − 0.1 − dB only at pin 8 +2.4 +2.5 +2.6 dB −1.9 −2.0 −2.1 dB 4.5 5 8.8 V AF Inputs; Vi 1 and Vi 2 (pins 7 and 8) Vi(rms) nominal input signal voltage (RMS value) 54% modulation Vi(rms) clipping voltage level (RMS value) THD ≤ 1.5%; note 1 THD ≤ 1.5%; note 2 Gv AF signal voltage gain ∆Gv (Vo1) stereo control range nominal step ∆Gv (Vo2) level control range nominal step Ri input resistance Rdeem internal de-emphasis resistor (pins 15 and 17) − 0.5 − dB 40 50 60 kΩ see Fig.4 4.25 5.0 5.75 kΩ − 0.5 − V maximum 9 steps Additional AF input pin (pins 9 and 10) Vi(rms) nominal input signal voltage (RMS value) 54% modulation Vi(rms) clipping voltage level (RMS value) THD ≤ 1.5% Gv AF signal voltage gain Ri input resistance 1998 Jul 03 VP = 5 V 1.25 1.40 − V VP = 8 V 2.10 2.35 − V −1 0 1 dB 40 50 60 kΩ G = Vo/Vi; note 3 9 Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control SYMBOL PARAMETER TDA9840 CONDITIONS MIN. TYP. MAX. UNIT AF outputs (pins 11 to 14) Vo(rms) nominal output signal voltage (RMS value) THD ≤ 0.3%; 54% modulation − 0.5 − V Vo(rms) clipping voltage level (RMS value) THD ≤ 1.5% VP = 5 V 1.4 1.6 − V VP = 8 V 2.4 2.65 − V Ro output resistance 150 250 350 Ω CL load capacitor on output − − 1.5 nF RL load resistor on output (AC-coupled) 10 − − kΩ B frequency response (bandwidth) fi = 40 to 20000 Hz; note 4 −0.5 − +0.5 dB B−3 dB frequency response −3 dB; note 4 300 350 400 kHz THD total harmonic distortion note 3 − 0.2 0.3 % S/N(W) weighted signal-to-noise ratio “CCIR468-3” (quasi-peak) 66 75 − dB αcr crosstalk attenuation for notes 3 and 5 DUAL Zs ≤ 1 kΩ 70 75 − dB STEREO Zs ≤ 1 kΩ 40 45 − dB αmute mute attenuation Zs ≤ 1 kΩ; note 3 76 80 − dB ∆VDC change of DC level output voltage between any two modes of operation after switching − − ±10 mV PSRR power supply ripple rejection fr = 70 Hz; see Fig.6 50 65 − dB IO(DC) DC output current − − ±20 µA note 6 − 90 80 dB αI2C noise from I2C-bus 10 MHz crystal oscillator (pin 19) fr series resonant frequency of crystal (fundamental mode) CL = 20 pF 9.995 10.008 10.021 MHz fω working oscillator frequency (running in parallel resonance mode) over operating temperature range including ageing and influence of drive circuit 9.988 10.008 10.028 MHz Rr equivalent crystal series resistance even at extremely low drive level (<1 pW) over operating temperature range with C0 = 6 pF − 60 200 Ω Rn crystal series resistance of unwanted mode 2 × Rr − − Ω C0 crystal parallel capacitance − 6 10 pF C1 crystal motional capacitance − 25 50 fF 1998 Jul 03 with Rr ≤ 100 Ω 10 Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control SYMBOL PARAMETER TDA9840 CONDITIONS MIN. TYP. MAX. UNIT PXTAL level of drive in operation − − 5 µW VOSC(p-p) oscillator operating voltage (peak-to-peak value) 500 550 600 mV − 100 mV Pilot processing Vi pil(rms) pilot input voltage level at pin 5 unmodulated (RMS value) 5 500 1000 − kΩ 25 50 75 % lower side −405 − −405 Hz upper side 192 − 192 Hz lower side −296 − −296 Hz upper side 302 − 302 Hz lower side −188 − −188 Hz upper side 411 − 411 Hz 0 − 1.7 ms 450 600 750 Hz Ri pil pilot input resistance m modulation depth AM ∆fpil pilot PLL pull-in frequency range (referred to fpil = 54.6875 kHz) fω = 9.988 MHz fω = 10.008 MHz fω = 10.028 MHz tpil pilot PLL pull-in time fLP low-pass frequency response −3 dB R3 low-pass output resistance 18.75 25 31.25 kΩ V4(rms) identification threshold voltage (RMS value) − − 70 mV QL loaded quality factor of resonance circuit high sensitivity 40 − 50 loaded quality factor of resonance circuit with fixed coil sensitivity loss 2 to 3 dB; see Fig.2 − 12 − AGC acquisition time Vi pil(rms) switched from 0 to 100 mV RMS value − − 0.1 s tacqui AGC Identification (internal functions) Vi tuner identification voltage sensitivity note 7 (pin 5) − 28 − dBµV C/N pilot carrier-to-noise ratio for start of identification note 8 − 33 − dB/Hz H hysteresis note 7 − − 2 dB 1998 Jul 03 11 Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control SYMBOL fdet PARAMETER pull-in frequency range of identification PLL (referred to fdet STEREO = 117.48 Hz and fdet DUAL = 274.12 Hz) TDA9840 CONDITIONS MIN. TYP. MAX. UNIT normal mode lower side STEREO −0.38 − −0.38 Hz DUAL −0.69 − −0.69 Hz STEREO 0.69 − 0.69 Hz DUAL 0.69 − 0.69 Hz STEREO −0.89 − −0.89 Hz DUAL −2.05 − −2.05 Hz STEREO 1.15 − 1.15 Hz DUAL 2.05 − 2.05 Hz STEREO 0 − 1.35 s DUAL 0 − 0.72 s STEREO 0 − 0.57 s DUAL 0 − 0.25 s STEREO 2.0 − 2.0 Hz DUAL 2.3 − 2.3 Hz 3.8 − 3.8 Hz normal mode upper side fast mode lower side fast mode upper side tdet fident pull-in time of identification PLL (referred to fdet STEREO = 117.48 Hz and fdet DUAL = 274.12 Hz) identification window frequency width (referred to fdet STEREO = 117.48 Hz and fdet DUAL = 274.12 Hz) normal mode fast mode normal mode; note 9 fast mode; note 9 STEREO 5.8 − 5.8 Hz normal mode 0.94 − 0.94 s fast mode 0.47 − 0.47 s STEREO 0.35 − 2.3 s DUAL 0.35 − 2.0 s STEREO 0.175 − 1.1 s DUAL 0.175 − 1.0 s STEREO 0.6 − 1.6 s DUAL 0.6 − 1.6 s STEREO 0.3 − 0.8 s DUAL 0.3 − 0.8 s DUAL tintegr tident(on) integrator time constant total identification time on normal mode; note 10 fast mode; note 10 tident(off) total identification time off normal mode; note 11 fast mode; note 11 1998 Jul 03 12 Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control SYMBOL PARAMETER TDA9840 CONDITIONS MIN. TYP. MAX. UNIT I2C-bus transceiver (pins 1 and 20) fCI clock frequency 0 − 100 kHz I2C-bus: SCL (pin 20) VIL LOW level input voltage −0.3 − 1.5 V VIH HIGH level input voltage 3.0 − 5.5 V tlow timing LOW period 4.7 − − µs thigh timing HIGH period 4.0 − − µs tr rise time − − 1 µs tf fall time − − 0.3 µs IIL LOW level input current − − −10 µA IIH HIGH level input current − − 10 µA V I2C-bus: SDA (pin 1) VIL LOW level input voltage −0.3 − 1.5 VIH HIGH level input voltage 3.0 − 5.5 V tr rise time − − 1 µs tf fall time − − 0.3 µs tsu data set-up time 0.25 − − µs IIL LOW level input current − − −10 µA IOL LOW level output current −3 − − mA IIH HIGH level input current − − 10 µA Notes 1. Input control amplifiers with ∆Gv = 0 dB. 2. Input control amplifiers with ∆Gv = −2 dB. 3. Vo = 0.5 V RMS value; f = 1 kHz; input control amplifiers with ∆Gv = 0 dB. 4. Without de-emphasis capacitors with respect to nominal gain. 5. In dual mode: A (B)-signal into B (A) channel. In stereo mode: R-signal into left channel; L-signal = 0. 6. Test procedure tbf (same as TDA9855). 7. Tuner input signal, measured with PCALH reference front end (1⁄2EMF, 75 Ω, 2T/20T/white bar, 100% video) and PC/SC1 = 13 dB; PC/SC2 = 20 dB. The pilot band-pass has to be aligned. 8. Bandwidth of the pilot BP-filter B−3 dB = 1.2 kHz. Vi 2 input driven with identification-modulated pilot carrier and white noise. 9. Identification window is defined as total pull-in frequency range (lower plus upper side) of identification PLL (steady detection) plus window increase due to integrator (fluctuating detection). 10. The maximum total system identification time ON is equal to tident(on) plus tacqui AGC plus tI2C read-out. 11. The maximum total system identification time OFF is equal to tident(off) plus tI2C read-out. 1998 Jul 03 13 Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control TDA9840 I2C-BUS PROTOCOL FOR THE TV AND VTR STEREO/DUAL SOUND PROCESSOR TDA9840 HIGH. After a successful reading of the status register, the bit D7 will be reset to LOW. The TDA9840 has an I2C-bus interface with five registers: status, test, switch, level and stereo adjustment register controlled by a microcontroller via I2C-bus. The status register can be read and the other registers are write registers. The status byte represents the transmitter status detected by the identification circuit and the power-on reset status. The switch register controls the source selectors of the AF signal part, and the level and stereo adjustment register set the input level and stereo adjustment stage. Additionally, a test register is built-in to reduce the detection time of the identification circuit (test mode, fast mode respectively). The bits D5 and D6 represent the transmitter status detected by the identification circuit (stereo, dual or mono transmission). The other bits are set to 0 (default). Data format for the receiver Table 1 REGISTER I2C-bus transceiver and data-handling (bus specification) The TDA9840 is controlled by a microcomputer via the bidirectional 2-line I2C-bus. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. VALUE Switch register (00)HEX Port register (01)HEX (without function) Level adjustment register (02)HEX Stereo adjustment register (03)HEX Test register (04)HEX The port register is without function, because this IC has no control ports as TDA8415/6/7. A data byte for the subaddress (01)HEX will not be stored in any register. An acknowledge will be sent to the microcontroller. The first byte of the data transmission is the slave address and the second byte is the subaddress indicating the data register in which the data shall be stored. Starting from subaddress (00)HEX the n-th data byte will automatically be stored under subaddress n − 1. When the bus is free, both lines are HIGH. The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change, when the clock signal on the SCL line is LOW. The set-up and hold times are specified in the Chapter “Characteristics”. All 8 bits of the subaddress are decoded by the device. The subaddresses from (04)HEX to (FF)HEX are forbidden for the user. If the I2C-bus transceiver receives subaddresses from (05)HEX to (FF)HEX, no acknowledge will be sent back to the microcontroller. A HIGH-to-LOW transition of the SDA line, while SCL is HIGH, is defined as the start condition. A LOW-to-HIGH transition of the SDA line, while SCL is HIGH, is defined as the stop condition. The bus transceiver will be reset on the reception of a start condition. The bus is considered to be busy after the start condition. The bus is considered to be free again after a stop condition. Switch register The source selector is controlled by the switch register. Table 7 shows the modes of operation. Note, that in the event of the external operation mode, no further selection is possible. Data format transmitter mode For the data transmission no subaddress is to be transmitted, because there is only one read register implemented. So the total number of bytes reduces from three to two. The second byte represents the status of the IC. Status register (see Table 4) The bit D7 (PONRES) represents the status of the IC and indicates whether the power-on reset was activated by switching-on the supply voltage or a supply voltage breakdown. If so, the I2C-bus transceiver, the digital PLLs and integrators are initialized and the PONRES bit is set to 1998 Jul 03 Registers for receiver mode (see Table 6) 14 Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control TDA9840 Level adjustment register Level and stereo adjustment The information about the level adjustment of the AF channel Vi 2 (pin 8) is stored in the level adjustment register (see Table 10). There are 10 steps (positions) of the AF level adjustment stage. The level range is from 2.5 dB up to −2.0 dB in 0.5 dB steps. For the level and stereo adjustment of both AF channels Vi 1 and Vi 2, the following procedure will be recommended. After a power-on reset, the data byte of the level adjustment register will be set to (00)HEX: 0 dB gain at the AF input Vi 2. • Sets the data byte of the switch register (dual mode) to (1A)HEX Stereo adjustment register • Adjusts the output level with the level adjustment register. Level adjustment of the AF channel V • Feeds AF signal at the input Vi 2 • Measures the signal at the outputs Vo 2 or Vo 4 The information about the stereo adjustment of the AF channel Vi 1 (pin 7) is stored in the stereo adjustment register (see Table 11). There are 50 steps (positions) of the AF stereo adjustment stage. The stereo range is from 2.5 dB up to −2.4 dB in 0.1 dB steps. Stereo adjustment of the AF channel Vi 1 • Feeds AF stereo signals at the inputs Vi 1 ((L+R)/2) and Vi 2 (R) • Sets the data byte of the switch register (stereo mode) to (2A)HEX After a power-on reset, the data byte of the stereo adjustment register will be set to (00)HEX: 0 dB gain at the AF input Vi 1. • Measures the crosstalk attenuation between Vo 1 and Vo 2 or Vo 3 and Vo 4 Test register (also used for fast mode) • Adjusts the crosstalk attenuation with the stereo adjustment register. Table 12 shows the meaning of the test register. The integration time of the integrator is approximately 1 s (normal mode, default). If the data byte of this register is set to HIGH, the integration time is reduced from approximately 1 to approximately 0.5 s (fast mode, test mode). The pull-in ranges of the identification PLLs are changed to: During the stereo adjustment the data byte of the level adjustment register does not change. After the level and stereo adjustment, the bytes of the level and stereo adjustment register must be stored by the microcontroller in a memory. (To avoid mis-adjustment it would be wise to compare the stored bytes with the proper adjustment bytes). If the PONRES bit of the status register will be set to HIGH (see status register) the data bytes for these both registers must be sent out of the memory to the TDA9840 via I2C-bus. Also the data byte of the switch register (see Table 7) must be changed, because the AF outputs are muted. Stereo: −0.89/+1.15 Hz Dual: ±2.05 Hz. If the integration time of the integrator is switched from one mode to the other (i.e. from fast mode/test mode to normal mode), the status register bits D5 and D6 might set to zero internally (MONO). Therefore, the previous status register information has to be stored by the microcontroller until the transmitter status is detected again by the identification circuit (now in the new mode) the first time. The data byte of the test register can be reset in two different ways to (00)HEX: integration time approximately 1 s, normal mode: • after a power-on reset, for instance by switching the power supply Vp off and on again • data transmission via I2C-bus for the test register (see Table 12). 1998 Jul 03 15 Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control TDA9840 I2C-BUS FORMAT X is the read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read (the circuit is slave transmitter). If more than 1 byte of DATA is transmitted, then auto-increment of the significant subaddress is performed. Table 2 S I2C-bus; SLAVE ADDRESS/SUBADDRESS/DATA format SLAVE ADDRESS Table 3 A SUBADDRESS A DATA P Explanation of Table 2 BIT S FUNCTION start condition SLAVE ADDRESS 1000 010X A acknowledge, generated by the slave SUBADDRESS dual sound A/B DATA data byte; see Table 6 P stop condition Table 4 I2C-bus; SLAVE ADDRESS/DATA to read the status byte (X = 1 in the address byte) FUNCTION Status byte Table 5 DATA SLAVE ADDRESS D7 D6 D5 D4 D3 D2 D1 D0 1000 0101 PONRES ST DS 0 0 0 0 0 Explanation of Table 4 BIT FUNCTION PONRES = 0 after a successful reading of the status register PONRES = 1 after power-on reset or after supply breakdown ST = 0; DS = 0 MONO sound identified ST = 0; DS = 1 DUAL sound identified ST = 1; DS = 0 STEREO sound identified ST = 1; DS = 1 incorrect identification 1998 Jul 03 16 Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control Table 6 TDA9840 I2C-bus; SUBADDRESS/DATA for writing (X = 0 in the address byte) DATA FUNCTION SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 Switching 0000 0000 0 SW6 SW5 SW4 SW3 SW2 SW1 SW0 Without function (note 1) 0000 0001 0 0 0 0 0 0 0 0 Level adjustment 0000 0010 0 0 0 0 LV3 LV2 LV1 LV0 Stereo adjustment 0000 0011 0 0 ST5 ST4 ST3 ST2 ST1 ST0 Note 1. This byte is acknowledged by the TDA9840. Function of the bits: • SW6 to SW0 input and output AF selection; see Table 7 • LV3 to LV0 level adjustment; see Table 10 • ST5 to ST0 stereo adjustment; see Table 11. Table 7 Data byte to select AF inputs and AF outputs [subaddress (00)HEX] INPUT SIGNAL OUTPUT SIGNAL DATA TRANSMISSION MODE ST/DS/M EXT MAIN V i 1 Vi 2 Vi 3 Vi 4 Vo 1 Vo 2 Vo 3 Vo 4 PIN PIN PIN PIN PIN PIN PIN PIN 7 8 9 10 14 13 12 11 Sound mute − − − − − MONO M M − − − M STEREO ST DUAL DS − External Table 8 SCART no signal M M M D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 0 0 0 0 0 0 0 00 0 0 0 1 0 0 0 0 10 S R − − S S S S 0 0 0 1 0 0 0 0 10 S R − − L R L R 0 0 1 0 1 0 1 0 2A A B − − A B A A 0 0 0 1 0 0 1 0 12 A B − − A B A B 0 0 0 1 1 0 1 0 1A A B − − A B B A 0 0 0 1 0 1 1 0 16 A B − − A B B B 0 0 0 1 1 1 1 0 1E − − C D C D C D 0 1 1 1 1 0 1 0 7A Explanation of Table 7 SIGNAL DESCRIPTION SIGNAL DESCRIPTION R right C NICAM or AM sound (standard L) L left D NICAM S ( L + R) -------------------2 M mono sound DS dual sound dual sound A/B ST stereo sound A and B 1998 Jul 03 17 Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control Table 9 TDA9840 AF switch configuration INPUT OUTPUT TRANSMITTER STATUS SIGNAL MONO MAIN SCART M M M STEREO DUAL External M M L L or M L or M R R or M R or M A A A or B B B A or B C C C D D D Table 10 Data byte to select level adjustment [subaddress (02)HEX] ∆GV (dB) DATA D7 D6 D5 D4 D3 D2 D1 D0 HEX +2.5 0 0 0 0 1 1 0 1 0D +2.0 0 0 0 0 1 1 0 0 0C +1.5 0 0 0 0 1 0 1 1 0B +1.0 0 0 0 0 1 0 1 0 0A +0.5 0 0 0 0 1 0 0 1 09 0 0 0 0 0 0 0 0 0 00 −0.5 0 0 0 0 0 0 0 1 01 −1.0 0 0 0 0 0 0 1 0 02 −1.5 0 0 0 0 0 0 1 1 03 −2.0 0 0 0 0 0 1 0 0 04 1998 Jul 03 18 Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control TDA9840 Table 11 Data byte to select stereo adjustment [subaddress (03)HEX] DATA ∆GV (dB) D7 D6 D5 D4 D3 D2 D1 D0 HEX +2.5 0 0 1 1 1 0 0 1 39 +2.4 0 0 1 1 1 0 0 0 38 +2.3 0 0 1 1 0 1 1 1 37 +2.2 0 0 1 1 0 1 1 0 36 +2.1 0 0 1 1 0 1 0 1 35 +2.0 0 0 1 1 0 1 0 0 +1.9 0 0 1 1 0 0 1 1 +1.8 0 0 1 1 0 0 1 +1.7 0 0 1 1 0 0 +1.6 0 0 1 1 0 0 +1.5 0 0 1 0 1 +1.4 0 0 1 0 +1.3 0 0 1 0 +1.2 0 0 1 +1.1 0 0 +1.0 0 +0.9 0 +0.8 ∆GV (dB) DATA D7 D6 D5 D4 D3 D2 D1 D0 HEX 0 0 0 0 0 0 0 0 0 00 −0.1 0 0 0 0 0 0 0 1 01 −0.2 0 0 0 0 0 0 1 0 02 −0.3 0 0 0 0 0 0 1 1 03 −0.4 0 0 0 0 0 1 0 0 04 34 −0.5 0 0 0 0 0 1 0 1 05 33 −0.6 0 0 0 0 0 1 1 0 06 0 32 −0.7 0 0 0 0 0 1 1 1 07 0 1 31 −0.8 0 0 0 0 1 0 0 0 08 0 0 30 −0.9 0 0 0 0 1 0 0 1 09 1 1 1 2F −1.0 0 0 0 0 1 0 1 0 0A 1 1 1 0 2E −1.1 0 0 0 0 1 0 1 1 0B 1 1 0 1 2D −1.2 0 0 0 0 1 1 0 0 0C 0 1 1 0 0 2C −1.3 0 0 0 0 1 1 0 1 0D 1 0 1 0 1 1 2B −1.4 0 0 0 0 1 1 1 0 0E 0 1 0 1 0 1 0 2A −1.5 0 0 0 0 1 1 1 1 0F 0 1 0 1 0 0 1 29 −1.6 0 0 0 1 0 0 0 0 10 0 0 1 0 1 0 0 0 28 −1.7 0 0 0 1 0 0 0 1 11 +0.7 0 0 1 0 0 1 1 1 27 −1.8 0 0 0 1 0 0 1 0 12 +0.6 0 0 1 0 0 1 1 0 26 −1.9 0 0 0 1 0 0 1 1 13 +0.5 0 0 1 0 0 1 0 1 25 −2.0 0 0 0 1 0 1 0 0 14 +0.4 0 0 1 0 0 1 0 0 24 −2.1 0 0 0 1 0 1 0 1 15 +0.3 0 0 1 0 0 0 1 1 23 −2.2 0 0 0 1 0 1 1 0 16 +0.2 0 0 1 0 0 0 1 0 22 −2.3 0 0 0 1 0 1 1 1 17 +0.1 0 0 1 0 0 0 0 1 21 −2.4 0 0 0 1 1 0 0 0 18 Table 12 Data byte to select integration time [subaddress (04)HEX] DATA FUNCTION Test byte SUBADDRESS 0000 0100 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X INTFU INT1SN Function of the bits: • INTFU = 0 integrator function enabled • INTFU = 1 integrator function disabled • INT1SN = 0 integration time approximately 1 s (default) • INT1SN = 1integration time approximately 0.5 s. 1998 Jul 03 19 Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control TDA9840 MED647 +2 R: −15%; C: −5% VoAF (dB) +1 0 −1 R: +15%; C: +5% −2 10 Fig.4 1998 Jul 03 10 2 10 3 10 4 foAF (Hz) Tolerance scheme of AF frequency response; de-emphasis with CD1, CD2 = 10 nF (±5%), Rinternal = 5 kΩ (±15%). 20 10 5 Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control handbook, full pagewidth SDA C AGC 10 µF C LP 10 nF C DCL 100 nF 1/2 V P XTAL 18 3 17 4 AF from 5.5 MHz Vi 1 AF from 5.742 MHz Vi 2 from external sound source C Vi 3 from external sound source D Vi 4 5% C D2 10 nF 50 µs de-emphasis 16 2.5 mH TDA9840 15 6 30 kΩ VP CVP 10 µF 5 47 pF 10 MHz 19 2 3.3 nF SCL 20 1 100 µF/16 V C ref TDA9840 5% C D1 10 nF 50 µs de-emphasis 2.2 µF 7 14 Vo 1 8 13 Vo 2 9 12 Vo 3 10 11 Vo 4 main 2.2 µF 2.2 µF scart 2.2 µF MBE460 Fig.5 Test circuit of the stereo decoder TDA9840. handbook, full pagewidth 14 VB VP 13 18 TDA9840 12 10 k Ω 11 6 100 µF 7 8 9 10 Vo 1 Vo 2 measurements on outputs Vo 3 Vo 4 16 5 V modulated with 200 mV (p-p) 70 Hz 100 µF / 16 V 100 µF MBE462 Fig.6 Test circuit for measurement of ripple rejection. 1998 Jul 03 21 Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control TDA9840 INTERNAL CIRCUITRY handbook, full pagewidth + + SDA 2 kΩ 1 2 kΩ 20 + 19 – SCL XTAL 3 pF + 13 kΩ + + 5 kΩ + CLP 68 µA 25 kΩ 2 + 17 16 40 µA 60 µA 5 kΩ + 4 25 kΩ Cref 6 D1 + 5 kΩ + 14 Vi 1 22.5 kΩ 5 kΩ 5 kΩ 7 + 10 kΩ 8 10 kΩ 1/2 VP –2 dB IB 200 µA AF inputs 12 1/2 VP 25 kΩ –6 dB 10 25 kΩ 200 µA IB 1/2 VP –6 dB 25 kΩ 11 IB 200 µA MBE461 VP ESD protection diode for pins 2 to 15, 17 and 19 zener diode protection for pins 1, 18 and 20 Fig.7 Internal circuits. 22 Vo 3 + 1/2 VP 1998 Jul 03 Vo 2 AF outputs + 9 Vo 1 + 13 25 kΩ Vi 4 200 µA TDA9840 IB 40 kΩ Vi 3 IB –2 dB 40 kΩ Vi 2 C – 40 µA 5 15 – + GND + 1/2 VP Vi pil C D2 + 5 kΩ VP – 3 25 kΩ CDCL 18 – CAGC +5 V 5 kΩ Vo 4 Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control TDA9840 PACKAGE OUTLINES DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 ME seating plane D A2 A A1 L c e Z b1 w M (e 1) b MH 11 20 pin 1 index E 1 10 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 inches 0.17 0.020 0.13 0.068 0.051 0.021 0.015 0.014 0.009 1.060 1.045 D e e1 L ME MH w Z (1) max. 6.40 6.22 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.0 0.25 0.24 0.10 0.30 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.078 (1) E (1) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT146-1 1998 Jul 03 REFERENCES IEC JEDEC EIAJ SC603 23 EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-05-24 Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control TDA9840 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.050 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 inches 0.10 Z (1) θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013AC 1998 Jul 03 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-24 97-05-22 24 o 8 0o Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. WAVE SOLDERING This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (order code 9398 652 90011). Wave soldering techniques can be used for all SO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. DIP • The longitudinal axis of the package footprint must be parallel to the solder flow. SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. • The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. REPAIRING SOLDERED JOINTS A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1998 Jul 03 TDA9840 25 Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control TDA9840 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1998 Jul 03 26 Philips Semiconductors Product specification TV and VTR stereo/dual sound processor with digital identification and I2C-bus control NOTES 1998 Jul 03 27 TDA9840 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545104/00/03/pp28 Date of release: 1998 Jul 03 Document order number: 9397 750 03999