INTEGRATED CIRCUITS DATA SHEET TDA9851 I2C-bus controlled economic BTSC stereo decoder Product specification File under Integrated Circuits, IC02 1997 Nov 12 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder TDA9851 FEATURES • Voltage Controlled Amplifier (VCA) noise reduction circuit • Stereo or mono selectable at the AF outputs • Stereo pilot PLL circuit with ceramic resonator • Automatic pilot cancellation • Automatic Volume Level (AVL) control (+6 to −15 dB) • I2C-bus transceiver. GENERAL DESCRIPTION The TDA9851 is a bipolar-integrated BTSC stereo decoder for application in TV sets, VCRs and multimedia PCs. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCC supply voltage ICC supply current − 30 40 mA Vo(rms) output voltage (RMS value) composite input voltage 250 mV (RMS) for 100% modulation L + R (25 kHz deviation); fmod = 300 Hz − 500 − mV αcsL,R stereo channel separation L and R 14% modulation; fL = 300 Hz; fR = 3 kHz − 20 − dB THDL,R total harmonic distortion L and R 100% modulation L or R; fmod = 1 kHz − 0.2 1.0 % S/N signal-to-noise ratio mono mode; referenced to 500 mV output signal CCIR 468-2 weighted; quasi peak 50 60 − dB DIN noise weighting filter (RMS value) − 73 − dBA 8 9 9.5 V ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA9851 TDA9851T 1997 Nov 12 SDIP24 SO24 DESCRIPTION VERSION plastic shrink dual in-line package; 24 leads (400 mil) SOT234-1 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 2 1997 Nov 12 C1 composite baseband input 3 C9 R3 R2 21 7 FDO 20 FDI COMP 6 5 3 CPH C4 C10 BPU 19 C11 CW 18 DETECTOR AND VOLTAGE CONTROLLED AMPLIFIER STEREO DECODER CP2 R1 17 C13 TW 4 L−R L+R CER Q1 9 15 22 14 C14 C15 VCAP AGND Vref 16 CAV R4 RFR 10 1 24 13 12 MHA969 DGND 23 I2C-BUS TRANSCEIVER AUTOMATIC VOLUME LEVEL FILTER AND REFERENCE TDA9851 11 n.c. C7 SCL SDA OUTR OUTL I2C-bus controlled economic BTSC stereo decoder Fig.1 Block diagram. VCC 2 SUPPLY C6 CSS DEMATRIX AND MODE SELECT 8 CMO C5 book, full pagewidth CP1 C2 C3 Philips Semiconductors Product specification TDA9851 BLOCK DIAGRAM Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder TDA9851 Component list Electrolytic capacitors ±20%; foil capacitors ±10%; resistors ±5%; unless otherwise specified; see Fig.1. COMPONENT VALUE TYPE REMARK C1 2.2 µF electrolytic C2 220 nF foil C3 2.2 µF electrolytic C4 220 nF foil C5 2.2 µF electrolytic 63 V C6 2.2 µF electrolytic 63 V 63 V ±10% 63 V 63 V C7 4.7 µF electrolytic C9 22 nF foil C10 4.7 nF foil C11 1 µF electrolytic 63 V C13 10 µF electrolytic 63 V C14 100 µF electrolytic 16 V C15 100 µF electrolytic 16 V R1 3.3 kΩ R2 15 kΩ R3 1.3 kΩ R4 100 kΩ CSB503F58 radial leads CSB503JF958 alternative as SMD Q1 1997 Nov 12 4 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder TDA9851 PINNING SYMBOL PIN DESCRIPTION SCL 1 serial clock input (I2C-bus) VCC 2 supply voltage CPH 3 capacitor for phase detector CER 4 ceramic resonator CP1 5 capacitor for pilot detector SCL 1 24 SDA CP2 6 capacitor for pilot detector VCC 2 23 DGND COMP 7 composite input signal CPH 3 22 AGND CMO 8 capacitor DC-decoupling mono CER 4 21 FDI CSS 9 capacitor DC-decoupling stereo RFR 10 resistor for filter reference CP1 5 20 FDO n.c. 11 not connected OUTL 12 output, left channel OUTR 13 Vref handbook, halfpage CP2 6 19 BPU TDA9851 COMP 7 18 CW output, right channel CMO 8 17 TW 14 reference voltage 0.5VCC CSS 9 16 CAV VCAP 15 capacitor for electronic filtering of supply RFR 10 15 VCAP CAV 16 automatic volume control capacitor TW 17 capacitor timing CW 18 capacitor for VCA and band-pass filter lower corner frequency 19 band-pass filter upper corner frequency FDO 20 fixed de-emphasis output FDI 21 fixed de-emphasis input AGND 22 analog ground DGND 23 digital ground SDA 24 serial data input/output (I2C-bus) BPU 1997 Nov 12 14 Vref n.c. 11 13 OUTR OUTL 12 MHA968 Fig.2 Pin configuration. 5 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder TDA9851 The composite signal is fed into a pilot detector/pilot cancellation circuit and into the MPX demodulator. The main L + R signal passes a 75 µs fixed de-emphasis filter and is fed into the dematrix circuit. The decoded sub-signal L − R is sent to the VCA circuit. To generate the pilot signal the stereo demodulator uses a PLL circuit including a ceramic resonator. an input voltage range between 0.1 to 1.1 V (RMS). The circuit adjusts variations in modulation during broadcasting and because of changes in the programme material. The function can be switched off. To avoid audible plops during the permanent operation of the AVL circuit a soft blending scheme has been applied between the different gain stages. A capacitor (4.7 µF) at pin CAV determines the attack and decay time constants. In addition the ratio of attack and decay times can be changed via the I2C-bus. Mode selection Integrated filters The L − R signal is fed via the internal VCA circuit to the dematrix/switching circuit. Mode selection is achieved via the I2C-bus. The filter functions necessary for stereo demodulation are provided on-chip using transconductor circuits. The filter frequencies are controlled by the filter reference circuit via the external resistor R4. FUNCTIONAL DESCRIPTION Stereo decoder Automatic volume level control The automatic volume level stage controls its output voltage to a constant level of typically 200 mV (RMS) from LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER VCC supply voltage VSDA, VSCL voltage of SDA and SCL to GND Vn voltage of all other pins to GND Tamb operating ambient temperature Tstg storage temperature Ves electrostatic handling CONDITIONS MIN. MAX. UNIT 0 9.9 V VCC < 9 V 0 VCC V VCC ≥ 9 V 0 9 V 0 VCC V −20 +70 °C −65 +150 °C − − V Tj < 125 °C note 1 Note 1. Machine model class B. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 1997 Nov 12 PARAMETER CONDITIONS VALUE UNIT TDA9851 (SOT234-1; SDIP24) 55 K/W TDA9851T (SOT137-1; SO24) 90 K/W thermal resistance from junction to ambient 6 in free air Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder TDA9851 CHARACTERISTICS All voltages are measured relative to GND; VCC = 9 V; Rs = 600 Ω; AC-coupled; RL = 10 kΩ; CL = 2.5 nF; fmod = 1 kHz mono signal; composite input voltage 250 mV (RMS) for 100% modulation L + R (25 kHz deviation); Tamb = 25 °C; see Fig.1; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VCC supply voltage 8 9 9.5 V ICC supply current − 30 40 mA Vi(max)(rms) maximum input voltage (RMS value) 2 − − V Zi input impedance 20 25 30 kΩ 9 − − dB Input stage Stereo decoder fmod = 300 Hz; THD < 15% HR headroom for L + R, L and R Vpil(rms) nominal stereo pilot voltage (RMS value) − 50 − mV Vth(on)(rms) pilot threshold voltage stereo on (RMS value) − − 35 mV Vth(off)(rms) pilot threshold voltage stereo off (RMS value) 15 − − mV hys hysteresis − 2.5 − dB Vo(rms) output voltage (RMS value) 100% modulation L + R; fmod = 300 Hz − 500 − mV αcsL,R stereo channel separation L and R 14% modulation; fL = 300 Hz; fR = 3 kHz − 20 − dB THDL,R total harmonic distortion L and R 100% modulation L or R; fmod = 1 kHz − 0.2 1.0 % S/N signal-to-noise ratio mono mode; referenced to 500 mV output signal CCIR 468-2 weighted; quasi peak 50 60 − dB DIN noise weighting filter (RMS value) − 73 − dBA Stereo decoder, oscillator (VCXO); note 1 fo nominal VCXO output frequency (32fH) with nominal ceramic resonator − 503.5 − kHz ∆ffr spread of free-running frequency with nominal ceramic resonator 500.0 − 507.0 kHz ∆fcr capture range frequency nominal pilot ±190 ±265 − Hz 1997 Nov 12 7 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder SYMBOL PARAMETER TDA9851 CONDITIONS MIN. TYP. MAX. UNIT Outputs OUTL and OUTR Zo output impedance − VO DC output voltage 0.45VCC 0.5VCC RL output load resistance (AC-coupled) 5 CL output load capacitance − − 2.5 nF αct crosstalk SAP into L and R 100% modulation; fmod = 1 kHz; SAP; mode selector switched to stereo 50 70 − dB Is nominal timing current for nominal release rate of VCA detector Is can be measured at pin TW via current meter connected to 0.5VCC + 1 V 6.5 8 9.5 µA Relrate nominal detector release rate nominal timing current and external capacitor values − 125 − dB/s maximum boost; note 2 5 6 7 dB maximum attenuation; note 2 14 15 16 dB − 1.5 − dB maximum boost; note 2 − 0.1 − V maximum attenuation; note 2 − 1.125 − V 160 200 250 mV 80 − 120 Ω 0.55VCC V − kΩ VCA Automatic volume level control Gv voltage gain Gstep equivalent step width between the input stages (soft switching system) Viop(rms) input voltage (RMS value) Vo(rms) output voltage in AVL operation (RMS value) Voffset(DC) DC offset voltage between different gain steps voltage at pin CAV 7.0 to 6.83 V or 6.83 to 6.61 V or 6.61 to 5.83 V or 5.83 to 3.1 V; note 3 − − 20 mV Ratt discharge resistors for attack time constant AT1 = 0; AT2 = 0; note 4 340 420 520 Ω AT1 = 1; AT2 = 0; note 4 590 730 910 Ω AT1 = 0; AT2 = 1; note 4 0.96 1.2 1.5 kΩ AT1 = 1; AT2 = 1; note 4 1.7 2.1 2.6 kΩ Idec charge current for decay time 2.0 2.4 µA − 30 − µA − VCAP − 0.7 − normal mode; CCD = 0; note 5 1.6 power-on speed-up; CCD = 1; note 5 Muting at power supply voltage drop for OUTR and OUTL ∆VCC 1997 Nov 12 supply voltage drop for mute active 8 V Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder SYMBOL PARAMETER TDA9851 CONDITIONS MIN. TYP. MAX. UNIT Power-on reset; note 6 VPOR(start) VPOR(end) start of reset voltage end of reset voltage increasing supply voltage − − 2.5 V decreasing supply voltage 4.2 5 5.8 V increasing supply voltage 5.2 6 6.8 V Digital part (I2C-bus pins); note 7 VIH HIGH-level input voltage 3 − VCC ≤ 9 V VIL LOW-level input voltage −0.3 − +1.5 V IIH HIGH-level input current −10 − +10 µA IIL LOW-level input current VOL LOW-level output voltage IIL = 3 mA −10 − +10 µA − − 0.4 V Notes to the characteristics 1. The oscillator is designed to operate together with Murata resonator CSB503F58 or CSB503JF958 as SMD. Change of the resonator supplier is possible, but the resonator specification must be close to the specified ones. 2. The AVL input voltage is internal. It corresponds to the output voltage OUTL and OUTR at AVL off. 3. The listed pin voltage corresponds with typical gain steps of +6 dB, +3 dB, 0 dB, −6 dB and −15 dB. 4. Attack time constant = CCAV × Ratt. 5. –G2 –G1--------- --------20 20 – 10 C CAV × 0.76 V 10 Decay time = ---------------------------------------------------------------------------------I dec Example: CCAV = 4.7 µF; Idec = 2 µA; G1 = −9 dB; G2 = +6 dB → decay time results in 4.14 s. 6. When reset is active the GMU bit (mute) is set and the I2C-bus receiver is in the reset position. 7. The AC characteristics are in accordance with the I2C-bus specification for standard mode (clock frequency maximum 100 kHz). A higher frequency, up to 280 kHz, can be used if all clock and data times are interpolated between standard mode (100 kHz) and fast mode (400 kHz) in accordance with the I2C-bus specification. Information about the I2C-bus can be found in brochure “I2C-bus and how to use it” (order number 9398 393 40011). 1997 Nov 12 9 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder TDA9851 I2C-BUS PROTOCOL I2C-bus format to read (slave transmits data) S Table 1 SLAVE ADDRESS A R/W DATA Explanation of I2C-bus format to read (slave transmits data) NAME DESCRIPTION S START condition; generated by the master Standard SLAVE ADDRESS (MAD) 101 101 1 R/W logic 1 (read); generated by the master A acknowledge; generated by the slave DATA slave transmits an 8-bit data word P STOP condition; generated by the master Table 2 P Definition of the transmitted bytes after read condition MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 Y Y Y Y Y Y Y STP A P Table 3 Function of the bits in Table 2 BITS FUNCTION STP stereo pilot identification (stereo received = 1) Y indefinite I2C-bus format to write (slave receives data) S Table 4 SLAVE ADDRESS A R/W DATA Explanation of I2C-bus format to write (slave receives data) NAME DESCRIPTION S START condition Standard SLAVE ADDRESS (MAD) 101 101 1 R/W logic 0 (write) A acknowledge; generated by the slave DATA see Table 5 P STOP condition Table 5 Definition of the DATA (second byte after MAD) MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 0 0 AT2 AT1 CCD AVLON GMU STEREO 1997 Nov 12 10 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder Table 6 Function of the bits in Table 5 BITS Table 9 FUNCTION TDA9851 AVLON bit setting FUNCTION DATA STEREO mode selection stereo or mono Automatic volume control on 1 GMU mute control OUTL and OUTR Automatic volume control off 0 AVLON AVL on/off CCD increased AVL decay current on/off AT1 and AT2 attack time at AVL Table 7 FUNCTION Mode setting FUNCTION MODE OUTL OUTR READABLE BIT SETTING BIT STP STEREO Left right 1 (stereo received) 1 Mono mono 1 (stereo received) 0 Mono mono 0 (no stereo received) 1 Mono mono 0 (no stereo received) 0 Table 8 Table 10 CCD bit setting DATA GMU Forced mute at OUTR and OUTL 1 No forced mute at OUTR and OUTL 0 1997 Nov 12 Load current for normal AVL decay time 0 Increased load current 1 Table 11 AVL attack time Mute setting FUNCTION DATA 11 DATA Ratt (Ω) AT1 AT2 420 0 0 730 1 0 1200 0 1 2100 1 1 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder TDA9851 INTERNAL PIN CONFIGURATIONS 1 2 + 1.8 kΩ MHA972 MHA971 Fig.3 Pin 1; SCL. Fig.4 Pin 2; VCC. 3 + 4 + 3 kΩ MHA974 10 kΩ 10 kΩ MHA973 Fig.5 Pin 3; CPH. Fig.6 Pin 4; CER. + 6 5 + 3.5 kΩ 8.5 kΩ 12 kΩ MHA975 MHA976 Fig.7 Pin 5; CP1. 1997 Nov 12 Fig.8 Pin 6; CP2. 12 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder TDA9851 7 + 8, 9 25 kΩ + 25 kΩ 10 kΩ 50 pF 10 kΩ 25 kΩ MHA978 100 pF MHA977 Fig.9 Pin 7; COMP. Fig.10 Pin 8; CMO and pin 9; CSS. + 12, 13 80 Ω 1 kΩ + 10 MHA979 MHA980 Fig.11 Pin 10; RFR. Fig.12 Pin 12; OUTL and pin 13; OUTR. 14 + 15 3.4 kΩ 4.7 kΩ 300 Ω 3.4 kΩ 5 kΩ MHA982 MHA981 Fig.13 Pin 14; Vref. 1997 Nov 12 Fig.14 Pin 15; VCAP. 13 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder TDA9851 17 16 + + MHA983 MHA984 Fig.15 Pin 16; CAV. Fig.16 Pin 17; TW. + 21 18 + + 6 kΩ 16 kΩ 19 MHA985 MHA986 Fig.17 Pin 18; CW. Fig.18 Pin 19; BPU and pin 21; FDI. 24 20 1.8 kΩ + MHA987 MHA988 Fig.19 Pin 20; FDO. 1997 Nov 12 Fig.20 Pin 24; SDA. 14 1997 Nov 12 SCL SDA handbook, full pagewidth 1 SCL 24 SDA 15 VCC 2 23 C4 DGND 3 R1 C3 CPH 22 AGND 4 5 C2 CP1 20 FDO R3 6 C1 COMP composite baseband input CP2 7 C11 CW 18 TDA9851 19 BPU C10 8 C5 CMO 17 TW C13 9 C6 CSS 16 CAV C7 R4 RFR 10 15 VCAP C14 n.c. 11 14 Vref C15 OUTR MHA970 OUTL 12 13 I2C-bus controlled economic BTSC stereo decoder Fig.21 Application circuit. Q1 CER 21 FDI R2 C9 Philips Semiconductors Product specification TDA9851 APPLICATION INFORMATION Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder TDA9851 PACKAGE OUTLINES SDIP24: plastic shrink dual in-line package; 24 leads (400 mil) SOT234-1 ME seating plane D A2 A A1 L c e Z b1 (e 1) w M MH b 13 24 pin 1 index E 1 12 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.7 0.51 3.8 1.3 0.8 0.53 0.40 0.32 0.23 22.3 21.4 9.1 8.7 1.778 10.16 3.2 2.8 10.7 10.2 12.2 10.5 0.18 1.6 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-02-04 SOT234-1 1997 Nov 12 EUROPEAN PROJECTION 16 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder TDA9851 SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c HE y v M A Z 13 24 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.61 0.60 0.30 0.29 0.050 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT137-1 075E05 MS-013AD 1997 Nov 12 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-24 97-05-22 17 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. WAVE SOLDERING This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Wave soldering techniques can be used for all SO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. SDIP SOLDERING BY DIPPING OR BY WAVE • The longitudinal axis of the package footprint must be parallel to the solder flow. The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. • The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. REPAIRING SOLDERED JOINTS A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1997 Nov 12 TDA9851 18 Philips Semiconductors Product specification I2C-bus controlled economic BTSC stereo decoder TDA9851 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 Nov 12 19 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1997 SCA55 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 547047/1200/01/pp20 Date of release: 1997 Nov 12 Document order number: 9397 750 02702