INTEGRATED CIRCUITS DATA SHEET SAA7740H Digital Audio Processing IC (DAPIC) Product specification Supersedes data of 1996 Mar 11 File under Integrated Circuits, IC01 1997 May 30 Philips Semiconductors Product specification Digital Audio Processing IC (DAPIC) SAA7740H FEATURES Hardware • Two digital inputs and two digital outputs in the I2S-bus format (i.e. 4 audio channels) • Independent input/output interfaces • Slave input/output interfaces • External delay line processing for delays up to 1 second • Slave processing • Reverberation with selectable reverberation time (up to 5 seconds) and energy • I2C-bus microcontroller interface • DC filtering at the inputs • One programmable 2nd-order digital filter unit • Three different surround sound programs to obtain a spatial effect on 4 loudspeakers • Two multiply accumulate processor units (24 × 16-bit/MAC) • Passive DOLBY surround processing with the addition of an external dynamic noise reduction IC • DRAM interface and address computation unit for external delay lines • Karaoke processing • On-chip coefficient and external delay line address storage • Quad 8th-order correction filtering • Dual 16th-order correction filtering • Digital volume and balance control • Hardware controlled soft mute via the MUTE pin • Hardware controlled soft demute via the RST pin • Soft controlled soft mute/demute via the microcontroller interface • Operating ambient temperature; −40 to +85 °C. • Input switching matrix Software • Output rear and front switching matrix. • 5-band parametric equalizer with selectable centre frequency, slope setting and boost/cut gain settings from −12 to +12 dB APPLICATIONS • Stereo width control from mono to stereo to spatial stereo • Audio combination sets • Digital amplifiers • Car audio systems • Stereo Hall-effects for field acoustics, such as concert halls, with 8 coefficients and 8 delayed taps per channel • TV audio channels. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDD(tot) total DC supply voltage all VDD pins 4.5 5.0 5.5 V IDD(tot) total DC supply current fxtal = 16.9344 MHz − 60 − mA fxtal input crystal frequency 12.288 16.9344 23.0 MHz Ptot total power dissipation fxtal = 16.9344 MHz − 0.3 − W Tamb operating ambient temperature −40 − +85 °C ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA7740H QFP64 1997 May 30 DESCRIPTION plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 × 20 × 2.8 mm 2 VERSION SOT319-2 Philips Semiconductors Product specification Digital Audio Processing IC (DAPIC) SAA7740H BLOCK DIAGRAM handbook, full pagewidth CLK1/XTAL1 XTAL2 SCCLK VDDX VSSX CLKO 60 61 63 TSTCLK TST1 TST2 47 48 45 TST3 49 56 59 9, 13, 25, 40, 46, 50, 55 XTAL OSCILLATOR CLOCK COUNTER VSS 7 7, 8, 26, 32, 38, 53, 54 62 7 DIWS DI1D DI2D DIBCK RST ALL 43 DIGITAL SIGNAL PROCESSING CORE 2nd-ORDER FILTER MAC OFFSET FILTER REGISTERS 41 42 44 I2 S-BUS INPUT INPUT BUFFER 36 34 OUTPUT BUFFER 64 PROGRAM COUNTER 16 PROGRAMMABLE ROM 7 COEFFICIENT RAM 37 31 to 27/24 to 21 ADDRESS CONTROL UNIT SAA7740H I 2 C-BUS INTERFACE Fig.1 Block diagram. 1997 May 30 3 DO2D DOBCK MUTE RAS CAS CAS2 WE OE D0 to D3 52 AS2 DO1D A0 to A8 MLC173 AS1 DOWS 11, 12, 15, 16 20 33 2 3 16 51 35 4 19 10 17 18 14 1 16 I2 S-BUS OUTPUT VDD A8B MUX SCL SDA Philips Semiconductors Product specification Digital Audio Processing IC (DAPIC) SAA7740H PINNING SYMBOL PIN DESCRIPTION SYMBOL PIN DESCRIPTION RST 1 reset input (active LOW) DO1D 34 digital audio output 1 (I2S-bus) SCL 2 serial clock input (I2C-bus) DO2D 35 digital audio output 2 (I2S-bus) DOWS 36 digital audio input word select (I2C-bus) SDA 3 serial data input/output MUTE 4 mute input (active HIGH) DOBCK 37 digital audio input serial bit clock n.c. 5 not connected VDD 38 supply voltage n.c. 6 not connected n.c. 39 not connected VDD 7 supply voltage VSS 40 ground supply 41 digital audio input 1 (I2S-bus) 42 digital audio input 2 (I2S-bus) VDD 8 supply voltage DI1D VSS 9 ground supply DI2D CAS 10 column address strobe (DRAM) (active LOW) DIWS 43 digital audio input word select DIBCK 44 digital audio input serial bit clock TSTCLK 45 clock input for test mode (should be tied LOW) D0 11 input/output data bus line 0 (DRAM) D1 12 input/output data bus line 1 (DRAM) VSS 13 ground supply VSS 46 ground supply 47 test pin input 1 (should be tied LOW) OE 14 output buffer enable (DRAM) (active LOW) TST1 D2 15 input/output data bus line 2 (DRAM) TST2 48 D3 16 input/output data bus line 3 (DRAM) test pin input 2 (should be tied LOW) CAS2 17 second column address strobe (active LOW) TST3 49 test pin input 3 (should be tied LOW) WE 18 write enable (DRAM; active LOW) VSS 50 ground supply RAS 19 row address strobe (DRAM; active LOW) AS1 51 address select input 1 (I2C-bus) AS2 52 address select input 2 (I2C-bus) A8B 20 inverse MSB address line output (DRAM) VDD 53 supply voltage VDD 54 supply voltage A8 21 address line output 8 (DRAM) VSS 55 ground supply A7 22 address line output 7 (DRAM) clock or crystal input 23 address line output 6 (DRAM) CLK1/ XTAL1 56 A6 A5 24 address line output 5 (DRAM) n.c. 57 not connected VSS 25 ground supply n.c. 58 not connected VDD 26 supply voltage XTAL2 59 crystal output 2 A4 27 address line output 4 (DRAM) VDDX 60 crystal supply voltage A3 28 address line output 3 (DRAM) VSSX 61 crystal ground supply A2 29 address line output 2 (DRAM) SCCLK 62 A1 30 address line output 1 (DRAM) scan test clock input (should be tied LOW) A0 31 address line output 0 (DRAM) CLKO 63 clock signal output VDD 32 supply voltage ALL 64 MUX 33 address latch strobe output (SRAM) mode select input (should be tied HIGH) 1997 May 30 4 Philips Semiconductors Product specification 52 AS2 53 VDD 54 VDD RST 1 51 AS1 SCL 2 50 VSS SDA 3 49 TST3 MUTE 4 48 TST2 n.c. 5 47 TST1 n.c. 6 46 VSS VDD 7 45 TSTCLK VDD 8 44 DIBCK VSS 9 43 DIWS SAA7740H CAS 10 42 DI2D D0 11 41 DI1D D1 12 40 VSS VSS 13 39 n.c. OE 14 38 VDD D2 15 37 DOBCK D3 16 36 DOWS 5 VDD 32 A0 31 A1 30 A2 29 A3 28 A4 27 VDD 26 VSS 25 33 MUX A5 24 RAS 19 A6 23 34 DO1D A7 22 WE 18 A8 21 35 DO2D A8B 20 CAS2 17 Fig.2 Pin configuration. 1997 May 30 55 VSS 56 CLK1/XTAL1 57 n.c. 58 n.c. SAA7740H 59 XTAL2 60 VDDX 61 VSSX 62 SCCLK 64 ALL handbook, full pagewidth 63 CLKO Digital Audio Processing IC (DAPIC) MLC156 Philips Semiconductors Product specification Digital Audio Processing IC (DAPIC) SAA7740H GENERAL DESCRIPTION GENERAL DAPIC MODE The SAA7740H is a function-specific digital signal processor. The device is capable of performing processing for listening-environments such as equalization, hall-effects, reverberation, surround-sound and digital volume/balance control. The SAA7740H can also be reconfigured (in a dual and quad filter mode) so that it can be used as a digital filter with programmable characteristics. In the general DAPIC mode two variants are available (see Figs 3 and 4). In this mode the DAPIC accepts 2 stereo input signals. DC filtering is performed on the inputs before further processing. On one of the stereo inputs a 5-band graphic equalization can be performed. The stereo image of this signal can be controlled from mono to stereo. In the first variant (see Fig.3) a stereo hall-effect can be added to the signal by means of direct reflections. In the second variant (see Fig.4) a reverberation effect can be added to the signal by means of exponential decaying reflections. Surround-sound can then be created for the rear loudspeakers. The surround-sound module is also able to provide karaoke. For reasons of silicon efficiency, the SAA7740H realises most functions directly in hardware. The flexibility exists in the possibility to download function parameters, correction coefficients and various configurations from a host microcontroller (see Fig.1). The parameters can be passed in real time and all functions can be switched on simultaneously. The surround-sound module accepts the second stereo input, a microphone signal can be added via the 5-band equalizer. At the output, each of the 4 channels can be individually delayed via the external DRAM. The interfacing and addressing of the DRAM is performed by the DAPIC. The communication with a host microcontroller conforms with the standard I2C-bus format. The SAA7740H accepts 2 digital stereo signals in the I2S-bus format at audio sampling frequency (fas) and provides 2 digital stereo outputs. The applications for the general mode are digital amplifiers, audio combination sets and TV audio channels. Mode description The SAA7740H can be set in four basic modes of operation. 1997 May 30 6 1997 May 30 (1) External DRAM. SWITCHES DC FILTERS STEREO CONTROL (1) (1) SURROUND SOUND OR KARAOKE DELAY hall effect DELAY (1) (1) (1) VOLUME/ BALANCE DELAY (1) MLC151 SWITCHES Digital Audio Processing IC (DAPIC) 7 handbook, full pagewidth Fig.3 General DAPIC mode with hall-effect. 5 - BAND GRAPHIC EQUALIZER 5 - BAND GRAPHIC EQUALIZER Philips Semiconductors Product specification SAA7740H 1997 May 30 (1) External DRAM. SWITCHES DC FILTERS STEREO CONTROL SURROUND SOUND OR KARAOKE reverberation generator (1) (1) (1) VOLUME/ BALANCE DELAY (1) MLC152 SWITCHES Digital Audio Processing IC (DAPIC) 8 handbook, full pagewidth Fig.4 General DAPIC mode with reverberation. 5 - BAND GRAPHIC EQUALIZER 5 - BAND GRAPHIC EQUALIZER Philips Semiconductors Product specification SAA7740H Philips Semiconductors Product specification Digital Audio Processing IC (DAPIC) SAA7740H 16 poles and 16 zeros can be selected arbitrarily from the Z-domain. At the output, one of the channels can be delayed internally by the DAPIC. The two corrected outputs can be added to either one of the two stereo outputs. DUAL-FILTER MODE In the dual-filter mode one mono signal is accepted (see Fig.5) The input can be selected from either one of the 2 stereo inputs (from the left or right input channel). DC filtering is performed at the input before further processing. Two separate corrections, in parallel, can be performed by means of an 8-band graphic equalizer. The application for this mode is in loudspeaker correction. handbook, full pagewidth 16 POLE/ZERO CORRECTION FILTER FIXED DELAY 11 SAMPLES DC FILTERS 16 POLE/ZERO CORRECTION FILTER SWITCHES SWITCHES MLC153 Fig.5 Dual filter mode. 1997 May 30 9 Philips Semiconductors Product specification Digital Audio Processing IC (DAPIC) SAA7740H QUAD-FILTER MODE STEREO EXPANSION MODE In the quad-filter mode two stereo signals are accepted (see Fig.6). DC filtering is performed at the inputs before further processing. A correction can be performed on the input signals using a 4-band graphic equalizer, i.e. 8 poles and 8 zeros can be placed arbitrarily in the Z-domain. At the output, different delays can be applied to the 4 channels via the external DRAM. The interfacing and addressing of the DRAM is performed by the DAPIC. In the stereo expansion mode one stereo signal is accepted (see Fig.7). DC filtering is performed at the inputs before further processing. A 4-band graphic equalization is first performed after which a complex stereo expansion is applied. A room effect can be added by the addition of early reflections. The applications for this mode are in the headphone out-of-head and incredible stereo applications. The application for this mode is in 4-channel correction applications such as car and home audio systems. handbook, full pagewidth 8 POLE/ZERO CORRECTION FILTER 8 POLE/ZERO CORRECTION FILTER SWITCHES DC FILTERS DELAY (1) SWITCHES 8 POLE/ZERO CORRECTION FILTER 8 POLE/ZERO CORRECTION FILTER MLC154 (1) External DRAM. Fig.6 Quad filter mode. 1997 May 30 10 1997 May 30 (1) External DRAM. SWITCHES DC FILTERS 4 - BAND EQUALIZER (1) 8 POLE/ZERO (1) 8 POLE/ZERO (1) DELAY (1) Hall-effect DELAY VOLUME/ BALANCE MLC155 SWITCHES Digital Audio Processing IC (DAPIC) 11 Fig.7 Stereo expansion mode. D STEREO CONTROL D handbook, full pagewidth 4 - BAND EQUALIZER Philips Semiconductors Product specification SAA7740H Philips Semiconductors Product specification Digital Audio Processing IC (DAPIC) SAA7740H The transfer byte organization is as follows: FUNCTIONAL DESCRIPTION The SAA7740H is used as a slave device. The internal operation is automatically synchronized with the word select clock of the incoming data (I2S-bus format). Within an input frame of data, at fas, 384 clock cycles are needed to compute a stereo output sample. The external clock therefore, should be minimum 384fas. External clocks which generate more than 384 clocks cycles will cause the processor to return to a wait state. START condition The external clock can be either a crystal connected directly to the DAPIC, or any clock generated in the system which contains DAPIC. STOP condition. First byte (8 bits) Acknowledge (1-bit) Second byte (8 bits) Acknowledge (1-bit) Third to tenth byte (8 bits) Acknowledge (1-bit) The first byte is the address of the I2C-bus device being addressed. If the device detects its address it answers with an acknowledge by pulling down the data line (SDA) for one clock period (SCL line). The second byte contains the address of the internal RAM to which the first new coefficient should have written. The data will then be transmitted. Each new word (coefficient) is 2 bytes wide. Up to four words of data can be written within one transfer. Should the mode of the feature register be addressed then only one data word will be transferred. The I2S-bus Two I2S-bus inputs and outputs are available on the DAPIC. The serial clock (DIBCK and DOBCK) and the word select (DIWS and DOWS) are applied from an external source. The two inputs and outputs are fully synchronized. However, the inputs do not have to be synchronized with the outputs. The clock and word select signals can be separated at the input and output. Because the I2C-bus (on the DAPIC) is a slave receiver bus, the clock has to be generated by the host microcontroller. The input and output buses support word lengths in accordance with the I2S-bus standard. Up to 20 significant bits can be read by the DAPIC. Zeros will be added at the LSB position should less than 20 bits be applied. If more than 20 bits are applied the extra LSBs will be ignored. The stereo word rate (fas) can be either 32, 44.1 or 48 kHz. The minimum time interval between two I2C-bus transfers (bus free between a STOP and START condition) should coeff + 1 be: t inv > ------------------------ ms f as Because the DAPIC is a slave device it can only be connected to a master I2S-bus transmitter or receiver (see Chapter “Timing characteristics” and Fig.9). Where: Number of coefficients = coeff Frequency fas should be in kHz. I2C-bus control (SCL and SDA) The I2C-bus interface is used to control the operation of the DAPIC for the audio signal processing and write the coefficients and the external delay line addresses of the different signal processing algorithms. New coefficients are updated in real time to the internal RAM. Table 1 I2C-bus slave address. BIT 7 0 BIT 6 0 BIT 5 1 BIT 4 1 BIT 3 BIT 2 BIT 1 BIT 0 0 AS2(1) AS1(1) 0 Note 1. AS1 and AS2 are the hardware (pin) programmable address bits. When the device detects this address it will respond with an acknowledge pulse on the SDA line. 1997 May 30 12 Philips Semiconductors Product specification Digital Audio Processing IC (DAPIC) SAA7740H Improper acknowledge generated by the DAPIC If an I2C-bus device, other than DAPIC, is addressed by the master then the DAPIC will generate a short acknowledge pulse. The DAPIC starts pulling down the SDA line at the trailing edge of the SCL clock pulse. and releases the SDA line approximately 390 ns after the leading edge of the following SCL LOW-to-HIGH transition (see Fig.8). This improper acknowledge pulse can cause the I2C-bus master to detect an incorrect acknowledgement, depending on the capturing moment of the SDA line by the I2C-bus master. Any possible non-acknowledgements of involved I2C-bus devices, including the SAA7740H, will be masked thus making the system unreliable. To avoid these problems the I2C-bus master should only capture the SDA line at such a moment that the improper acknowledge pulse will not be detected. non-DAPIC device address handbook, full pagewidth data output from transmitter improper acknowledge generated by DAPIC data output from DAPIC SCL from master 1 2 7 8 9 S 390 ns (typ) START condition Fig.8 Improper acknowledge generated by the DAPIC. 1997 May 30 13 MGK425 Philips Semiconductors Product specification Digital Audio Processing IC (DAPIC) SAA7740H For fast DRAMs, the maximum value for RAS to CAS delay time (tdRAS;CAS) is important. DRAM interface The DRAM interface contains a nibble wide data bus, a 9-bit wide address bus and all necessary control signals to enable the different DRAM configurations. Different DRAM combinations can be connected to the DAPIC. The smallest DRAM is a 64 × 4-bit (256 kbits) RAM. For this configuration, 16K data words can be stored. When this RAM is connected to the DAPIC, the MSB address signal (A8) can be felt floating. Timing of the control signals RAS, CAS, CAS2, A8B, OE and WE is related to the applied clock frequency of the DAPIC. The important timing parameters are the page mode cycle time (tcy;CAS), the access time (tacc;RAS), the refreshing rate and the maximum value for RAS to CAS delay time (tdRAS;CAS) (see Chapter “Timing characteristics” and Fig.10). A read/write operation will always be executed in the page mode (one row address and four column addresses) because every data transfer consists of 4 nibbles. The DAPIC can address up to 1 Mbit DRAMs. However, RAMs greater than 1 Mbit can also be connected. This, therefore, implies that the redundant address lines of the RAM must be fixed to VDD or VSS or must be joined with one of the other address pins. The choice of a 256 kbit or a 1 Mbit DRAM device must be indicated by a flag bit residing in the start address control word of the different delay lines. The refresh time of the DRAM (trfsh) must be greater than; 2 addr t rfsh > ------------- ms 3f as where ‘addr’ is the number of physical address lines and fas is measured in kHz. 1997 May 30 14 Philips Semiconductors Product specification Digital Audio Processing IC (DAPIC) SAA7740H LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD DC supply voltage (each supply pin) −0.5 +6.5 V ∆VDD voltage difference between VDD and VDDX − 550 mV IIK DC input clamp diode current VI < −0.5 V or VI > VDD + 0.5 V − ±10 mA IOK DC output clamp diode current (output type 4 mA) VO < −0.5 V or VO > VDD + 0.5 V − ±20 mA IO DC output sink or source current (output type 4 mA) −0.5 < VO < VDD + 0.5 V − ±20 mA IDD DC supply current per pin − 50 mA ISS DC supply current per pin − 50 mA LTCH latch-up protection 100 − mA PO power dissipation per output − 100 mW Ptot total power dissipation − 1 W Tstg storage temperature −65 +150 °C Tamb operating ambient temperature −40 +85 °C Ves electrostatic discharge CIC specification/test method note 1 −3000 +3000 V note 2 −300 +300 V Notes 1. Human body model: C = 100 pF; R = 1.5 kΩ. 2. Machine model: C = 200 pF; L = 2.5 µH; R = 0 Ω. THERMAL CHARACTERISTICS SYMBOL Rth j-a 1997 May 30 PARAMETER thermal resistance from junction to ambient in free air 15 VALUE UNIT 47 K/W Philips Semiconductors Product specification Digital Audio Processing IC (DAPIC) SAA7740H DC CHARACTERISTICS VDD = 4.5 to 5.5 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL PARAMETER VDDn DC supply voltage (pins 7, 8, 26, 32, 38, 53, 54 and 60) IDD(tot) total of all DC supply current pins Ptot total power dissipation VIH CONDITIONS MIN. TYP. MAX. UNIT 4.5 5.0 5.5 V fxtal = 16.9344 MHz − 60 − mA fxtal = 16.9344 MHz − 300 − mW HIGH level input voltage (pins 1, 3, 4, 11, 12, 15, 16, 36, 37, 41 to 45, 47 to 49, 51, 52, 62 and 64) 0.7VDD − − V VIL LOW level input voltage (pins 1, 3, 4, 11, 12, 15, 16, 36, 37, 41 to 45, 47 to 49, 51, 52, 62 and 64) − − 0.3VDD V Vth(pos) Schmitt trigger positive-going threshold (pin 2) − − 0.8VDD V Vth(neg) Schmitt trigger negative-going threshold (pin 2) 0.2VDD − − V Vhys hysteresis voltage (pin 2) − 0.33VDD − V VOH HIGH level output voltage (pins 10 to 12, 14 to 24, 27 to 31, 33 to 35 and 63) VDD = 4.5 V; IO = 4 mA 4.0 − − V VOL LOW level output voltage (pins 3, 10 to 12, 14 to 24, 27 to 31, 33 to 35 and 63) VDD = 4.5 V; IO = 4 mA − − 0.5 V ILI input leakage current (pins 1, 2, 4, 36, 37, 41 to 45, 47 to 49, 51, 52 and 62) VDD = 0 or 5.5 V − − ±1 µA IZO output leakage current; 3-state VDD = 0 or 5.5 V (pins 3, 11, 12, 15 and 16) − − ±5 µA Rpd internal pull-down resistance to VSS (pin 64) VI = VDD 17 − 134 kΩ tr(i) input rise time VDD = 5.5 V − 6 200 ns tf(i) input fall time VDD = 5.5 V − 6 200 ns tr(o) output rise time for LOW-to-HIGH transition VDD = 4.5 V; Tamb = 85 °C; − CL = pF; pins 11, 12, 15 and 16 − 9.5 + 0.4CL ns − − 8.5 + 0.4CL ns VDD = 4.5 V; Tamb = 85 °C; − CL = pF; pins 11, 12, 15 and 16 − 11 + 0.5CL ns VDD = 4.5 V; Tamb = 85 °C; CL = pF; pins 10, 14, 17 to 24, 27 to 31, 33 to 35 and 63 − 9.0 + 0.5CL ns VDD = 4.5 V; Tamb = 85 °C; CL = pF; pins 10, 14, 17 to 24, 27 to 31, 33 to 35 and 63 tf(o) output fall time for HIGH-to-LOW transition 1997 May 30 16 − Philips Semiconductors Product specification Digital Audio Processing IC (DAPIC) SAA7740H AC CHARACTERISTICS VDDX = 5 V; Tamb = +25 °C; unless otherwise specified. SYMBOL PARAMETER fxtal crystal input frequency αf spurious frequency attenuation I59 crystal current output (pin 59) g CONDITIONS ≥384fas MIN. TYP. MAX. UNIT 12.288 16.9344 23.0 MHz 20 − − dB − − 1 mA transconductance at maximum current − 0.4 − mS Vxtal voltage across crystal − 500 − mV CL load capacitance − − 15 pF 1⁄ half clock period of external clock 21 − − ns 2Tclk slave mode only TIMING CHARACTERISTICS SYMBOL PARAMETER MIN. MAX. UNIT tHC pulse width HIGH, DIBCK and DOBCK 110 − ns tLC pulse width LOW, DIBCK and DOBCK 110 − ns tr DIBCK and DOBCK rise time − 20 ns tf DIBCK and DOBCK fall time − 20 ns th1 DIWS and DOWS hold time 10 − ns tsu1 DIWS and DOWS set-up time 20 − ns th2 DI1D and DI2D hold time 10 − ns tsu2 DI1D and DI2D set-up time 20 − ns tacc DO1D and DO2D access time − 25 + 0.5CL (CL in pF) ns half clock period 21 − ns − ns − ns DRAM timing 1⁄ 2Tclk 4× 1⁄ 2Tclk − 12 1⁄ T 2 clk − 12 tp;RAS RAS precharge time tW;RAS RAS pulse width 16 × tsu;RA row address set-up time 1⁄ 2Tclk th;RA row address hold time 1⁄ 2Tclk − 12 tdRAS;CAS RAS to CAS delay time 2 × 1⁄2Tclk − 11 th;CAS CAS hold time 4× th;RAS RAS hold time 2× tRAS;CA RAS to column address − −8 1⁄ T 2 clk 1⁄ T 2 clk 2 × 1⁄2Tclk + 14 ns − ns − 12 − ns 1⁄ thCA;RAS column address hold time from RAS 5× column address hold time from RAS precharge 1⁄ tlCA;RAS column address to RAS lead time 3 × 1⁄2Tclk − 8 1⁄ 2Tclk − 11 2Tclk − 12 tpCAS;RAS CAS to RAS precharge time 4× tsu;CA column address set-up time 1⁄ 17 ns ns − 12 thCA;RASp 1997 May 30 − − 1⁄ 2Tclk 2Tclk − 8 − 14 2Tclk +8 ns − ns − ns − ns − ns − ns Philips Semiconductors Product specification Digital Audio Processing IC (DAPIC) SYMBOL SAA7740H PARAMETER MIN. MAX. column address hold time to CAS 3× th2CA;CAS column address hold time to CAS precharge 1⁄ tW;CAS CAS pulse width 2 × 1⁄2Tclk − 14 th1CA;CAS tp;CAS CAS precharge time 1⁄ 2Tclk 2Tclk − − 14 15 2× 1⁄ 2Tclk 1⁄ 2Tclk − 11 UNIT − ns − ns − ns − ns tcy;CAS CAS page mode cycle time 4× − ns tacc;CA access time from column address − 3 × 1⁄2Tclk − 20 ns tacc;CAS access time from CAS − 2 × 1⁄2Tclk − 24 ns tacc;RAS access time from RAS − thDAT;CAS data hold time from CAS 2 − ns trcy;def read cycle definition time 4 × 1⁄2Tclk − 10 − ns tsu;DAT data input set-up time 1⁄ − ns th;DAT data input hold time − 16 − ns thDAT;RAS data input hold time from RAS − 15 − ns twcy;def write cycle definition time − 12 − ns toff 4× 2Tclk − 8 3 × 1⁄2Tclk 5 × 1⁄2Tclk 2 × 1⁄2Tclk − output data disable time 1⁄ VH handbook, full pagewidth CL VL t HC t h1 t LC t su1 WS t su2 t h2 DATA IN t acc DATA OUT MLC157 Fig.9 I2S-bus timing diagram. 1997 May 30 18 1⁄ 2Tclk 2Tclk + 8 − 22 ns ns Philips Semiconductors Product specification Digital Audio Processing IC (DAPIC) handbook, full pagewidth t p;RAS SAA7740H tf t W;RAS t hCA;RAS tr VH RAS VL tt t h;CAS t pCAS;RAS t dRAS;CAS t W;CAS t cy;CAS t h;RAS t p;CAS CAS t RAS;CA t su;CA t su;RA t h1CA;CAS tr t h;RA ROW A0 to A8 COLUMN ADD t lCA;RAS t hCA;RASp t h2CA;CAS COLUMN ADD COLUMN ADD WE t acc;CA t rcy;def t rcy;def READ t rcy;def t rcy;def t acc;CAS OE t acc;RAS D0 to D3 t hDAT;CAS DATA OUT DATA OUT t wcy;def t wcy;def WE WRITE OE t wcy;def t su;DAT t wcy;def t h;DAT D0 to D3 DATA IN DATA t off IN t hDAT;RAS t p;RAS t W;RAS RAS t p;RAS t RAS;CA t pCAS;RAS REFRESH CAS MLC158 A0 to A8 ROW Fig.10 Timing diagram DRAM interface. 1997 May 30 19 Philips Semiconductors Product specification Digital Audio Processing IC (DAPIC) SAA7740H Two data line have been implemented as input from an external processor for the four audio channels. Because of this configuration the DAPIC operates in the following manner. I2S-BUS PROTOCOL The I2S-bus digital interface is used for communication to external digital sources. It is a 3-line serial bus with one line each for data, clock and word select. Figure 11 illustrates an excerpt from the Philips I2S-bus specification interface report with respect to general timing and format of the bus. Word select (WS) at logic 0 signifies the left channel and logic 1 the right channel. The I2S-bus input block reads 4 samples (left and right samples of the front and rear channel) and stores the information into the register file. The operators read from the register file, process the data and store the intermediate results back into the register file. If a delay line is required, the external RAM will need to be accessed. The output samples are read from the register file and are passed via the fade unit to the I2S-bus output block. The same operation is repeated for each incoming audio sample. The serial data is transmitted in two’s complement with MSB first. One clock period after the negative edge of the WS line, the MSB of the left channel is transmitted. Data is synchronized on the negative edge of the clock and latched on the positive edge. T handbook, full pagewidth t LC t HC VIH SCK VIL t sr SD t hr VIH VIL WS SCK WS SD MSB LEFT MSB RIGHT MLC159 Fig.11 I2S-bus timing format. 1997 May 30 20 Philips Semiconductors Product specification Digital Audio Processing IC (DAPIC) SAA7740H I2C-BUS PROTOCOL Data transfer The I2C-bus is intended for 2-way, 2-line communication between different ICs or modules. The two lines are the serial data line (SDA) and the serial clock line (SCL). Both lines must be connected to the supply rail via a pull-up resistor when connected to the output stages of a microcontroller. Data transfer can only be initiated when the bus is not busy. Full details of the I2C-bus are given in the document “The I2C-bus and how to use it”. This document may be ordered using the code 9398 393 40011. A device generating a message is a ‘transmitter’, a device receiving a message is a ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the device are the ‘slaves’ (see Fig.14). Acknowledge The number of data bytes that are transferred between the START and STOP conditions, from transmitter to receiver, is unlimited. Each byte is followed by an acknowledge bit. The acknowledge bit is a HIGH level bit placed on the bus by the transmitter, whereas the master generates an extra acknowledge bit which is related to the clock pulse. A slave receiver which is addressed must generate an acknowledge bit after the reception of each byte. The master must also generate an acknowledge bit after the reception of each byte that has been clocked out of the slave transmitter. Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulses as changes in the data line at this time will be interpreted as control signals. The maximum clock frequency is 100 kHz (see Fig.12). The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Set-up and hold times must also be taken into account. A master receiver must signal an end-of-data to the transmitter. This is achieved by not generating an acknowledge on the last byte that has been clocked out of the slave. In this condition the transmitter must leave the data line HIGH to enable the master to generate a STOP condition (see Fig.15). START and STOP condition In the START and STOP condition the data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition on the data line, while the clock is HIGH, is defined as the START condition (S). A LOW-to-HIGH transition on the data line, while the clock is HIGH, is defined as the STOP condition (P); (see Fig.13). handbook, full pagewidth SDA SCL data line stable data valid change of data allowed Fig.12 Bit transfer on the I2C bus. 1997 May 30 21 MLC160 Philips Semiconductors Product specification Digital Audio Processing IC (DAPIC) SAA7740H handbook, full pagewidth SDA SCL S P START condition STOP condition MLC161 Fig.13 START and STOP conditions. handbook, full pagewidth SDA MSB 1 SCL acknowledgement signal from receiver acknowledgement signal from receiver byte complete interrupt within receiver clock line held LOW while interrupts are serviced 2 7 8 9 1 2 3 to 8 9 ACK S P START condition STOP condition MLC162 Fig.14 Data transfer on the I2C-bus. handbook, full pagewidth data output from transmitter not acknowledge data output from receiver acknowledge SCL from master 1 2 7 8 9 MLC163 S clock pulse for acknowledgement START condition Fig.15 Acknowledge on the I2C-bus. 1997 May 30 22 Philips Semiconductors Product specification Digital Audio Processing IC (DAPIC) SAA7740H APPLICATION INFORMATION Clock circuit and oscillator The clock generation of the SAA7740H is designed to accommodate two main modes, the master and the slave. handbook, halfpage C1 In the master mode, the DAPIC is the master in the system. The clock is generated by connecting a crystal to the oscillator pins CLK1/XTAL1 and XTAL2 (see Fig.16). 10 pF In the slave mode, the DAPIC is supplied as a slave. The external clock should be connected to the oscillator at pin CLK1/XTAL1 (see Fig.17). 10 pF CLK1/XTAL1 56 R1 100 kΩ C2 XTAL2 59 MLC164 Crystal oscillator supply The power supply for the oscillator is separate from the other supply line. This is to minimize feedback from the ground bounce of the IC to the oscillator. Pin VSSX is the ground supply and VDDX is the positive supply. Fig.16 Master mode. Power supply connection and EMC The SAA7740H has in total 8 positive supply lines (VDD) including VDDX, and 8 ground supply lines (VSS) including VSSX. For correct current distribution all positive supply lines should be connected together on the printed circuit-board. The ground supply lines should also be connected together on the printed circuit-board. handbook, halfpage external clock C1 CLK1/XTAL1 10 pF 30 pF To minimize radiation the IC should be placed on a double-layer printed circuit-board with a large ground plane on one side. The ground supply lines should have a short connection to the ground plane. An LC network in the positive supply lines can be used as a high frequency filter. C2 10 nF 56 max 1 V (p-p) R1 100 kΩ XTAL2 C3 59 MLC165 Test mode connections Pins SCCLK, TSTCLK, TST1, TST2 and TST3 are used to put the IC in the test mode and to test the internal connections. In the application these pins must be connected to ground. 1997 May 30 Fig.17 Slave mode. 23 Philips Semiconductors Product specification Digital Audio Processing IC (DAPIC) SAA7740H PACKAGE OUTLINE QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT319-2 c y X 51 A 33 52 32 ZE Q e E HE A A2 (A 3) A1 θ wM pin 1 index Lp bp L 20 64 detail X 19 1 ZD w M bp e v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp Q v w y mm 3.20 0.25 0.05 2.90 2.65 0.25 0.50 0.35 0.25 0.14 20.1 19.9 14.1 13.9 1 24.2 23.6 18.2 17.6 1.95 1.0 0.6 1.4 1.2 0.2 0.2 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-02-04 SOT319-2 1997 May 30 EUROPEAN PROJECTION 24 o 7 0o Philips Semiconductors Product specification Digital Audio Processing IC (DAPIC) SAA7740H SOLDERING Wave soldering Introduction Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. If wave soldering cannot be avoided, the following conditions must be observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. Reflow soldering Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9397 750 00192). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. 1997 May 30 25 Philips Semiconductors Product specification Digital Audio Processing IC (DAPIC) SAA7740H DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 May 30 26 Philips Semiconductors Product specification Digital Audio Processing IC (DAPIC) SAA7740H NOTES 1997 May 30 27 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 547027/1200/04/pp28 Date of release: 1997 May 30 Document order number: 9397 750 02262