PHILIPS SAA3500H

INTEGRATED CIRCUITS
DATA SHEET
SAA3500H
Digital audio broadcast channel
decoder
Preliminary specification
File under Integrated Circuits, IC01
2000 Jun 14
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
CONTENTS
1
FEATURES
SAA3500H
11
THERMAL CHARACTERISTICS
12
DC CHARACTERISTICS
13
AC CHARACTERISTICS
14
APPLICATION INFORMATION
Clock oscillator
Reset input
Boundary scan test interface
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
QUICK REFERENCE DATA
5
ORDERING INFORMATION
14.1
14.2
14.3
6
BLOCK DIAGRAM
15
PACKAGE OUTLINE
7
PINNING
16
SOLDERING
8
FUNCTIONAL DESCRIPTION
16.1
9
INTERFACE DESCRIPTION
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.7.1
9.7.2
9.7.3
Input interface
Memory interface
Parallel output interface
Serial output interface
Simple full capacity output
RDI output
Microcontroller interface
I2C-bus mode
L3-bus mode
Microcontroller interface registers
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
10
LIMITING VALUES
2000 Jun 14
16.2
16.3
16.4
16.5
2
17
DATA SHEET STATUS
18
DEFINITIONS
19
DISCLAIMERS
20
PURCHASE OF PHILIPS I2C COMPONENTS
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
1
SAA3500H
FEATURES
• Digital Audio Broadcast (DAB) full-capacity demodulator
and decoder
• Supports DAB transmission modes I, II, III and IV
• Integrated Analog-to-Digital Converter (ADC) for
IF input
• Digital mixer with on-chip digital Automatic Frequency
Control (AFC) and Automatic Gain Control (AGC)
2 APPLICATIONS
• Mobile receivers (FM/DAB car radios)
• Detectors for null symbol, DAB mode and transmitter
identification
• Personal Computer add-ons
• On-chip or external synchronization algorithms and
control loops
• Portable radios.
• Test and measurement equipment
• On-chip timing PLL and DCXO
3
• Dynamic DAB multiplex reconfiguration supported
The Philips SAA3500H is a Digital Audio Broadcast (DAB)
channel decoder according to the ETSI specification
ETS 300 401. The SAA3500H is a successor to the Philips
FADIC and SIVIC chip set and provides an IF ADC, digital
mixer, full DAB ensemble demodulation and decoding as
well as time and frequency synchronization functions.
Because of the full-speed Viterbi decoding capacity and a
high-speed receiver data output interface, DAB data
reception is not limited by the SAA3500H channel
decoder.
• Equal and unequal error protection for up to
64 sub-channels
• Fast information channel buffering
• Simple full capacity output
• Receiver data interface
• Serial output for three sub-channels
• I2C-bus or L3-bus control interface.
4
GENERAL DESCRIPTION
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VDD
supply voltage
3.0
3.3
3.6
V
Vi(max)
maximum input voltage
−0.5
−
VDD + 0.5
V
IDD
DC supply current
−
−
180
mA
fclk
clock frequency
−
24576
−
kHz
Tamb
ambient temperature
−40
+25
+85
°C
Tstg
storage temperature
−65
−
+150
°C
5
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA3500H
2000 Jun 14
QFP100
DESCRIPTION
plastic quad flat package; 100 leads (lead length 1.95 mm);
body 14 × 20 × 2.7 mm; high stand-off height
3
VERSION
SOT317-1
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
6
SAA3500H
BLOCK DIAGRAM
BYP
AIF
INP[9:0]
2
ADE
ADC
OUT[7:0]
OCLK
OIQ
OCIR
OEN
99
17
to
8
IQS
39 to 32
27
CHANNEL IMPULSE
29
RESPONSE
PROCESSOR
30
21 20 25 24
19 41
OSCO
4
5
NULL DETECTOR,
TIMEBASE,
DCXO
BOUNDARY
SCAN TEST
FAST FOURIER
TRANSFORMATION
sync
31
DIFFERENTIAL
DEMODULATOR
SYMBOL
SELECT
inhibit
VITERBI
DECODER
ERROR FLAG
DETECT/COUNT
MCI
FIC
BUFFER
SERIAL OUTPUT
55
51
CFIC
RESET
52
54 53
CCLK
CMODE CDATA
97
95
96
93
70
62 to 68, 81 to 91
71 to 78
69
61
FREQUENCY & TIME
DE-INTERLEAVER
CAPACITY UNIT
SELECT
MICROCONTROLLER
INTERFACE
22
49
to
50 47
46
to
44
43 56 58 57 59
SOC SOV[1:3] SFCO
SOD[1:3]
REF
Fig.1 Block diagram.
4
FSO
FSI
TMS
TCK
TDI
TDO
TRST
SAA3500H
metrics
UNEQUAL/EQUAL
ERROR PROTECTION
CONTROL
23
98
AUTOMATIC FREQUENCY
CONTROL PROCESSOR
2000 Jun 14
OSCI
MCLK
SLI
DIGITAL MIXER
AND FILTERS
AD CONVERTER
(8 BIT)
1
ADCLK
AGC
RDC
RDE
RDO
A17
A[17:0]
D[7:0]
RD
WR
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
7
SAA3500H
PINNING
SYMBOL
ADC
PIN
1
TYPE
DESCRIPTION
input
analog-to-digital converter DC input
analog-to-digital converter IF input
AIF
2
input
VSSA
3
ground analog supply ground
ADE
99
input
VDDA
100
INP[0:9]
8 to 17
ADCLK
analog-to-digital converter enable (active LOW)
supply analog voltage supply (+3.3 V)
input
2048 kHz IF or baseband digital parallel input data (8 or 10 bits)
19
output
analog-to-digital clock output 8192 kHz if BYP = HIGH, 4096 kHz if BYP = LOW
IQS
20
input
clock signal indicating I or Q baseband data if BYP = LOW;
signal for swapping I and Q data bytes if BYP = HIGH
BYP
21
input
IF input stage bypass (active LOW)
FSI
22
input
frame sync input (LOW indicates DAB null symbol detection)
FSO
23
output
null detector/frame sync output (LOW indicates DAB null symbol position)
SLI
24
output
AGC synchronization lock indicator (HIGH if synchronized)
AGC
25
output
AGC level comparator output (HIGH if input sample > reference level, else LOW)
OSCI
4
input
oscillator or system clock input, 24576 kHz
OSCO
5
output
oscillator output
MCLK
41
output
master clock output, 24576 kHz
VSS
7, 18,
26, 40,
60, 80
and 94
supply digital supply ground
VDD
6, 28,
42 and
79
supply digital voltage supply (+3.3 V)
TEST
OUT[0:7]
92
input
32 to 39 output
connect to ground for proper operation
baseband or channel impulse response output
OCLK
27
output
output data clock (negative edge indicates new data)
OIQ
29
output
output I or Q select signal if OCIR = HIGH, or frame trigger if OCIR = LOW
OCIR
30
input
output select: baseband if OCIR = HIGH, CIR if OCIR = LOW
OEN
31
input
output enable (active LOW)
CFIC
51
output
microcontroller interface signal indicating Fast Information Channel (FIC) processing
CMODE
52
input
microcontroller interface mode input (only L3-bus)
CDATA
53
I/O
microcontroller interface serial data I2C-bus or L3-bus (5 V tolerant)
CCLK
54
input
microcontroller interface clock input I2C-bus or L3-bus
55
input
RESET
chip reset input (active LOW)
A[17:11]
62 to 68 output
address outputs external RAM
A[10:0]
81 to 91 output
address outputs external RAM
WR
61
output
write data to RAM (active LOW)
RD
69
output
read data from RAM (active LOW)
A17
70
output
address bit 17 inverted for second RAM (128k × 8)
D[0:7]
2000 Jun 14
71 to 78 I/O
data input/output external RAM
5
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
SYMBOL
PIN
TYPE
SOV3
44
output
serial output valid data 3
SOV2
45
output
serial output valid data 2
SOV1
46
output
serial output valid data 1
SOD3
47
output
serial output data 3
SOD2
48
output
serial output data 2
SOD1
49
output
serial output data 1 (from channel decoder)
SOC
50
output
serial output clock (384 kHz continuous)
REF
43
output
receiver error flag [from Viterbi decoder, for Simple Full Capacity Output (SFCO)]
SFCO
56
output
simple full capacity output (direct from Viterbi decoder)
RDC
57
output
receiver data clock (6144 kHz continuous) or SFCO clock (burst)
RDE
58
input
RDI output enable (active LOW)
RDO
59
output
receiver data interface bi-phase output
TDO
93
output
boundary scan test serial output
TCK
95
input
boundary scan test clock input
TDI
96
input
boundary scan test serial input
TMS
97
input
boundary scan test mode select input
TRST
98
input
boundary scan test reset input
2000 Jun 14
DESCRIPTION
6
Philips Semiconductors
Preliminary specification
81 A10
82 A9
83 A8
84 A7
85 A6
86 A5
87 A4
SAA3500H
88 A3
89 A2
90 A1
91 A0
92 TEST
94 VSS
93 TDO
95 TCK
96 TDI
97 TMS
98 TRST
100 VDDA
99 ADE
Digital audio broadcast channel decoder
ADC
1
AIF
2
80 VSS
79 VDD
VSSA
3
78 D0
OSCI
4
77 D1
OSCO
5
76 D2
VDD
6
75 D3
VSS
7
74 D4
INP0
8
73 D5
INP1
9
72 D6
INP2 10
71 D7
INP3 11
70 A17
INP4 12
69 RD
INP5 13
68 A11
INP6 14
67 A12
INP7 15
66 A13
SAA3500H
INP8 16
65 A14
INP9 17
64 A15
VSS 18
63 A16
ADCLK 19
62 A17
IQS 20
61 WR
BYP 21
60 VSS
FSI 22
59 RDO
FSO 23
58 RDE
SLI 24
57 RDC
AGC 25
56 SFCO
VSS 26
OCLK 27
55 RESET
VDD 28
53 CDATA
OIQ 29
52 CMODE
54 CCLK
Fig.2 Pin configuration.
2000 Jun 14
7
SOC 50
SOD1 49
SOD2 48
SOD3 47
SOV1 46
SOV2 45
SOV3 44
REF 43
VDD 42
MCLK 41
VSS 40
OUT7 39
OUT6 38
OUT5 37
OUT4 36
OUT3 35
OUT2 34
OUT1 33
OUT0 32
51 CFIC
OEN 31
OCIR 30
MXXxxx
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
8
The FFT result of the reference symbol is processed by the
synchronization core, which performs two functions:
estimation of the frequency error of the baseband signal,
which is needed to adjust the digital mixer (AFC), and
calculation of the Channel Impulse Response (CIR) to be
used for positioning of the FFT window and the system
clock. All timing and frequency control loops are realized in
the synchronization core and can be influenced from the
control interface.
FUNCTIONAL DESCRIPTION
The 2.048 MHz IF signal is digitized by an 8-bit flash
Analog-to-Digital Converter (ADC), which samples at
8.192 MHz. The required input level is limited to a
peak-to-peak voltage of 2 V. Due to a fast
sample-and-hold circuit sub-sampling is possible, so that
all IF frequencies of N × 8.192 ±2.048 MHz can be used.
If a higher resolution ADC is wanted, an external ADC can
be connected.
The Viterbi decoder is preceded by frequency and time
de-interleaving of the incoming metrics in external RAM, to
distribute burst errors caused by channel fading. Variable
rate decoding is done with 3.072 Mb/s decision speed.
Output bits are re-encoded and compared to
corresponding input bits in order to generate an error flag
signal.
The digital mixer accepts a 2.048 MHz IF signal at its input
and converts it to baseband with In-phase (I) and
Quadrature-phase (Q) components. The mixer frequency
is adjusted on a DAB frame basis with 1 Hz resolution to
prevent performance degradation. The mixer output
signals are digitally filtered and subjected to internal
Automatic Gain Control (AGC) before entering the
subsequent Fast Fourier Transform (FFT) stage.
Sub-channel selection is done on a Capacity Unit (CU)
basis. All standardized Unequal Error Protection (UEP)
puncturing schemes for audio and Equal Error Protection
(EEP) schemes for data are provided. Up to
64 sub-channels can be selected separately, which means
virtually unlimited DAB decoding capabilities.
The output of the digital AGC detectors indicates for each
input sample whether the level is below or above the
reference input level. By means of external filtering and
gain control, the signal can be used to adjust the input
signal level of the analog-to-digital converter (external
AGC).
The output interface provides a full-speed standardized
Receiver Data Interface (RDI) for all sub-channel data.
This allows to extend every DAB receiver with external
decoders for all kind of services. A dedicated interface is
provided for the Philips SAA2502H audio source decoder,
which completes the DAB receiver.
The on-chip null detector operates on the digital baseband
signal and indicates the coarse position of the DAB null
symbol (FSO = LOW), which is used for time base
initialization. The spacing of detected null symbols is used
to detect the DAB transmission mode.
The system clock of 24.576 MHz, can be generated by an
integrated DCXO, which is internally locked to the DAB
signal. The clock is available on the MCLK pin to provide a
synchronous clock to the MPEG decoder and
microcontroller.
The time base counts samples on a symbol and a frame
basis in order to generate the internal control windows for
the FFT and to generate a frame sync signal (FSO) during
the null symbol. Initialization of the time base is determined
by the null detector signal (FSI) and the selected DAB
mode. After time base initialization the SAA3500H will be
in symbol processing mode and the null detector will be
deactivated.
The I2C-bus or L3-bus configurable control interface
provides access to Automatic Frequency Control (AFC),
Channel Impulse Response (CIR), Fast Information
Channel (FIC) and sub-channel selection controls.
The OFDM symbol demodulator applies a real-time FFT
and differential demodulation to the baseband signal. The
output is quantized to 4-bit metrics for the Viterbi decoder.
The position of the FFT window is adjusted on a DAB
frame basis in order to avoid Inter-Symbol Interference
(ISI).
2000 Jun 14
SAA3500H
8
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
9
SAA3500H
INTERFACE DESCRIPTION
9.1
Input interface
The input interface can be used in 3 different modes, depending on the bypass (BYP) and IQ Select (IQS) pins. Digital
input data should be in two’s complement format (optionally: offset binary) and synchronized with the ADCLK output
signal. Input data are read on the rising edge of ADCLK.
Table 1
Input modes
BYP
IQS
DESCRIPTION
0
clk
1
0
digital IF input sampled at 8192 kHz, internal I/Q demodulator
1
1
digital IF input sampled at 8192 kHz, internal I/Q demodulator with I and Q swapped
digital baseband input sampled at 2048 kHz and with I and Q data multiplexed
In case of baseband input the IQ select signal shall indicate whether the current sample is either I or Q data (INP[9:0]).
4096 kHz
ADCLK
INP[9:0]
Q0
I1
Q1
I2
Q2
10 bits
2048 kHz
IQS
Fig.3 Baseband input signals (BYP = LOW).
Digital IF input is, typically, at a frequency of 2048 kHz. It is possible to apply sub-sampling on a N × 8.192 ±2.048 MHz
(N = 1, 2, 3,...,19) IF signal, but care should be taken with the jitter of the crystal clock, which is proportional to N.
ADCLK
8192 kHz
INP[9:0]
10 bits
Fig.4 IF input signals [BYP = HIGH, IQS = LOW (no swap) or HIGH (swap)].
To use the on-chip null detector, pins FSI and FSO shall simply be connected to each other.
When using an external null detector, the FSI input shall indicate the position of the null symbol in the baseband signal
(FSI = LOW). The negative edge may have a maximum delay of 512 samples with respect to an ideal null detector. The
delay compensation can be set via the I2C/L3 interface (register ATCWinControl). The FSI input provides edge jitter
suppression of up to 40 samples starting from the first negative edge. Once the SAA3500H is in symbol processing
mode, the FSI signal is ignored. During the null detection state, the Sync Lock Indicator (SLI) will be continuously LOW.
9.2
Memory interface
An external SRAM memory of either 128 or 256 kbytes is required to store the metrics from the data de-interleaver for
half (432 CUs) or full (864 CUs) decoding capacity, respectively. The upper address line A17 is available both true and
inverted (A17) to allow memory extension without an address decoder. 3.3 V RAMs should be used with either an 8 or
(2 ×) 4-bit data bus and an access time of ≤80 ns. Input data are read on the rising edge of RD, output data shall be
latched on the rising edge of WR.
2000 Jun 14
9
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
A[17:0]
D[7:0]
RD
WR
Fig.5 RAM access.
9.3
Parallel output interface
The digital parallel output interface can be used in 3 different modes depending on the OCIR and OEN select pins.
Output data shall be latched on the falling edge of OCLK.
Table 2 Parallel output modes
X = don’t care.
OCIR OEN
DESCRIPTION
0
0
channel impulse response sampled at 64 kHz, OIQ = frame trigger
1
0
baseband sampled at 2048 kHz and with I and Q data multiplexed
X
1
OUT[7:0], OIQ and OCLK disabled
By means of an external digital-to-analog converter, either the CIR or I/Q data can be displayed on an oscilloscope.
Digital output data is clocked out on the falling edge of the OCLK output signal. In case of baseband output the OIQ signal
indicates, if the current sample is either I or Q data.
4096 kHz
OCLK
OUT[7:0]
Q
I
Q
I
Q
signed
2048 kHz
OIQ
Fig.6 Baseband output signals (OCIR = HIGH, OEN = LOW).
OCLK
64 kHz
OUT[7:0]
unsigned
OIQ
trigger
Fig.7 CIR output signals (OCIR = LOW, OEN = LOW).
2000 Jun 14
10
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
In the CIR output mode the channel impulse response is clocked out in a burst of N (unsigned) samples at 64 kHz each
frame after CIR processing (bit SyncBusy = logic 0). The edges of the frame trigger signal (OIQ) allow to trigger a CIR
display either at the start of the symbol or at the start of the symbol guard. In the latter case the CIR peak for a Gaussian
channel will be at the left of the display.
9.4
Serial output interface
The serial output interface is intended for transferring up to three sub-channels to the source decoder(s) with a total
maximum bit rate of 384 kbit/s. The sub-channels for these outputs should be selected with the appropriate I2C or L3
commands. The output clock is 384 kHz. Each sub-channel has its own serial data and data valid line, but the clock is
common. Serial output data shall be latched on the rising edge of SOC.
SOC
SOD
SOV
Fig.8 DAB3 serial output.
9.5
Simple full capacity output
This interface provides serial access to all the Viterbi decoder output bits without any formatting. Transmission framing
is indicated by the CFIC window, which can also be used to separate the FIC data (CFIC = HIGH) from the Main Service
Channel (MSC) data (CFIC = LOW). The bit CFICMode can be used to signal on CFIC the beginning of the selected
sub-channels (CFICMode = logic 0). The clock is a 3072 kHz burst clock, activated for each new output bit.
Accompanied with the data is the error flag, obtained by re-encoding the Viterbi output bits and comparison with the
corresponding Viterbi decoder input bits (REF = HIGH for error bit).
CFICMode = 0
CFIC
RDC
SFCO
REF
Fig.9 Simple full capacity output (CFICMode = logic 1).
9.6
RDI output
For external use a bi-phase modulated output (RDO) is provided, which carries all the FIC and MSC data, formatted
according to the DAB receiver data interface specification “EN 50255”, which is based on the IEC 60958 digital audio
interface. Optionally, a clock (6144 kHz) and word select signal (48 kHz) can be provided (instead of SFCO signals).
Transmitter Identification Information (TII) is not signalled on this RDI. The FIC however is always signalled, with the
Cyclic Redundancy Check (CRC) performed and the Error Check Field containing the resulting CRC (normally 0).
Selected sub-channels will be directed to the RDI interface in the extended capacity mode (22 bits for MSC), but the
number of RDI frames and the reliability are not signalled (i.e., set to all logic 0s and all logic 1s, respectively).
2000 Jun 14
11
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
RDO
Fig.10 RDI output (normal mode, RDE = LOW).
In case SFCO data output is not desired, a particular ‘RDI plus’ mode can be selected, which provides a continuous
6144 kHz clock on RDC, synchronous to the bi-phase RDI data and accompanied by a fixed word select signal, to allow
RDI source reception without an extra clock recovery circuit. Output data shall be latched on the rising edge of RDC.
RDC
RDO
SFCO
Channel 1 (32 bits)
Channel 2 (32 bits)
Fig.11 RDI output (RDI plus mode, RDE = LOW).
9.7
Microcontroller interface
The microcontroller interface of the SAA3500H operates in one of two distinct modes of operation: I2C-bus or L3-bus.
Mode setting is determined at initialization, as described in Fig.12. On either control bus data are transferred in 8-bit
packets, or bytes.
The interface uses three signals and the function in the L3-bus mode or I2C-bus mode is indicated in Table 3.
Table 3
Control bus modes
SIGNAL
I2C-BUS MODE
L3-BUS MODE
DIRECTION
DESCRIPTION
CDATA
L3DATA
SDA
input/output
microcontroller interface serial data
CCLK
L3CLK
SCL
input
microcontroller interface bit clock
CMODE
L3MODE
none
input
microcontroller interface mode select
During a hard reset of the device, the microcontroller interface mode is determined. As a consequence, the interface
cannot be used while the reset signal is asserted. Mandatory action must be taken for correct microcontroller interface
start-up at a hard reset, as explained in Fig.12.
RESET
I2C-bus mode
CMODE
L3-bus mode
CCLK
phase 1
phase 2
phase 3
Fig.12 Microcontroller interface initialization procedure.
2000 Jun 14
12
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
In phase 1, the level of the CMODE signal determines the microcontroller interface mode, while reset is asserted.
CMODE = HIGH defines I2C-bus mode, CMODE = LOW defines L3-bus mode. No transfers can be performed, as CCLK
must be HIGH.
In phase 2, which is for L3-bus mode of operation only, it is mandatory to take CMODE HIGH, then LOW again after reset
has been de-asserted, to correctly initialize the interface unit. This must occur before any L3-bus transfer (even to or from
other devices) is performed. CCLK shall remain HIGH during this phase.
In phase 3, the first transfer can be performed on the microcontroller interface.
Any deviation from these steps may result in undefined behaviour of the microcontroller interface, even with the
possibility of disturbing transfers to other devices connected to the control bus.
At a hardware reset, all writeable data items are forced to their default values.
The microcontroller interface provides access to all blocks, which generate or need control information. Selections on
the SAA3500H are at the sub-channel level, the required sub-channel parameters should be obtained via the Multiplex
Configuration Information (MCI), which is part of the FIC.
The CFIC window from the SAA3500H indicates FIC decoding. FIC data from the I2C/L3 interface will be invalid, if
CFIC = HIGH. It is therefore recommended to connect CFIC to a microcontroller interrupt input pin. With regard to the
real-time processing requirements, it is highly recommended to use a 16-bit microcontroller.
I2C-BUS MODE
9.7.1
The implemented I2C-bus interface is of the 400 kbit/s, 7-bit address type. The CDATA output driver is of the ‘open drain’
type in order to be compliant with the I2C-bus specification. The device address is as follows:
Table 4
I2C-bus device address
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
1
1
0
1
0
1
1
R/W
Bit 7 to bit 1 comprise the 7-bit I2C-bus slave address, while bit 0 indicates the transfer direction of data and acknowledge
bits as follows:
Table 5
Read and write operation to the microcontroller in I2C-bus mode
FUNCTION
R/W
REMARK
0
data from microcontroller to SAA3500H
all acknowledge generated by SAA3500H
1
data from SAA3500H to microcontroller
acknowledge for data generated by microcontroller
Fundamentals of the I2C-bus interface protocol are shown in Fig.13.
2000 Jun 14
13
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
CCLK
1
2
7
8
9
SAA3500H
1
2
7
8
CDATA
9
ACK
ACK
address transfer
data transfer
MSB
MSB
R/W
LSB
S
P
START
condition
STOP
condition
Fig.13 I2C-bus data transfer example.
For full details of the I2C-bus interface specification, please, refer to the I2C-bus specification
(http://www.semiconductors.com/handbook/various_38.html), which is also available on request.
9.7.2
L3-BUS MODE
The L3-bus device address is composed as follows:
Table 6
L3-bus device address
BIT 7
BIT 6
0
1
BIT 5
1
BIT 4
BIT 3
0
1
BIT 2
BIT 1
BIT 0
1
DOM1(1)
DOM0(1)
Note
1. The ‘Data Operation Mode’ bits DOM1 and DOM0 define the current sub-mode of the microcontroller interface until
the next time a device address is received (see Table 7).
Table 7
Read and write operation to the microcontroller in L3-bus mode
DOM1
DOM0
FUNCTION
REMARK
0
0
data from microcontroller to SAA3500H
general purpose data transfer
0
1
data from SAA3500H to microcontroller
general purpose data transfer
1
0
control from microcontroller to SAA3500H
register selection for data transfer
1
1
status from SAA3500H to microcontroller
short device status message
Fundamentals of the L3-bus interface protocol are shown in Fig.14.
2000 Jun 14
14
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
CCLK
1
CMODE
2
7
8
SAA3500H
1
LSB
7
8
data mode
addressing mode
CDATA
2
MSB
LSB
MSB
Fig.14 L3-bus command transfer example.
For full details of the L3-bus interface specification, please, refer to the SAA2502H data sheet (order number
9397 750 03068 or at http://www.semiconductors.com/products).
9.7.3
MICROCONTROLLER INTERFACE REGISTERS
Communication between the microcontroller and the SAA3500H is by addressing registers and writing or reading data.
All addresses and register contents are in hexadecimal notation.
The following registers are available for the writing of data:
Table 8
Writeable registers
ADDRESS
(HEX)
NAME
DESCRIPTION
SETTING AFTER RESET
(HEX)
00
Control
control
1F
01
Configuration
configuration
FF
10
CIFCount
CIF count and occurrence change flag
20
CurSubChSel
current sub-channel selection
00 00 00 00
21
NextSubChSel
next sub-channel selection
00 00 00 00
30
SOD1
select sub-channel for serial output SOD1
40
31
SOD2
select sub-channel for serial output SOD2
40
32
SOD3
select sub-channel for serial output SOD3
40
40
AGCExternal
setting of thresholds for external AGC
61 0C
41
AGCInternal
settings of the internal AGC
D0 49
42
AGCFixed
internal AGC switch off and fixed gain setting
50
NullDetMargin
null detector margin
51
TIIControl
TII main/sub identifier
60
MixerFreqInput
digital mixer frequency control input
62
CarrierShift
carrier shift by n carrier positions
00
63
AFCGain
AFC loop gain
10
70
ATCWinControl
ATC window control input or FFT window position and null
detector delay compensation
96
71
CIRThreshold
CIR detector thresholds, edge and range
73
ATCGains
ATC loops gains; clock I and P gains and window gain
2000 Jun 14
00 00 00
00
40
00 00
15
80 00 00
02 02
02 04 20
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
The following registers are available for the reading of data:
Table 9
Readable registers
ADDRESS
(HEX)
NAME
DESCRIPTION
BYTES TO READ
00
Status
internal processing status
1
10
FICErrCount
FIC error count per frame
2
20 to 2B
FICData
FIC data inclusive CRC result
32
51
TIIOutput
TII complex phase values
6
60
AFCLoopOutput AFC loop output for digital mixer frequency control
3
61
CarrierDev
AFC carrier deviation detector
2
70
ATCWinOutput
ATC window loop output for FFT window position
1
71
ATCDetector
ATC CIR detector output
3
72
ATCClockOutput ATC clock loop output for external VCXO
1
76
CIRPower
2
power of CIR response
A description of how to use the individual registers is given in a separate application note.
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
−0.5
+6
V
input voltage
−0.5
VDD + 0.5
V
IDD
supply current
−
200
mA
Ii
input current
−10
+10
mA
Io
output current
−10
+10
mA
Ptot
total power dissipation
−
650
mW
Tstg
storage temperature
−65
+150
°C
Tamb
operating ambient temperature
−40
+85
°C
Ves
electrostatic handling voltage
note 2
−300
+300
V
note 3
−3000
+3000
V
VDD
DC supply voltage
Vi
note 1
Notes
1. All supply connections must be made to the same external power supply unit.
2. Machine model: equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor (‘0 Ω’ is actually
0.75 µH + 10 Ω).
3. Human body model: equivalent to discharging a 100 pF capacitor through a 1500 Ω series resistor.
11 THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
2000 Jun 14
PARAMETER
CONDITIONS
thermal resistance from junction to ambient in free air
16
VALUE
UNIT
60
K/W
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
12 DC CHARACTERISTICS
VDD = 3.0 to 3.6 V; Tamb = −40 to +85 °C; all voltages referenced to ground (VSS); unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD(tot)
total DC supply voltage
IDD(tot)
note 1
3.0
3.3
3.6
V
total DC supply current
−
−
180
mA
total power dissipation
−
−
650
mW
2.0
−
−
V
Dissipation
Ptot
Inputs
CMOS LEVEL INPUT (INP[9:0], FSI, CCLK AND TCK)
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
|ILI|
input leakage current
Ci
input capacitance
−
−
0.8
V
VI = 0 or VI = VDD −
−
1
µA
−
5
−
pF
V
CMOS LEVEL INPUT, PULL-UP (BYP, CMODE, IQS, OCIR, OEN, RDE, TDI, TMS AND TRST)
VIH
HIGH-level input voltage
2.0
−
−
VIL
LOW-level input voltage
−
−
0.8
V
Rpu(VDD)(int)
internal pull-up resistor to VDD
16
33
78
kΩ
Ci
input capacitance
−
5
−
pF
CMOS LEVEL INPUT, HYSTERESIS, PULL-UP (RESET)
VIH(hys)
HIGH-level hysteresis input, rising edge
1.4
−
1.9
V
VIL(hys)
LOW-level hysteresis input, falling edge
0.9
−
1.45
V
Vhys
hysteresis voltage
0.4
−
0.7
V
Rpu(VDD)(int)
internal pull-up resistor to VDD
16
33
78
kΩ
Ci
input capacitance
−
5
−
pF
Inputs/outputs
CMOS LEVEL INPUT, HYSTERESIS, OPEN DRAIN OUTPUT (CDATA)
VIH(hys)
HIGH-level hysteresis input, rising edge
1.4
−
1.9
V
VIL(hys)
LOW-level hysteresis input, falling edge
0.9
−
1.45
V
Vhys
hysteresis voltage
0.4
−
0.7
V
VOL
LOW-level output voltage
−
−
0.4
V
2.0
−
−
V
CMOS LEVEL INPUT, 1.5 mA
VIH
OUTPUT STAGE
ILOAD = 3 mA
(D[7:0])
HIGH-level input voltage
VIL
LOW-level input voltage
−
−
0.8
V
|ILI|
input leakage current
VI = 0 or VI = VDD −
−
1
µA
VOH
HIGH-level output voltage
ILOAD = −1.5 mA
2.4
−
−
V
VOL
LOW-level output voltage
ILOAD = 1.5 mA
−
−
0.4
V
2000 Jun 14
17
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SYMBOL
PARAMETER
SAA3500H
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Outputs
CMOS LEVEL, 1.5 mA
AND WR)
OUTPUT STAGE
(A[17:0], A17, ADCLK, AGC, FSO, OCLK, OIQ, RD, SLI, SOD[1:3], SOV[1:3]
VOH
HIGH-level output voltage
ILOAD = −1.5 mA
2.4
−
−
V
VOL
LOW-level output voltage
ILOAD = 1.5 mA
−
−
0.4
V
CLOAD
output load capacitance
−
−
30
pF
CMOS LEVEL, 1.5 mA 3-STATE OUTPUT STAGE, (OUT[7:0])
VOH
HIGH-level output voltage
ILOAD = −1.5 mA
2.4
−
−
V
VOL
LOW-level output voltage
ILOAD = 1.5 mA
−
−
0.4
V
|ILO|
output leakage current
inactive mode;
VO = 0 or
VO = VDD
−
−
1
µA
CLOAD
output load capacitance
−
−
30
pF
CMOS LEVEL, 3 mA
OUTPUT STAGE
(CFIC, MCLK, RDC, RDO, REF, SFCO, SOC AND TDO)
VOH
HIGH-level output voltage
ILOAD = −3 mA
2.4
−
−
V
VOL
LOW-level output voltage
ILOAD = 3 mA
−
−
0.4
V
CLOAD
output load capacitance
−
−
50
pF
Note
1. All supply connections must be made to the same external power supply unit.
13 AC CHARACTERISTICS
VDD = 3.0 to 3.6 V; Tamb = 25 °C; all voltages referenced to ground (VSS); unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Oscillator input (OSC)
fi(OSC)
input frequency
δOSC
input clock duty factor
note 1
−
24576
−
kHz
40
−
60
%
60 × T
−
−
ns
Reset input (RESET)
tCL,RESET
reset LOW duration
note 2
Input interface (ADCLK, BYP, INP[9:0] and IQS)
BASEBAND INPUT (BYP = LOW); see Fig.15
Tcy,ADCLK
ADCLK cycle time
−
244
−
ns
tCL,ADCLK
ADCLK LOW time
−
122
−
ns
tCH,ADCLK
ADCLK HIGH time
−
122
−
ns
th,INP
INP[9:0] hold time
5
−
−
ns
th,IQS
IQS hold time
−
−
80
ns
2000 Jun 14
18
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SYMBOL
PARAMETER
SAA3500H
CONDITIONS
MIN.
TYP.
MAX.
UNIT
IF INPUT (BYP = HIGH); see Fig.16
Tcy,ADCLK
ADCLK cycle time
−
122
−
ns
tCL,ADCLK
ADCLK LOW time
−
80
−
ns
tCH,ADCLK
ADCLK HIGH time
−
42
−
ns
th,INP
INP[9:0] hold time
5
−
−
ns
td,INP
INP[9:0] delay time
−
−
25
ns
Memory interface (A17, A[17:0], D[7:0], RD and WR); see Figs 17 and 18
Tcy,A
address cycle time
−
326
−
ns
tCL,RD
RD LOW time
−
163
−
ns
td,RD
RD delay time
−
40
−
ns
th,RD
RD hold time
−
0
−
ns
tCL,WR
WR LOW time
−
163
−
ns
td,WR
WR delay time
0
40
−
ns
td,D
data delay time
−
0
−
ns
th,D
data hold time
−
−
5
ns
Parallel output interface (OCIR, OCLK, OEN, OIQ and OUT[9:0])
BASEBAND OUTPUT (OCIR = HIGH); see Fig.19
Tcy,OCLK
OCLK cycle time
−
244
−
ns
tCL,OCLK
OCLK LOW time
−
122
−
ns
tCH,OCLK
OCLK HIGH time
−
122
−
ns
tsu,OUT
OUT[7:0] set-up time
−
15
−
ns
tsu,OIQ
OIQ set-up time
−
17
−
ns
CIR OUTPUT (OCIR = LOW); see Fig.20
Tcy,OCLK
OCLK cycle time
−
15.6
−
µs
tCL,OCLK
OCLK LOW time
−
8.3
−
µs
tCH,OCLK
OCLK HIGH time
−
7.3
−
µs
tsu,OUT
OUT[7:0] set-up time
−
0
−
ns
tsu,OIQ
OIQ set-up time
−
0
−
ns
Serial output interface (SOC, SOD[3:1] and SOV[3:1]); see Fig.21
Tcy,SOC
SOC cycle time
−
2.6
−
µs
tCL,SOC
SOC LOW time
−
1.3
−
µs
tCH,SOC
SOC HIGH time
−
1.3
−
µs
th,SOD
SOD hold time
−
0
−
ns
tsu,SOV
SOV set-up time
−
4
−
ns
th,SOV
SOV hold time
−
2
−
ns
2000 Jun 14
19
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SYMBOL
PARAMETER
SAA3500H
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Simple full capacity output interface (CFIC, RDC, REF and SFCO); see Fig.22
tCH,CFIC
tSH,CFIC
CFIC HIGH time
CFIC strobe HIGH time
DAB mode I
−
3.738
−
ms
DAB mode II
−
0.935
−
ms
DAB mode III
−
1.246
−
ms
DAB mode IV
−
1.869
−
ms
bit CFICMode = 0 −
75
−
ns
bit CFICMode = 1 −
0
−
ns
tsu,CFIC
CFIC set-up time
−
165
−
ns
th,CFIC
CFIC hold time
−
80
−
ns
Tcy,RDC
RDC cycle time
325
−
−
ns
tCH,RDC
RDC HIGH time
250
−
−
ns
tCL,RDC
RDC LOW time
−
75
−
ns
tsu,SFCO
SFCO set-up time
−
5
−
ns
tsu,REF
REF set-up time
−
165
−
ns
th,REF
REF hold time
−
−160
−
ns
RDI output interface (RDC, RDE, RDO and SFCO)
NORMAL MODE; see Fig.23
tONE
ONE time
−
163
−
ns
tZERO
ZERO time
−
326
−
ns
RDI PLUS MODE; see Fig.24
Tcy,RDC
RDC cycle time
−
163
−
ns
tCH,RDC
RDC HIGH time
−
86
−
ns
tCL,RDC
RDC LOW time
−
77
−
ns
Tcy,SFCO
SFCO cycle time
−
20.8
−
µs
tCH,SFCO
SFCO HIGH time
−
10.4
−
µs
tCL,SFCO
SFCO LOW time
−
10.4
−
µs
tsu,SFCO
SFCO set-up time
−
4
−
ns
th,SFCO
SFCO hold time
−
0
−
ns
Microcontroller interface
INITIALIZATION PROCEDURE; see Fig.25
tCL,RESET
RESET LOW time
note 2
60 × T
−
−
ns
td,RES-MOD
delay time from RESET to CMODE
note 2
10 × T
−
−
ns
tCH,CMODE
CMODE HIGH time
note 2
10 × T
−
−
ns
td,MOD-CLK
delay time from CMODE to first CCLK
note 2
10 × T
−
−
ns
2000 Jun 14
20
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SYMBOL
PARAMETER
SAA3500H
CONDITIONS
MIN.
TYP.
MAX.
UNIT
L3-BUS MICROCONTROLLER TO SLAVE DEVICE; see Figs 26 and 28
tcL
L3CLK LOW time
note 2
T + 10
−
−
ns
tcH
L3CLK HIGH time
note 2
T + 10
−
−
ns
td1
L3MODE set-up time before first L3CLK
LOW
10
−
−
ns
th1
L3DATA hold time after L3CLK HIGH
10
−
−
ns
th2
L3MODE hold time after last L3CLK HIGH
15
−
−
ns
tsu
L3DATA set-up time before L3CLK HIGH
note 2
T + 10
−
−
ns
tL
L3MODE LOW time
note 2
T + 10
−
−
ns
0
−
20
ns
−
−
20
ns
−
−
2T + 30
ns
0
−
20
ns
T
−
−
ns
L3-BUS SLAVE DEVICE TO MICROCONTROLLER; see Fig.27
td2
L3MODE HIGH to L3DATA enabled time
td3
L3MODE HIGH to L3DATA stable time
td4
L3CLK HIGH to L3DATA stable time
td5
L3MODE LOW to L3DATA disabled time
th3
L3DATA hold time after L3CLK HIGH
I2C-BUS INPUTS/OUTPUT
note 2
note 2
(CDATA AND CCLK)
tf,I2C
output fall time
−
−
250
ns
fCCLK
CCLK clock frequency
−
−
400
kHz
Notes
1. In a real application, the clock frequency may vary in a range of ±50 ppm due to timing synchronization.
2. T = 4 × OSC cycle time, i.e., T = 163 ns at fosc = 24.576 MHz.
Tcy,ADCLK
tCH,ADCLK
tCL,ADCLK
ADCLK
INP[9:0]
th,INP
th,IQS
IQS
Fig.15 Baseband input timing (BYP = LOW).
Tcy,ADCLK
tCH,ADCLK
tCL,ADCLK
ADCLK
INP[9:0]
th,INP
td,INP
Fig.16 IF input timing [BYP = HIGH, IQS = LOW (no swap) or HIGH (swap)].
2000 Jun 14
21
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
Tcy,A
Tcy,A
A[17:0]
A[17:0]
D[7:0]
D[7:0]
td,WR
tCL,WR
th,D
td,RD
WR
Fig.17 RAM access read timing.
Fig.18 RAM access write timing.
Tcy,OCLK
Tcy,OCLK
tCL,OCLK
tCH,OCLK
tCL,OCLK
tCH,OCLK
OCLK
OCLK
OUT[7:0]
OUT[7:0]
tsu,OIQ
tsu,OUT
tsu,OIQ
tsu,OUT
OIQ
OIQ
Fig.19 Baseband output timing (OCIR = HIGH,
OEN = LOW).
Fig.20 CIR output timing (OCIR = LOW,
OEN = LOW).
Tcy,SOC
tCL,SOC
tCH,SOC
SOC
th,SOD
SOD
SOV
tsu,SOV
th,SOV
Fig.21 DAB3 serial output timing.
2000 Jun 14
th,D
td,D
tCL,RD
RD
22
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
tCH,CFIC
tsu,CFIC
CFIC
th,CFIC
tSH,CFIC
Tcy,RDC
tCH,RDC
tCL,RDC
RDC
SFCO
tsu,REF
tsu,SFCO
th,REF
REF
Fig.22 Simple full capacity output timing.
tONE
tZERO
RDO
Fig.23 RDI output timing (normal mode, RDE = LOW).
Tcy,RDC
tCL,RDC
tCH,RDC
RDC
RDO
tsu,SFCO
th,SFCO
tCL,SFCO
SFCO
tCH,SFCO
Tcy,SFCO
Fig.24 RDI output timing (RDI plus mode, RDE = LOW).
2000 Jun 14
23
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
tCL,RESET
SAA3500H
tCH,CMODE
RESET
td,RES-MOD
td,MOD-CLK
CMODE
CCLK
Fig.25 Microcontroller interface initialization timing.
t d1
handbook, full pagewidth
t h2
L3MODE
t cL
t cH
L3CLK
L3DATA
t h1
t su
MGB507
Fig.26 Timing of L3-bus addressing mode.
t d1
handbook, full pagewidth
t h2
L3MODE
t cL
t cH
L3CLK
t su
L3DATA
microcontroller
to IC
t h1
L3DATA
IC to
microcontroller
t d2
t d3
t h3
t d5
t d4
MGB508
Fig.27 Timing of L3-bus data transfer mode.
2000 Jun 14
24
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
tL
handbook, full pagewidth
L3MODE
t d1
t h2
L3CLK
td5
t d2
L3DATA
IC to
microcontroller
MGB509
Fig.28 Timing of L3-bus halt mode.
14 APPLICATION INFORMATION
A suggestion for an application block diagram is shown in Fig.29.
RAM
(256k × 8)
A
SAW
FILTER
TUNER
BAND III/L
RDI
D
SAA3500H
AGC
DAB3
SAA2502H
I2S
L/R
SPDIF
24.576 MHz
MICROCONTROLLER
I2C or L3-BUS
Fig.29 Typical application diagram.
14.1
Clock oscillator
14.2
To perform automatic fine tuning of the clock signal, the
microcontroller reads data from the SAA3500H and
controls an external (VCXO) crystal oscillator. The
following requirements should be met by that oscillator:
The reset signal is active LOW and should have a
minimum duration of 60 clock cycles.
14.3
VALUE
UNIT
Frequency
24576
kHz
Pull range
±50
ppm
Operating temperature
−40 to +85
°C
Frequency drift with temperature
≤±20
ppm
Tolerance and ageing
≤±10
ppm
2000 Jun 14
Boundary scan test interface
For normal operation set TRST LOW, TCK LOW or HIGH,
TDI and TMS not connected or HIGH. The boundary scan
chain has a length of 84 and a 5-bit instruction code.
Table 10 VCXO specification
PARAMETER
Reset input
25
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
15 PACKAGE OUTLINE
QFP100: plastic quad flat package;
100 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height
SOT317-1
c
y
X
80
A
51
81
50
ZE
e
E HE
A
A2
(A 3)
A1
θ
wM
pin 1 index
Lp
bp
L
31
100
detail X
30
1
wM
bp
e
ZD
v M A
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
3.3
0.36
0.10
2.87
2.57
0.25
0.40
0.25
0.25
0.13
20.1
19.9
14.1
13.9
0.65
24.2
23.6
18.2
17.6
1.95
1.0
0.6
0.2
0.15
0.1
Z D (1) Z E (1)
0.8
0.4
1.0
0.6
θ
o
7
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT317-1
2000 Jun 14
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
97-08-01
99-12-27
MO-112
26
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
16 SOLDERING
16.1
Introduction to soldering surface mount
packages
• For packages with leads on two sides and a pitch (e):
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
16.2
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
16.3
16.4
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
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16.5
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Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, SQFP
not suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not
PLCC(3),
SO, SOJ
suitable
suitable(2)
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended(3)(4)
suitable
SSOP, TSSOP, VSO
not recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
17 DATA SHEET STATUS
DATA SHEET STATUS
PRODUCT
STATUS
DEFINITIONS (1)
Objective specification
Development
This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification
Qualification
This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
18 DEFINITIONS
19 DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
20 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2000 Jun 14
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Preliminary specification
Digital audio broadcast channel decoder
NOTES
2000 Jun 14
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Preliminary specification
Digital audio broadcast channel decoder
NOTES
2000 Jun 14
31
SAA3500H
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Internet: http://www.semiconductors.philips.com
SCA 69
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Printed in The Netherlands
753503/01/pp32
Date of release: 2000
Jun 14
Document order number:
9397 750 07187