INTEGRATED CIRCUITS DATA SHEET TDA8783 40 Msps, 10-bit analog-to-digital interface for CCD cameras Product specification Supersedes data of 1999 Jun 25 2002 Oct 23 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras TDA8783 FEATURES APPLICATIONS • Correlated Double Sampling (CDS), AGC, 10-bit ADC and reference regulator included, adjustable bandwidth (CDS and AGC) • CCD camera systems. GENERAL DESCRIPTION • Fully programmable via a 3-wire serial interface The TDA8783 is a 10-bit analog-to-digital interface for CCD cameras. The device includes a correlated double sampling circuit, AGC and a low-power 10-bit Analog-to-Digital Converter (ADC) together with its reference voltage regulator. • Sampling frequency up to 40 MHz • AGC gain from 4.5 to 34.5 dB (in 0.1 dB steps) • CDS programmable bandwidth from 4 to 120 MHz • AGC programmable bandwidth from 4 to 54 MHz • Standby mode available for each block for power saving applications 20 mW (typ.) The AGC and CDS have a bandwidth circuit controlled by on-chip DACs via a serial interface. • 6 dB fixed gain analog output for analog iris control A 10-bit DAC controls the ADC input clamp level. • 8-bit and 10-bit DAC included for analog settings An additional 8-bit DAC is provided for additional system controls; its output voltage range is 1.4 V (p-p) which is available at pin OFDOUT. • Low power consumption of only 483 mW (typ.) • 5 V operation and 2.5 to 5.25 V operation for the digital outputs • TTL compatible inputs, TTL and CMOS compatible outputs. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION TDA8783HL LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2 2002 Oct 23 2 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras TDA8783 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCCA analog supply voltage 4.75 5 5.25 V VCCD digital supply voltage 4.75 5 5.25 V VCCO digital outputs supply voltage 2.5 3 5.25 V ICCA analog supply current − 78 95 mA ICCD digital supply current − 18 20 mA ICCO digital outputs supply current − 1 − mA fCLK = 27 MHz; CL = 20 pF; ramp input ADCres ADC resolution − 10 − bits Vi(CDS)(p-p) CDS input voltage (peak-to-peak value) − 400 1200 mV GCDS CDS output amplifier gain − 6 − dB fCLK(max) maximum clock frequency 40 − − MHz AGCdyn AGC dynamic range − 30 − dB Ntot(rms) total noise from CDS input to ADC output (RMS value) − 0.125 − LSB Ptot total power consumption − 483 − mW 2002 Oct 23 fcut(CDS) = 120 MHz; fcut(AGC) = 54 MHz gain = 4.5 dB; fcut(CDS) = 120 MHz; fcut(AGC) = 40 MHz 3 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras TDA8783 BLOCK DIAGRAM handbook, full pagewidth IND 47 INP AGND3 VCCA3 SHD 46 48 45 CLPOB CLPDM SHP 44 43 CLK 42 1 DGND2 VCCD2 40 39 41 OE 38 VCCO 37 36 TRACKAND-HOLD CLOCK GENERATOR TRACKAND-HOLD 35 TRACKAND-HOLD CPCDS AGND1 34 8 CLAMP 5 33 4-BIT DAC CUT-OFF CLAMP ref1 32 31 AMPOUT AGND4 AGCOUT 4 OUTPUTS BUFFER 10-BIT ADC 6 dB 2 30 TDA8783 7 1 29 AGC 28 VCCA1 AGND5 ADCIN Vref CLPADC 6 1 4-BIT DAC CUT-OFF 27 9-BIT DAC 9 10 12 11 26 25 + 8-BIT DAC 10-BIT DAC 13 DACOUT 15 16 VCCA2 AGND2 17 18 19 23 AGND6 VRT VRB DEC1 STDBY Fig.1 Block diagram. 2002 Oct 23 4 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DGND1 OFDOUT SERIAL INTERFACE REGULATOR 14 3 OGND 22 SEN 21 20 24 SDATA VCCD1 SCLK MGM491 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras TDA8783 PINNING SYMBOL PIN DESCRIPTION CLPOB 1 clamp pulse input at optical black AGND4 2 analog ground 4 OFDOUT 3 analog output of the additional 8-bit control DAC (controlled via the serial interface) AMPOUT 4 CDS amplifier output (fixed gain = 6 dB) AGND1 5 analog ground 1 VCCA1 6 analog supply voltage 1 AGCOUT 7 AGC amplifier signal output CPCDS 8 clamp storage capacitor pin AGND5 9 analog ground 5 ADCIN 10 ADC analog signal input from AGCOUT via a short circuit CLPADC 11 clamp control input for ADC analog input signal clamp (used with a capacitor from Vref to ground) Vref 12 ADC input clamp reference voltage (normally connected to pin VRB or DACOUT, or connected to ground via a capacitor) DACOUT 13 DAC output for ADC clamp level AGND2 14 analog ground 2 VCCA2 15 analog supply voltage 2 VRB 16 ADC reference voltage (BOTTOM) code 0 VRT 17 ADC reference voltage (TOP) code 1023 DEC1 18 decoupling 1 (decoupled to ground via a capacitor) AGND6 19 analog ground 6 SDATA 20 serial data input for the 4 control DACs (9-bit DAC for AGC gain, 8-bit DAC for frequency cut-off; additional 8-bit DAC for OFD output voltage; 10-bit DAC for ADC clamp level and the standby mode per block and edge pulse control); see Fig.3, Fig.4 and Table 1 SCLK 21 serial clock input for the control DACs and their serial interface; see Fig.3, Fig.4 and Table 1 SEN 22 enable input for the serial interface shift register (active when SEN = logic 0); see Fig.3, Fig.4 and Table 1 STDBY 23 standby control (active HIGH); all the output bits are logic 0 when standby is enabled VCCD1 24 digital supply voltage 1 DGND1 25 digital ground 1 D0 26 ADC digital output 0 (LSB) D1 27 ADC digital output 1 D2 28 ADC digital output 2 D3 29 ADC digital output 3 D4 30 ADC digital output 4 D5 31 ADC digital output 5 D6 32 ADC digital output 6 D7 33 ADC digital output 7 D8 34 ADC digital output 8 D9 35 ADC digital output 9 (MSB) OGND 36 digital output ground 2002 Oct 23 5 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras SYMBOL PIN VCCO 37 TDA8783 DESCRIPTION digital output supply voltage 43 pre-set sample-and-hold pulse input SHD 44 data sample-and-hold pulse input VCCA3 45 analog supply voltage 3 INP 46 pre-set input signal from CCD IND 47 data input signal from CCD AGND3 48 analog ground 3 37 VCCO SHP 38 OE clamp pulse input at dummy pixel 39 VCCD2 ADC clock input 42 40 DGND2 41 CLPDM 41 CLK CLK 42 CLPDM digital ground 2 43 SHP 40 44 SHD DGND2 45 VCCA3 digital supply voltage 2 46 INP output enable (active LOW: digital outputs active; active HIGH: digital outputs high impedance) 39 47 IND 38 VCCD2 48 AGND3 OE CLPOB 1 36 OGND AGND4 2 35 D9 OFDOUT 3 34 D8 AMPOUT 4 33 D7 AGND1 5 32 D6 VCCA1 6 AGCOUT 7 30 D4 CPCDS 8 29 D3 AGND5 31 D5 TDA8783HL 9 28 D2 ADCIN 10 27 D1 CLPADC 11 26 D0 Vref 12 Fig.2 Pin configuration. 2002 Oct 23 6 VCCD1 24 STDBY 23 SEN 22 SCLK 21 SDATA 20 AGND6 19 VRT 17 DEC1 18 VRB 16 VCCA2 15 AGND2 14 DACOUT 13 25 DGND1 MGM492 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras TDA8783 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCCA analog supply voltage note 1 −0.3 +7.0 V VCCD digital supply voltage note 1 −0.3 +7.0 V VCCO output stages supply voltage note 1 −0.3 +7.0 V ∆VCC supply voltage difference between VCCA and VCCD −1.0 +1.0 V between VCCA and VCCO −1.0 +4.0 V −1.0 +4.0 V Vi input voltage referenced to AGND −0.3 +7.0 V VCLK(p-p) AC input voltage for switching (peak-to-peak value) referenced to DGND − VCCD V Io output current − 10 mA Tstg storage temperature −55 +150 °C Tamb ambient temperature −20 +75 °C Tj junction temperature − 150 °C between VCCD and VCCO Note 1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 and +7.0 V provided that the supply voltage difference ∆VCC remains as indicated. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 2002 Oct 23 PARAMETER CONDITIONS thermal resistance from junction to ambient in free air 7 VALUE UNIT 76 K/W Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras TDA8783 CHARACTERISTICS VCCA = VCCD = 5 V; VCCO = 3 V; fCLK = 27 MHz; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VCCA analog supply voltage 4.75 5 5.25 V VCCD digital supply voltage 4.75 5 5.25 V VCCO digital outputs supply voltage 2.5 3 5.25 V ICCA analog supply current − 78 95 mA ICCD digital supply current − 18 20 mA ICCO digital outputs supply current − 1 − mA CL = 20 pF on all data outputs; ramp input Digital inputs CLOCK INPUT: CLK (REFERENCED TO DGND) VIL LOW-level input voltage 0 − 0.8 V VIH HIGH-level input voltage 2.0 − VCCD V IIL LOW-level input current VCLK = 0.8 V −1 − +1 µA IIH HIGH-level input current VCLK = 2.0 V − − 20 µA Zi input impedance fCLK = 27 MHz − 46 − kΩ Ci input capacitance fCLK = 27 MHz − 1 − pF INPUTS: SHP AND SHD VIL LOW-level input voltage 0 − 0.8 V VIH HIGH-level input voltage 2.0 − VCCD V IIL LOW-level input current VIL = 0.8 V − −6 − µA IIH HIGH-level input current VIH = 2.0 V − 0 − µA 0 − 0.8 V INPUTS: SEN, SCLK, SDATA, OE, STDBY, CLPDM, CLPOB AND CLPADC VIL LOW-level input voltage VIH HIGH-level input voltage 2.0 − VCCD V Ii input current −2 − +2 µA Correlated Double Sampling (CDS); note 1 Vi(CDS)(p-p) CDS input amplitude pin 47 (peak-to-peak value) − 400 1200 mV ICPCDS, IINP, IIND input current pins 8, 46 and 47 −2 − +2 µA tCDS(min) CDS control pulses minimum active time 8 − − ns thd1 hold time INP compared to control see Fig.5 pulse SHP − 1 − ns 2002 Oct 23 fi(CDS1,2) = fCLK(pix); Vi(CDS)(p-p) = 600 mV black-to-white transition in 1 pixel (±1 LSB typ.); fcut(CDS) = 120 MHz; fcut(AGC) = 54 MHz 8 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras SYMBOL TDA8783 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT − 1 − ns 0000 − 8 − ns 0001 − 21 − ns 0010 − 42 − ns 0011 − 52 − ns 0100 − 82 − ns 0111 − 94 − ns 1000 − 195 − ns 1011 − 219 − ns 1111 − 280 − ns thd2 hold time of IND compared to control pulse SHD see Fig.5 tset(CDS) CDS settling time see Fig.12; control DAC 4 bits input code; AGC gain = 0 dB; fcut(AGC) = 54 MHz; Vi(CDS) = 600 mV (p-p) black-to-white transition in 1 pixel (±1 LSB typ.) Amplifier outputs GAMPOUT output amplifier gain − 6 − dB ZAMPOUT output amplifier impedance − 300 − Ω VAMPOUT(p-p) output amplifier dynamic voltage (peak-to-peak value) − 2.4 − V VAMPOUT(bl) output amplifier black level voltage − 1.5 − V VAGCOUT(p-p) AGC output amplifier dynamic voltage level (peak-to-peak value) − 2000 − mV VAGCOUT(bl) AGC output amplifier black level voltage Vref connected to DACOUT − Vref − V ZAGCOUT AGC output amplifier output impedance at 10 kHz − 5 − Ω IAGCOUT AGC output static drive current static − − 1 mA GAGC(min) minimum gain of AGC circuit AGC DAC input code = 00 (9-bit control); see Fig.7 − 4.5 − dB GAGC(max) maximum gain of AGC circuit AGC DAC input code ≥ 319 (9-bit control); see Fig.7 − 34.5 − dB fcut(AGC) cut-off frequency AGC 4-bit control DAC input code = 00 − 54 − MHz input code = 15 − 4 − MHz other codes see Fig.13 2002 Oct 23 9 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras SYMBOL PARAMETER TDA8783 CONDITIONS MIN. TYP. MAX. UNIT Clamps gm(ADC) ADC clamp transconductance at clamp level − 7 − mS gm(CDS) CDS clamp transconductance at clamp level − 1.5 − mS Analog-to-Digital Converter (ADC) fCLK(max) maximum clock frequency 40 − − MHz tCPH clock pulse width HIGH 12 − − ns tCPL clock pulse width LOW SRCLK clock input slew rate (rising and falling edge) Vi(ADC)(p-p) 12 − − ns 0.5 − − V/ns ADC input voltage level (peak-to-peak value) − 2 − V VRB ADC reference voltage output code 0 − 1.5 − V VRT ADC reference voltage output code 1023 − 3.5 − V IADCIN ADC input current −2 − +120 µA INL integral non-linearity ramp input − ±0.6 ±1.5 LSB DNL differential non-linearity ramp input − ±0.2 ±0.75 LSB td(s) sampling delay time − − 5 ns 30 − ns 10% to 90% Total chain characteristics (CDS + AGC + ADC) td delay between SHD and CLK 50% at rising edges − CLK and SHD: transition full scale code 0 to 1023; fcut(CDS) = 120 MHz; fcut(AGC) = 54 MHz; Vi(CDS) = 600 mV Ntot(rms) total output noise (RMS value) fcut(CDS) = 120 MHz; fcut(AGC) = 40 MHz; note 2 Voffset(fl-d) maximum offset between CCD floating level and CCD dark pixel level Vn(i)(eq)(rms) equivalent input noise voltage (RMS value) GAGC = 4.5 dB − 0.125 − LSB GAGC = 34.5 dB − 1.6 − LSB −200 − +200 mV AGC gain = 34.5 dB − 125 − µV AGC gain = 4.5 dB − 150 − µV Digital-to-Analog Converter (OFDOUT) VOFDOUT(p-p) additional 8-bit control DAC (OFD) output voltage (peak-to-peak value) − 1.4 − V VOFDOUT(0) DC output voltage for code 0 − 2.3 − V − 3.7 − V VOFDOUT(255) DC output voltage for code 255 2002 Oct 23 10 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras SYMBOL TDA8783 PARAMETER ZOFDOUT additional 8-bit control DAC (OFD) output impedance IOFDOUT OFD output current drive CONDITIONS MIN. TYP. MAX. UNIT − 2000 − Ω − − 50 µA − 1 − V code 0 − 1.5 − V code 1023 − 2.5 − V − − 250 Ω static ADC clamp control DAC (see Fig.8) VDACOUT(p-p) ADC clamp 10-bit control DAC output voltage (peak-to-peak value) VDACOUT DC output voltage ZDACOUT ADC clamp control DAC output impedance IDACOUT DAC output current drive static − − 50 µA OFELOOP maximum offset error of DAC + ADC clamp loop code 0 − ±5 − LSB code 1023 − ±5 − LSB VCCO V Digital outputs (fCLK = 40 MHz; CL = 20 pF); note 3 VOH HIGH-level output voltage IOH = −1 mA VCCO − 0.5 − VOL LOW-level output voltage IOL = 1 mA 0 − 0.5 V 0 V < Vo < VCCO −20 − +20 µA 8 − − ns CL = 20 pF; VCCO = 5 V − 17 23 ns CL = 10 pF; VCCO = 5 V − 15 21 ns CL = 20 pF; VCCO = 3 V − 20 29 ns CL = 10 pF; VCCO = 3 V − 17 25 ns CL = 20 pF; VCCO = 2.5 V − 22 33 ns CL = 10 pF; VCCO = 2.5 V − 18 28 ns 5 − − MHz IOZ output current in 3-state mode to(h) output hold time to(d) output delay time Serial interface fSCLK(max) maximum frequency of serial interface Notes 1. More information about CDS related signals is available in the following figures: The clamp current for pin CPCDS is given in Fig. 9, clamp current for pins IND and INP in Fig 10 and for clamp current for pin Vref in Fig 11. The CDS output amplitude is shown in Fig. 14 2. Noise measurement at ADC outputs: the coupling capacitor at the input is connected to ground, so that only the noise contribution of the front-end is evaluated. The front-end operates at 18 Mpix with a line of 1024 pixels. The first 40 are used to run CLPOB and the last 40 to run CLPDM. Data at the ADC outputs is measured during the other pixels. The differences between the types of codes statistic is then computed; the result is the noise. No quantization noise is taken into account as no signal is input. Figure15 gives noise figure graphs with signal input. 3. Depending on operating pixel frequency, the output voltage and capacitance must be determined according to the output delay timings (to(d)), see Fig.5. 2002 Oct 23 11 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras handbook, full pagewidth TDA8783 SDATA SHIFT REGISTER D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 A0 A1 A2 SCLK LSB MSB 10 LATCH SELECTION SEN 8 (D7 to D0) 9 (D8 to D0) 8 (D7 to D0) 7 (D6 to D0) 10 (D9 to D0) OFD LATCHES AGC GAIN LATCHES FREQUENCY LATCHES PARTIAL STANDBY AND EDGE CLAMP REFERENCE LATCHES 8-bit DAC AGC control frequency control CDS and AGC standby control or edge clocks 10-bit DAC MGM515 Fig.3 Serial interface block diagram. tsu2 handbook, full pagewidth thd4 MSB SDATA A2 A1 A0 D9 D8 D7 LSB D6 D5 D4 D3 D2 D1 D0 SCLK SEN MGE373 tsu1 thd3 tsu3 tsu1 = tsu2 = tsu3 = 4 ns (min.); thd3 = thd4 = 4 ns (min.). Fig.4 Loading sequence of control DACs input data via the serial interface. 2002 Oct 23 12 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras Table 1 TDA8783 Serial interface programming ADDRESS BITS DATA BITS D9 to D0 A2 A1 A0 0 0 0 OFD output control (D7 to D0). 0 0 1 Cut-off frequency of CDS and AGC. Only the 4 LSBs (D3 to D0) are used for CDS. D4 to D7 are used for AGC. D8 and D9 should be set to logic 0. 0 1 0 AGC gain control (D8 to D0). 0 1 1 Partial standby controls for power consumption optimization. Only the 4 LSBs (D3 to D0) are used. Edge control for pulses SHP, SHD, CLAMP and clock ADC: D0 = 1: CDS + AGC in standby; ICCA + ICCD = 35 mA D1 = 1: OFD DAC in standby; ICCA + ICCD = 95 mA D2 = 1: 6 dB amplifier (output on AMPOUT pin) in standby; ICCA + ICCD = 95.5 mA D3 = 1: SHP and SHD activated with falling edge (for positive pulse) D4 = 1: CLPDM, CLPOB and CLPADC activated on HIGH level; note 1 D5 = 0: CLKADC activated with falling edge D6 must be set to logic 0. 1 0 0 Clamp reference DAC (D9 to D0). Note 1. When CLPADC is HIGH (D4 = 1: serial interface), the ADC input is clamped to voltage level Vref. Vref is connected to ground via a capacitor. Table 2 Standby selection STDBY 2002 Oct 23 DATA BITS D9 to D0 ICCA + ICCD (TYP.) 1 LOW 4 mA 0 active 96 mA 13 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras TDA8783 handbook, full pagewidth IND SHP N+1 N N+2 N+3 tCDS 1.4 V tn(IN; SHP) SHD 1.4 V td tn(IN; SHD) tCPH CLK t d(s) 1.4 V to(d) N ADCIN to(h) 90% DATA N−3 N−2 N−1 N 10% MGR395 Fig.5 Pixel frequency timing diagram. 2002 Oct 23 14 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras TDA8783 1 pixel handbook, full pagewidth AGCOUT VIDEO OPTICAL BLACK 1 pixel HORIZONTAL FLYBLACK CLPDM CLPADC WINDOW DUMMY VIDEO CLPDM CLPADC WINDOW CLPOB (active HIGH) CLPOB WINDOW CLPDM (active HIGH) (1) CLPADC (active HIGH) (1) MGR396 (1) When dummy pixels are not available. Fig.6 Line frequency timing diagram. 2002 Oct 23 15 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras TDA8783 MGM507 handbook, halfpage 34.5 GAGC (dB) 4.5 0 511 319 AGC control DAC input code Fig.7 AGC gain as a function of DAC input code. MGM508 handbook, full pagewidth 2.5 3.7 ADC CLAMP DAC voltage output (V) OFD DAC voltage output (V) 2.3 1.5 0 1023 ADC CLAMP control DAC input code 0 255 OFD control DAC input code Fig.8 DAC voltage output as a function of DAC input code. 2002 Oct 23 16 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras TDA8783 handbook,I halfpage (µA) +100 0 2.00 V (V) −100 200 mV MGR397 Fig.9 Typical clamp current for pin CPCDS. handbook,I halfpage (µA) +300 0 2.85 V (V) −300 400 mV MGR398 Fig.10 Typical clamp current for pins IND and INP. handbook,I halfpage (µA) +200 0 Vref V (V) −200 400 mV MGR399 Fig.11 Typical clamp current for pin Vref. 2002 Oct 23 17 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras TDA8783 MGR441 160 handbook, full pagewidth 300 tset fcut (MHz) (ns) 250 120 (2) (3) 200 (4) 80 150 (1) 100 40 50 0 0 1 2 3 4 5 6 7 8 9 A (1) fcut. (2) tset (10 bits accuracy). (3) tset (9 bits accuracy). (4) tset (8 bits accuracy). Fig.12 CDS settling time and bandwidth. 2002 Oct 23 18 B C D E 4-bit control DAC input code F 0 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras TDA8783 MGR401 60 handbook, full pagewidth fcut (MHz) 40 20 0 0 1 2 3 4 5 6 7 8 9 A B C D E 4-bit control DAC input code F Fig.13 AGC bandwidth. MGR442 1.6 handbook, full pagewidth (1) Vo(CDS)(p-p) (2) (V) 1.2 (3) (4) (5) 0.8 (6) 0.4 0 0 (1) tset(CDS) = 12 ns (2) tset(CDS) = 10 ns 0.2 0.4 (3) tset(CDS) = 8 ns (4) tset(CDS) = 7 ns 0.6 0.8 (5) tset(CDS) = 6 ns (6) tset(CDS) = 5 ns Fig.14 CDS output. 2002 Oct 23 19 1.0 1.2 1.4 Vi(CDS)(p-p) (V) 1.6 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras TDA8783 MGR443 3 handbook, full pagewidth Ntot(rms) (LSB) (1) 2 (2) (3) (4) 1 (5) (6) 0 00 40 80 C0 100 code 13F (4.5) (10.5) (16.5) (22.5) (28.5) GAGC (dB) (34.5) (1) (2) (3) (4) fpix = 27 MHz; control DAC = 00H; fcut(CDS) = 120 MHz; fcut(AGC) = 54 MHz. fpix = 18 MHz; control DAC = 10H; fcut(CDS) = 120 MHz; fcut(AGC) = 40 MHz. fpix = 10 MHz; control DAC = 31H; fcut(CDS) = 80 MHz; fcut(AGC) = 30 MHz. fpix = 5 MHz; control DAC = 43H; fcut(CDS) = 35 MHz; fcut(AGC) = 12 MHz. (5) fpix = 1 MHz; control DAC = F8H; fcut(CDS) = 6 MHz; fcut(AGC) = 4 MHz. (6) fpix = 375 kHz; control DAC = FFH; fcut(CDS) = 4 MHz; fcut(AGC) = 4 MHz. Fig.15 Output noise (RMS value). 2002 Oct 23 20 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras TDA8783 APPLICATION INFORMATION 5.0 V CCD 5.0 V (3) (3) (3) OE DGND2 VCCD2 CLK CLPDM SHP SHD VCCA3 from timing generator INP AGND3 IND 220 nF 2.5 to 5.25 V VCCO handbook, full pagewidth 48 47 46 45 44 43 42 41 40 39 38 37 CLPOB AGND4 OFDOUT AMPOUT AGND1 (3) 5.0 V VCCA1 AGCOUT 1 µF CPSDS AGND5 ADCIN 1 µF CLPADC Vref 1 36 2 35 3 34 4 33 5 32 6 31 TDA8783 7 30 8 29 9 28 10 27 11 26 12 25 OGND D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DGND1 STDBY VCCD1 SEN SCLK SDATA DEC1 AGND6 VRT VRB VCCA2 AGND2 DACOUT 13 14 15 16 17 18 19 20 21 22 23 24 (2) (1) 100 nF 2.2 nF serial interface (3) 5.0 V 5.0 V (3) 1 nF 1 nF MGM504 Depending on the application, the following connections must be made: (1) The clamp level of the signal input at ADCIN can be tuned from code 00 to code 511 in 0.5 LSB steps of ADC via the serial interface (clamp ADC activated). (2) Clamp ADC not activated, direct connection from DACOUT to Vref. (3) All supply pins must be decoupled with 100 nF capacitors as close as possible to the device. Fig.16 Application diagram. 2002 Oct 23 21 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras TDA8783 Power and grounding recommendations In a two-ground system, in order to minimize the noise from package and die parasitics, the following recommendations must be implemented: Care must be taken to minimize noise when designing a printed-circuit board for applications such as PC cameras, surveillance cameras, camcorders and digital still cameras. • The ground pin associated with the digital outputs must be connected to the digital ground plane and special care should be taken to avoid feedthrough in the analog ground plane. The analog and digital ground planes must be connected with an inductor as close as possible to the IC package, in order to have the same DC voltage on the ground planes. For the front-end integrated circuit, the basic rules of printed-circuit board design and implementation of analog components (such as classical operational amplifiers) must be taken into account, particularly with respect to power and ground connections. • The digital output pins and their associated lines should be shielded by the digital ground plane, which can be used as return path for the digital signals. The connections between CCD interface and CDS input should be as short as possible and a ground ring protection around these connections can be beneficial. Decoupling capacitors are necessary on all supply pins as shown in Fig.16. Separate analog and digital supplies provide the best performance. If it is not possible to do this on the board, then decouple the analog supply pins effectively from the digital supply pins. The decoupling capacitors must be placed as close as possible to the IC package. 2002 Oct 23 22 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras TDA8783 PACKAGE OUTLINE LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M pin 1 index θ bp Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 7.1 6.9 0.5 9.15 8.85 9.15 8.85 1.0 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) θ 0.95 0.55 7 0o 0.95 0.55 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT313-2 136E05 MS-026 2002 Oct 23 EIAJ EUROPEAN PROJECTION ISSUE DATE 99-12-27 00-01-19 23 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras TDA8783 SOLDERING If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C for small/thin packages. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. 2002 Oct 23 24 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras TDA8783 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE(1) WAVE BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable(3) HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS not PLCC(4), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(2) suitable suitable suitable not recommended(4)(5) suitable not recommended(6) suitable Notes 1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2002 Oct 23 25 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras TDA8783 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2002 Oct 23 26 Philips Semiconductors Product specification 40 Msps, 10-bit analog-to-digital interface for CCD cameras TDA8783 NOTES 2002 Oct 23 27 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA74 © Koninklijke Philips Electronics N.V. 2002 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753504/03/pp28 Date of release: 2002 Oct 23 Document order number: 9397 750 10176