DISCRETE SEMICONDUCTORS DATA SHEET PHC2300 Complementary enhancement mode MOS transistors Product specification Supersedes data of 1997 Jun 19 File under Discrete Semiconductors, SC13b 1997 Oct 24 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors FEATURES PHC2300 PINNING - SOT96-1 (SO8) • High-speed switching PIN • No secondary breakdown. SYMBOL DESCRIPTION 1 s1 source 1 2 g1 gate 1 APPLICATIONS 3 s2 source 2 • Universal line interface in telephone sets 4 g2 gate 2 • Relay, high-speed and line transformer drivers. 5 d2 drain 2 6 d2 drain 2 DESCRIPTION 7 d1 drain 1 One N-channel and one P-channel enhancement mode MOS transistor in an 8-pin plastic SOT96-1 (SO8) package. 8 d1 drain 1 d1 d1 handbook, halfpage CAUTION 8 5 The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. 1 4 MAM118 s1 d2 d2 g1 s2 g2 Fig.1 Simplified outline and symbol. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Per FET VDS drain-source voltage (DC) N-channel − 300 V P-channel − −300 V − ±20 V VGS gate-source voltage (DC) VGSth gate-source threshold voltage ID RDSon Ptot 1997 Oct 24 V N-channel VDS = VGS; ID = 1 mA 0.8 2 V P-channel VDS = VGS ; ID = −1 mA −0.8 −2 V N-channel − 340 mA P-channel − −235 mA drain current (DC) Ts = 80 °C drain-source on-state resistance N-channel VGS = 10 V; ID = 170 mA − 8 Ω P-channel VGS = −10 V; ID = −115 mA − 17 Ω Ts = 80 °C − 1.6 W total power dissipation 2 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC2300 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Per FET VDS drain-source voltage (DC) N-channel − 300 V P-channel − −300 V − ±20 V N-channel − 340 mA P-channel − −235 mA − 1.4 A VGS gate-source voltage (DC) ID drain current (DC) IDM peak drain current Ts = 80 °C; note 1 note 2 N-channel − −0.9 A Ts = 80 °C; note 3 − 1.6 W Tamb = 25 °C; note 4 − 1.8 W Tamb = 25 °C; note 5 − 0.9 W Tamb = 25 °C; note 6 − 1.2 W P-channel Ptot total power dissipation Tstg storage temperature −55 +150 °C Tj operating junction temperature −55 +150 °C Notes 1. Ts is the temperature at the soldering point of the drain leads. 2. Pulse width and duty cycle limited by maximum junction temperature. 3. Maximum permissible dissipation per MOS transistor. (So both devices may be loaded up to 1.6 W at the same time). 4. Maximum permissible dissipation per MOS transistor. Value based on a printed-circuit board with an Rth a-tp (ambient to tie-point) of 27.5 K/W. 5. Maximum permissible dissipation per MOS transistor. Value based on a printed-circuit board with an Rth a-tp (ambient to tie-point) of 90 K/W. 6. Maximum permissible dissipation if only one MOS transistor dissipates. Value based on a printed-circuit board with an Rth a-tp (ambient to tie-point) of 90 K/W. 1997 Oct 24 3 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC2300 MDA235 2 MDA240 10 handbook, halfpage handbook, halfpage Ptot ID (A) (W) 1.6 1 (1) 1.2 10−1 0.8 tp δ= T P 10−2 DC 0.4 t tp 10−3 0 0 40 80 120 Ts (°C) T 160 10 1 102 VDS (V) δ = 0.01; Ts = 80 °C. (1) RDSon limitation. Fig.2 Power derating curve. Fig.3 SOAR; N-channel. MGL245 −10 handbook, halfpage ID (A) −1 (1) −10−1 tp δ= T P −10−2 DC t tp T −10−3 −1 −10 −102 VDS (V) −103 δ = 0.01; Ts = 80 °C. (1) RDSon limitation. Fig.4 SOAR; P-channel. 1997 Oct 24 4 103 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC2300 THERMAL CHARACTERISTICS SYMBOL PARAMETER VALUE UNIT 43 K/W thermal resistance from junction to soldering point Rth j-s MDA244 102 handbook, full pagewidth (1) (2) Rth js (K/W) (3) (4) 10 (5) (6) (7) (8) 1 δ= P (9) tp T (10) t tp T 10−1 10−6 10−5 10−4 10−3 (1) δ = 1.00. (2) δ = 0.75. (3) δ = 0.5. (4) δ = 0.33. (6) δ = 0.1. (7) δ = 0.05. (8) δ = 0.02. (9) δ = 0.01. Fig.5 10−2 10−1 1 tp (s) (5) δ = 0.2. (10) δ = 0. Transient thermal resistance from junction to soldering point as a function of pulse time for N- and P-channels; typical values. CHARACTERISTICS Tj = 25 °C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Per FET V(BR)DSS VGSth IDSS 1997 Oct 24 drain-source breakdown voltage N-channel VGS = 0; ID = 10 µA 300 − − V P-channel VGS = 0; ID = −10 µA −300 − − V gate-source threshold voltage N-channel VGS = VDS ; ID = 1 mA 0.8 − 2 V P-channel VGS = VDS ; ID = −1 mA −0.8 − −2 V N-channel VGS = 0; VDS = 240 V − − 100 nA P-channel VGS = 0; VDS = −240 V − − −100 nA drain-source leakage current 5 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors SYMBOL IGSS RDSon Ciss Coss Crss QG QGS QGD PARAMETER PHC2300 MIN. TYP. MAX. UNIT N-channel − − ±100 nA P-channel − − ±100 nA gate leakage current CONDITIONS VGS = ±20 V; VDS = 0 drain-source on-state resistance N-channel VGS = 10 V; ID = 170 mA − − 8 Ω P-channel VGS = −10 V; ID = − 115 mA − − 17 Ω N-channel VGS = 0; VDS = 50 V; f = 1 MHz − 57 − pF P-channel VGS = 0; VDS = −50 V; f = 1 MHz − 45 − pF N-channel VGS = 0; VDS = 50 V; f = 1 MHz − 15 − pF P-channel VGS = 0; VDS = −50 V; f = 1 MHz − 15 − pF N-channel VGS = 0; VDS = 50 V; f = 1 MHz − 2.6 − pF P-channel VGS = 0; VDS = −50 V; f = 1 MHz − 3 − pF N-channel VGS = 10 V; VDS = 50 V; ID = 170 mA − 2097 − pC P-channel VGS = −10 V; VDS = −50 V; ID = −115 mA − 2137 − pC input capacitance output capacitance reverse transfer capacitance total gate charge gate-source charge N-channel VGS = 10 V; VDS = 50 V; ID = 170 mA − 75 − pC P-channel VGS = −10 V; VDS = −50 V; ID = −115 mA − 68 − pC gate-drain charge N-channel VGS = 10 V; VDS = 50 V; ID = 170 mA − 527 − pC P-channel VGS = −10 V; VDS = −50 V; ID = −115 mA − 674 − pC Switching times ton toff 1997 Oct 24 turn-on time N-channel VGS = 0 to 10 V; VDD = 50 V; ID = 170 mA − 2.5 10 ns P-channel VGS = 0 to −10 V; VDD = −50 V; ID = −115 mA − 4 10 ns N-channel VGS = 10 to 0 V; VDD = 50 V; ID = 170 mA − 17 30 ns P-channel VGS = −10 to 0 V; VDD = −50 V; ID = −115 mA − 25 35 ns turn-off time 6 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors handbook, full pagewidth PHC2300 VDD 90 % Vin RL 10 % 0 Vout 90 % Vout Vin 10 % 0 td(off) td(on) tf MAM274 tr ton toff Fig.6 Switching times test circuit with input and output waveforms; N-channel. 0 handbook, full pagewidth −VDD 10 % Vin 90 % RL Vout 0 10 % 10 % Vout Vin 90 % 90 % td(off) td(on) tr ton tf toff MGD391 Fig.7 Switching times test circuit with input and output waveforms; P-channel. 1997 Oct 24 7 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC2300 MRC237 1.2 ID (A) MBH441 −800 handbook, halfpage handbook, halfpage VGS = 10 V P = 1.0 W 1 VGS = −10 V ID (mA) 5.0 V 4.0 V 0.8 3.5 V 0.6 3.0 V −600 −4.5 V −4.0 V −400 −3.5 V −3.0 V 0.4 2.5 V 0.2 0 −200 −2.5 V 2.0 V 0 4 8 VDS (V) −2.0 V 0 12 0 −2 −4 −6 Tamb = 25 °C; tp = 80 µs; δ = 0. Tamb = 25 °C; tp = 80 µs; δ = 0. Fig.8 Fig.9 Output characteristics; N-channel typical values. MRC243 1 −10 −12 VDS (V) Output characteristics; P-channel typical values. MBH440 −800 handbook, halfpage ID −8 handbook, halfpage ID (mA) (A) 0.8 −600 0.6 −400 0.4 0.2 0 −200 0 2 4 6 8 10 VGS (V) 0 0 −2 −4 −6 −8 −10 VGS (V) VDS = 10 V; Tamb = 25 °C; tp = 80 µs; δ = 0. VDS = −10 V; Tamb = 25 °C; tp = 80 µs; δ = 0. Fig.10 Transfer characteristic; N-channel typical values. Fig.11 Transfer characteristic; P-channel typical values. 1997 Oct 24 8 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC2300 MDA237 160 MDA236 160 handbook, halfpage handbook, halfpage C (pF) C (pF) 120 120 80 80 Ciss Ciss 40 40 Coss Coss Crss Crss 0 0 0 5 10 15 20 25 VDS (V) −5 0 −10 −15 −20 −25 VDS (V) f = 1 MHz; Tamb = 25 °C. f = 1 MHz; Tamb = 25 °C. Fig.12 Capacitance as a function of drain-source voltage; N-channel typical values. Fig.13 Capacitance as a function of drain-source voltage; P-channel typical values. MDA242 12 VGS 50 handbook, halfpage V GS V DS (V ) MDA243 12 50 handbook, halfpage VDS ( V) ( V) 10 (V) 10 40 40 35 35 8 8 30 6 30 6 25 (1 ) 25 (1) (2) (2) 20 4 20 4 15 10 2 15 10 2 5 5 0 0 Q G ( p C) QG (pC) VDD = 50 V; ID = 170 mA; Tamb = 25 °C. (1) VDS. (2) VGS. VDD = −50 V; ID = −115 mA; Tamb = 25 °C. (1) VDS. (2) VGS. Fig.14 Gate-source voltage and drain-source voltage as a function of total gate charge; N-channel typical values. 1997 Oct 24 1639 1746 1853 1960 2067 1319 1426 1533 1105 1212 545 664 779 890 999 0 83 193 308 426 0 1955 2063 1634 1741 1849 1311 1418 1526 1097 1203 549 664 773 881 989 0 87 195 311 430 0 Fig.15 Gate-source voltage and drain-source voltage as a function of total gate charge; P-channel typical values. 9 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC2300 MDA238 0.5 handbook, halfpage ISD (A) 0.4 (A) −0.4 0.3 −0.3 0.2 −0.2 0.1 −0.1 0 0 MDA239 −0.5 ISD handbook, halfpage 0.2 0.4 0.6 0 0.8 1 VSD (V) −0.4 0 −0.8 VSD (V) −1.2 VGD = 0. VGD = 0. Fig.16 Source-drain current as a function of source-drain diode forward voltage; N-channel typical values. Fig.17 Source-drain current as a function of source-drain diode forward voltage; P-channel typical values. MDA234 102 handbook, halfpage RDSon (Ω) (1) (2) (3) (4) (5) RDSon (Ω) 10 1 MDA233 102 handbook, halfpage (1) (2) (3) (4) (5) 10 0 2 4 VDS ≥ ID × RDSon; Tamb = 25 °C; tp = 300 µs; δ = 0. (1) ID = 10 mA. (2) ID = 20 mA. 6 8 1 10 VGS (V) −2 −4 VDS ≥ ID × RDSon; Tamb = 25 °C; tp = 300 µs; δ = 0. (3) ID = 50 mA. (4) ID = 100 mA. (5) ID = 200 mA. (1) ID = −10 mA. (2) ID = −20 mA. Fig.18 Drain-source on-state resistance as a function of gate-source voltage; N-channel typical values. 1997 Oct 24 0 −6 −8 −10 VGS (V) (3) ID = −50 mA. (4) ID = −100 mA. (5) ID = −200 mA. Fig.19 Drain-source on-state resistance as a function of gate-source voltage; P-channel typical values. 10 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC2300 MBH438 MRC236 1.25 1.4 handbook, halfpage handbook, halfpage k k 1 1.2 0.75 1.0 0.5 0.8 0.25 0 –50 0 50 100 0.6 −75 150 Tj ( o C) −25 25 75 125 175 Tj (°C) V GSth at T j k = ------------------------------------V GSth at 25°C V GSth at T j k = ------------------------------------V GSth at 25°C VGSth at VDS = VGS; ID = 1 mA. VGSth at VDS = VGS; ID = −1 mA. Fig.20 Temperature coefficient of gate-source threshold voltage as a function of junction temperature; N-channel, typical values. Fig.21 Temperature coefficient of gate-source threshold voltage as function of junction temperature; P-channel typical values. 1997 Oct 24 11 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC2300 MBH439 MRC235 2.5 2.4 handbook, halfpage handbook, halfpage k k (1) 2 2.0 (2) (1) 1.5 1.6 1 1.2 0.5 0.8 0 –50 0 50 100 o Tj ( C) 0.4 −75 150 −25 25 75 (2) 125 175 Tj (°C) R DSon at T j k = ---------------------------------------R DSon at 25 °C R DSon at T j k = ---------------------------------------R DSon at 25 °C (1) RDSon at VGS = 10 V; ID = 250 mA. (2) RDSon at VGS = 2.4 V; ID = 20 mA. (1) RDSon at VGS = -4.5 V; ID = −80 mA. (2) RDSon at VGS = -2.8 V; ID = −50 mA. Fig.22 Temperature coefficient of drain-source on-resistance as a function of junction temperature; N-channel typical values. Fig.23 Temperature coefficient of drain-source on-resistance as a function of junction temperature; P-channel typical values. 1997 Oct 24 12 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC2300 PACKAGE OUTLINE SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.244 0.039 0.028 0.050 0.041 0.228 0.016 0.024 inches 0.010 0.057 0.069 0.004 0.049 0.01 0.01 0.028 0.004 0.012 θ Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03S MS-012AA 1997 Oct 24 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-05-22 13 o 8 0o Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC2300 DEFINITIONS Data Sheet Status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1997 Oct 24 14 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC2300 NOTES 1997 Oct 24 15 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 137107/1200/02/pp16 Date of release: 1997 Oct 24 Document order number: 9397 750 02783