19-1291; Rev 0; 9/97 IF Undersampler The MAX1005 provides a high level of signal integrity from a low power budget. It operates from a single power supply, or from separate analog and digital supplies with independent voltages ranging from +2.7V to +5.5V. The MAX1005 can operate with an unregulated analog supply of 5.5V and a regulated digital supply down to 2.7V. This flexible power-supply operation saves additional power in complex digital systems. The MAX1005 has three operating modes: transmit (DAC active), receive (ADC active), and shutdown (ADC and DAC inactive). In shutdown mode, the total supply current drops below 1µA. The device requires only 2.4µs to wake up from shutdown mode. The MAX1005 is ideal for hand-held, as well as base-station applications. It is available in a tiny 16-pin QSOP package specified for operation over both the commercial and extended temperature ranges. ________________________Applications ____________________________Features ♦ Differential-Input, 5-Bit ADC ♦ Differential-Output, 7-Bit DAC ♦ 15Msps Min Conversion Rate ♦ 25MHz -1dB Full-Power Bandwidth ♦ 44dB SFDR for ADC 39dB at 10.7MHz SFDR (Imaged) for DAC ♦ Internal Voltage Reference ♦ Parallel Logic Interface ♦ Single-Supply Operation (+2.7V to +5.5V) ♦ 0.1µA Low-Power Shutdown Mode ______________Ordering Information PART MAX1005CEE MAX1005EEE TEMP. RANGE PIN-PACKAGE 0°C to +70°C -40°C to +85°C 16 QSOP 16 QSOP __________________Pin Configuration TOP VIEW VCCD 1 16 CLK DGND 2 15 D0 RXEN 3 14 D1 PWT1900 AIO+ 4 PHS/P AIO- 5 12 D3 Wireless Loops TXEN 6 11 D4 PCS/N AGND 7 10 D5 VCCA 8 9 MAX1005 13 D2 D6 QSOP Functional Diagram appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. MAX1005 _______________General Description The MAX1005 is a combined digitizer and reconstruction integrated circuit designed to work in systems that demodulate and modulate communications signals. It integrates IF undersampling and signal synthesis functions into a single, low-power circuit. Its analog-todigital converter (ADC) is used to directly sample or undersample a downconverted RF signal, while its digital-to-analog converter (DAC) recreates the IF subcarrier and transmission data. The MAX1005’s ADC is ideal for undersampling applications, due to the analog input amplifier’s wide (15MHz) bandwidth. The DAC has very low glitch energy, which minimizes the transmission of unwanted spurious signals. An on-chip reference provides for low-noise ADC and DAC conversions. MAX1005 IF Undersampler ABSOLUTE MAXIMUM RATINGS VCCA to AGND ........................................................-0.3V, +6.0V VCCD to DGND ........................................................-0.3V, +6.0V VCCA to VCCD ...................................................................±6.3V Digital I/O Pins (D0–D6, CLK, RXEN, TXEN) to DGND .................................-0.3V to (VCCD + 0.3V) or 6.0V (whichever is smaller) Analog I/O Pins (AIO+, AIO-) to AGND................................(VCCA - 1.5V) to (VCCA + 0.3V) AGND to DGND........................................................-0.3V, +0.3V Power Dissipation (TA = +70°C) QSOP (derate 5.90mW/°C above 70°C) ......................470mW Operating Temperature Ranges MAX1005CEE .....................................................0°C to +70°C MAX1005EEE...................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, <10sec)...........................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCCA = VCCD = 3.0V, fCLK = 15MHz, RL = ∞, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TRANSMIT DAC DC ACCURACY (Note 1) Resolution N 7 Bits Integral Nonlinearity INL ±0.2 ±1 LSB Differential Nonlinearity DNL ±0.2 ±1 LSB Offset Error Transmit Full-Scale Output Voltage VOUT 736 800 28 39 ±1 LSB 864 mVp-p TRANSMIT DAC DYNAMIC PERFORMANCE (TA = +25°C) (Note 2) Spurious-Free Dynamic Range SFDR (Note 3) Total Harmonic Distortion plus Noise THD+N (Note 4) Wakeup Time Exiting Shutdown VCCA = VCCD = 2.7V to 5.5V VCCA = VCCD = 3.0V -28 0.7 (Note 5) DAC Latency (Notes 6, 7) PSR dBc 39 tWAKE Clock Feedthrough Power-Supply Rejection VCCA = VCCD = 3.0V 2.4 -50 µs dBc 0.5 VCC_ (A or D or both) = 3.0V ±100mVp-p at 100kHz dBc CLK period 67 dB ±0.2 LSB ±0.2 LSB TRANSMIT ADC DC ACCURACY (Note 8) Resolution N Integral Nonlinearity INL Differential Nonlinearity DNL Offset Error Full-Scale Input Range 5 AIO+ = AIO- Bits ±2 VIN 368 LSB 400 432 VCCA = VCCD = 3.0V -42 -24 VCCA = VCCD = 2.7V to 5.5V -42 mV RECEIVE ADC DYNAMIC PERFORMANCE (TA = +25°C) (Note 8) Total Harmonic Distortion THD (Notes 9, 10) Spurious-Free Dynamic Range SFDR (Note 9) Effective Number of Bits ENOB (Note 9) 2 VCCA = VCCD = 3.0V 24 VCCA = VCCD = 2.7V to 5.5V VCCA = VCCD = 3.0V VCCA = VCCD = 2.7V to 5.5V 44 44 4.5 4.9 4.9 _______________________________________________________________________________________ dB dB Bits IF Undersampler MAX1005 ELECTRICAL CHARACTERISTICS (continued) (VCCA = VCCD = 3.0V, fCLK = 15MHz, RL = ∞, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL Input Full-Power Bandwidth (-1dB) CONDITIONS VIN = 90% of full scale Conversion Rate MIN TYP 15 25 MAX MHz 15 Wakeup Time Exiting Shutdown Mode Power-Supply Rejection Msps tWAKE PSR 0.6 VCC_ (A or D or both) = 3.0V ±100mVp-p at 100kHz UNITS 2.4 <0.1 µs LSB ANALOG INPUT/OUTPUT (AIO+, AIO-) (Note 11) Input Resistance RIN Input Resistance Temperature Coefficient Input Capacitance (Note 6) TA = +25°C, differential between AIO+ and AIO- 1.56 TCRIN CIN 2.00 2.44 -2000 kΩ ppm/°C Differential between AIO+ and AIO- 4 AIO+ or AIO- to GND 4 pF POWER REQUIREMENTS VCCA, VCCD Supply Voltage Analog Supply Current Digital Supply Current Shutdown Supply Current ICCA ICCD ICCA + ICD 2.7 5.5 RXEN = 1, TXEN = 0, VCCA = VCCD ADC on, DAC off = 3.0V, RXEN = 0, TXEN = 1, CL ≤ 12.5pF ADC off, DAC on V 9.0 14.8 2.5 3.8 4.0 6.4 3.0 5.6 <0.1 5 µA VCCD V 0.5 V VCCD + 0.1 V mA RXEN = 1, TXEN = 0, VCCA = VCCD ADC on, DAC off = 3.0V, RXEN = 0, TXEN = 1, CL ≤ 12.5pF ADC off, DAC on mA VCCA = VCCD = 3.0V, CL ≤ 12.5pF, RXEN = TXEN DIGITAL INPUTS/OUTPUTS (D0–D6, RXEN, TXEN, CLK) (Note 12) Output High Voltage VOH D0–D4, VCCD = 2.7V to 5.5V, ISOURCE = 200µA Output Low Voltage VOL D0–D4, VCCD = 2.7V to 5.5V, ISINK = 50µA Input High Voltage VIH VCCD = 2.7V to 5.5V Input Low Voltage VIL VCCD = 2.7V to 5.5V VCCD - 1.0 0 D0–D6, CLK 0.7VCCD RXEN, TXEN VCCD 0.5 D0–D6, CLK RXEN, TXEN 0.3VCCD -0.1 0.5 V _______________________________________________________________________________________ 3 MAX1005 IF Undersampler ELECTRICAL CHARACTERISTICS (continued) (VCCA = VCCD = 3.0V, fCLK = 15MHz, RL = ∞, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS CONDITIONS D0–D6, CLK; VCCD = 2.7V to 5.5V Input Current Input Capacitance IIN CIN MIN TYP -1 MAX UNITS 7 RXEN, TXEN; VCCD = 2.7V to 3.6V TXEN = RXEN ±1 TXEN = 0 and RXEN = 1, or TXEN = 1 and RXEN = 0 ±2 RXEN, TXEN; VCCD = 3.6V to 5.5V TXEN = RXEN ±1 TXEN = 0 and RXEN = 1, or TXEN = 1 and RXEN = 0 ±4 D0–D6, CLK; TXEN = 1, RXEN = 0 (Note 6) 8 µA pF TIMING CHARACTERISTICS (Data Outputs: RL = 1MΩ, CL = 15pF, TA = TMIN to TMAX, unless otherwise noted.) (Note 12) DAC Data Setup Time tDS TA = +25°C (Note 6) 5 0.6 DAC Data Hold Time tHOLD TA = +25°C (Note 6) 5 0.3 CLK Duty Cycle ADC CLK to Output Data Valid 45 tDO CL ≤ 12.5pF 13 ns ns 55 % 20 ns TXEN = 1, RXEN = 0. All DAC transfer function parameters are measured differentially from AIO+ to AIO- using the EndPoint Linearity method. Note 2: fIN = 4.3MHz digital sine wave applied to DAC data inputs; fCLK = 15MHz. The reference frequency (fREF) is defined to be 10.7MHz (fCLK - fIN). All frequency components present in the DAC output waveform except for fREF and fIN are considered spurious. Note 3: For DAC SFDR measurements, the amplitude of fREF (10.7MHz) is compared to the amplitudes of all frequency components of the output waveform except for fIN (4.3MHz). Note 4: For DAC measurements, THD+N is defined as the ratio of the square-root of the sum-of-the-squares of the RMS values of all harmonic and noise components of the output waveform (except for fIN and fREF) to the RMS amplitude of the fREF component. Note 5: Clock feedthrough is defined as the difference in amplitude between the fREF component and the fCLK component when measured differentially from AIO+ to AIO-. Note 6: Guaranteed by design. Not production tested. Note 7: The DAC input interface is a master/slave register. An additional half clock cycle is required for data at the digital inputs to propagate through to the DAC switches. Note 8: RXEN = 1, TXEN = 0. Unless otherwise noted, for all receive ADC measurements, the analog input signal is applied differentially from AIO+ to AIO-, specified using the Best-Fit Straight-Line Linearity method. Note 9: fIN = 10.7MHz, fCLK = 15MHz. Amplitude is 1dB below full-scale. The reference frequency (fREF) is defined to be 4.3MHz (fCLK - fIN). All components except for fREF and fIN are considered spurious. Note 10: Receive ADC THD measurements include the first five harmonics. Note 11: CAUTION: Operation of the analog inputs AIO+ and AIO- (pins 4 and 5) at more than 1.5V below VCCA could cause latchup and possible destruction of the part. Avoid shunt capacitances to GND on these pins. If shunt capacitances are required, then bypass these pins only to VCCA. Note 12: All digital input signals are measured from 50% amplitude reference points. All digital output signal propagation delays are measured to VOH(AC) for rising output signals and to VOL(AC) for falling output signals. The values for VOH(AC) and VOL(AC) as a function of the VCCD supply are shown in the following table: Note 1: 4 VCCD (V) VOH(AC) (V) VOL(AC) (V) 2.7 to 3.3 VCCD - 1.1 0.5 3.3 to 5.5 2/3 x VCCD 0.5 _______________________________________________________________________________________ IF Undersampler RECEIVE ADC DIFFERENTIAL NONLINEARITY 0.40 0.4 0.3 0.20 0.20 0.2 0.10 0.10 0.1 0.00 -0.10 0 -0.1 -0.20 -0.20 -0.2 -0.30 -0.30 -0.3 -0.40 -0.40 -0.4 -0.50 -0.50 -6 -3 0 3 6 9 12 15 -0.5 -15 -12 -9 -6 -3 0 3 6 9 12 15 -64 -32 -16 0 16 32 CODE CODE TRANSMIT DAC DIFFERENTIAL NONLINEARITY RECEIVE ADC FFT PLOT FULL POWER ANALOG INPUT BANDWIDTH 0.4 fIN = 10.7MHz fCLK = 15MHz 256 POINTS 20 10 AMPLITUDE (dB) 0.2 0.1 0 -0.1 0 -10 -20 -30 -0.2 -40 -0.3 -50 -0.4 -60 -48 -32 -16 0 CODE 16 32 48 64 64 -2 -3 -4 -5 -6 -70 -0.5 VIN = 90% OF FULL SCALE -1 AMPLITUDE (dB) 0.3 48 0 MAX1005-05 30 MAX1005-04 0.5 -64 -48 CODE MAX1005-06 0.00 -0.10 INL (LSB) 0.30 DNL (LSB) 0.30 -15 -12 -9 DNL (LSB) 0.5 MAX1005-02 0.40 INL (LSB) 0.50 MAX1005-01 0.50 TRANSMIT DAC INTEGRAL NONLINEARITY MAX1005-03 RECEIVE ADC INTEGRAL NONLINEARITY -7 0 1.465 2.930 4.395 FREQUENCY (MHz) 5.860 7.325 1 10 100 ANALOG INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 5 MAX1005 __________________________________________Typical Operating Characteristics (VCCA = VCCD = 3.0V, TA = +25°C, unless otherwise noted.) MAX1005 IF Undersampler ______________________________________________________________Pin Description PIN NAME 1 VCCD Digital Supply Voltage, +2.7V to +5.5V 2 DGND Digital Ground. Connect to digital ground plane. 3 RXEN Receive ADC Enable Input. A logic-high level on this input combined with a logic-low level on TXEN enables the receive ADC and disables the transmit DAC. If RXEN = TXEN, the MAX1005 enters its low-power shutdown mode. 4 AIO+ Positive Analog Input/Output Pin. If RXEN = 1 and TXEN = 0, then AIO+ is the positive analog input to the receive ADC. If RXEN = 0 and TXEN = 1, then AIO+ is the positive transmit DAC output pin. 5 AIO- Negative Analog Input/Output Pin. If RXEN = 1 and TXEN = 0, then AIO- is the negative analog input to the receive ADC. If RXEN = 0 and TXEN = 1, then AIO- is the negative transmit DAC output pin. 6 TXEN Transmit DAC Enable Input. A logic-high level on this input combined with a logic-low level on RXEN enables the transmit DAC and disables the receive ADC. If RXEN = TXEN, the MAX1005 enters its lowpower shutdown mode. 7 AGND Analog Ground. Connect to analog ground plane. 8 VCCA Analog Supply Voltage, +2.7V to +5.5V 9, 10 D6, D5 Two MSBs for DAC input data. D6 is the MSB. D4–D0 Data Input/Output Pins. If RXEN = 0 and TXEN = 1, then D4–D0 function as the five lower bits of DAC input data, with D0 as the LSB. If RXEN = 1 and TXEN = 0, then D4–D0 function as the five data outputs for the ADC, with D4 as the MSB and D0 as the LSB. In low-power shutdown mode (RXEN = TXEN), D0–D4 should not be externally held high, to prevent excessive input leakage currents. 11–15 16 CLK FUNCTION Clock Input. If the receive ADC is active (RXEN = 1, TXEN = 0), the analog input is sampled on the falling edge of clock and the data outputs (D4-D0) are updated on the rising edge of CLK. If the transmit DAC is active (TXEN = 1, RXEN = 0), input data is clocked in on the falling edge of CLK and the DAC output is updated on the rising edge of CLK. The input clock may continue to run when the MAX1005 is shut down (TXEN = RXEN). _______________Detailed Description The MAX1005 is designed to operate with the Maxim PWT1900 (TAG-6) wireless transceiver chipset consisting of the MAX2411 RF transceiver, the MAX2511 IF transceiver, and the MAX1007 power-control/diversity IC. The MAX1005 integrates all the functions of an IF undersampler into a single low-power integrated circuit. It is also well suited for other time-division duplex (TDD) communications systems. This device includes a 7-bit transmit DAC, a 5-bit receive ADC, two internal bandgap references, clock drivers, and all necessary interface and control logic. Transmit DAC The low-side alias frequency (f CLK - fOUT = 10.7MHz) generated by the MAX1005’s 7-bit DAC is used to recreate the IF sub-carrier and transmission data in TDD and other communications systems. The DAC accepts CMOS input data in the twos-complement format and outputs a corresponding analog voltage differentially between AIO+ and AIO-. The full-scale output voltage range is typically ±400mV. The DAC code table is shown in Table 1. 6 Table 1. Transmit DAC Code Table DAC INPUT DATA ANALOG OUTPUT 011 1111 +FS 000 0000 0 100 0000 -FS Receive ADC The 5-bit receive ADC is used to directly sample or undersample a downconverted RF signal. The ADC converts an analog input signal to a 5-bit digital output code in the twos-complement format. Figure 1 shows the ADC transfer function. Analog input signals are applied differentially between AIO+ and AIO-, with a full-scale range of ±200mV. An internal amplifier buffers the input signal and drives the comparator array, minimizing loading on the external signal source. The input amplifier has a full-power -1dB bandwidth of at least 15MHz, making this device ideally suited for undersampling applications. _______________________________________________________________________________________ IF Undersampler 01110 SAMPLE n+1 SAMPLE n+2 CLK 00010 OUTPUT CODE SAMPLE n ANALOG INPUT MAX1005 01111 00001 00000 D0–D4 n-1 11111 n n+1 tDO 11110 11101 Figure 3. Receive ADC Timing Diagram 10001 Operating Modes 10000 The MAX1005 has three operating modes: transmit, receive, and shutdown. The operating mode is selected by the RXEN and TXEN inputs, as shown in Table 2. In transmit mode, the DAC is active and the ADC is inactive. Power consumption is typically 16.5mW with a 3V supply voltage. In receive mode, the ADC is active and the DAC is inactive. Power consumption in this mode is typically 39mW with a 3V supply voltage. The third mode is shutdown, in which both the DAC and the ADC are inactive. Select this mode by setting RXEN = TXEN at any voltage from DGND to VCCD. In shutdown mode, the CLK input can continue to run without damaging the device and with no significant increase in the typical shutdown supply current specification of 0.1µA. When exiting shutdown, the MAX1005 is guaranteed to be operational within 2.4µs after TXEN or RXEN is asserted, as shown in Table 2. COM - FS +FS INPUT VOLTAGE (LSB) Figure 1. Receive ADC Transfer Function CLK DAC INPUT n-1 DATA (D0–D6) tDS n n+1 n+2 tHOLD DAC OUTPUT n-1 n n+1 Figure 2. Transmit DAC Timing Diagram Digital Interface The DAC has a 7-bit parallel digital interface. Figure 2 shows the timing diagram for the transmit DAC. Digital data is latched into the DAC input register on the falling edge of CLK. On the next rising edge of CLK the data is transferred to the DAC register and the DAC output voltage is updated. The ADC is enabled by setting TXEN = 0 and RXEN = 1. Figure 3 shows the ADC timing diagram. Input data is sampled on the falling edge of CLK, while output data changes state on the rising edge of CLK. This minimizes digital feedthrough and noise while the analog input is being sampled. The ADC output data is applied to the 5-bit parallel output pins (D0–D4), with the MSB at D4. To prevent supply-current drain due to leakage currents from entering the ADC output bits, the ADC outputs (D0–D4) should not be held high in low-power shutdown mode. Table 2. Operating Mode Selection RXEN TXEN OPERATING MODE 0 0 Low-power shutdown: ADC and DAC disabled 0 1 Transmit mode: DAC active, ADC disabled 1 0 Receive mode: ADC active, DAC disabled 1 1 Low-power shutdown: ADC and DAC disabled _______________________________________________________________________________________ 7 Power-Supply Bypassing and Grounding The MAX1005 has separate analog (VCCA) and digital (VCCD) power-supply connections, as well as separate analog and digital ground connections to minimize coupling of noisy digital signals into the circuit’s analog portion. The device will operate with both of these power supplies connected to any voltage between +2.7V and +5.5V. This feature allows the digital circuitry to operate from a regulated logic power supply; this reduces power consumption and maintains compatibility with external logic, while allowing the analog circuitry to operate from an unregulated supply. The analog ground (AGND) and digital ground (DGND) should be tied together close to the device. At no time should the voltage between AGND and DGND exceed ±0.3V. The entire board needs good DC bypassing for both analog and digital supplies. Place the power-supply bypass capacitors close to where the power is routed onto board. 10µF electrolytic capacitors with low equivalent-series-resistance (ESR) ratings are recommended. For best effective bits performance, minimize capacitive loading at the digital outputs. Keep the digital output traces as short as possible. Bypass each of the VCC_ supply pins to its respective GND with high-quality ceramic capacitors located as close to the package as possible. ________________Functional Diagram TXEN RXEN DAC BANDGAP REFERENCE ADC BANDGAP REFERENCE VCCA AGND VCCD DGND ADC CLOCK DRIVER CLK VCCA 1k AIO+ DAC CLOCK DRIVER 1k 5-BIT FLASH ADC 5 DIGITAL INTERFACE 7-BIT DAC AIO- 7 D6–D0 7 MAX1005 ___________________Chip Information TRANSISTOR COUNT: 2377 SUBSTRATE CONNECTED TO AGND ________________________________________________________Package Information QSOP.EPS MAX1005 IF Undersampler Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.