CO M PL IA NT TISP9110LDM *R oH S INTEGRATED COMPLEMENTARY BUFFERED-GATE SCRS FOR DUAL POLARITY SLIC OVERVOLTAGE PROTECTION TISP9110LDM Overvoltage Protector High Performance Protection for SLICs with +ve and -ve Battery Supplies – Wide -110 V to +110 V Programming Range – Low 5 mA max. Gate Triggering Current – Dynamic Protection Performance Specified for International Surge Waveshapes 8-SOIC (210 mil) Package (Top View) (Tip or Ring) Line Applications include: – Wireless Local Loop – Access Equipment – Regenerated POTS – VOIP Applications 1 8 NC Ground (-V(BAT)) G1 2 7 (+V(BAT)) G2 3 6 Ground (Ring or Tip) Line 4 5 NC NC - No internal connection Terminal typical application names shown in parenthesis MD-8SOIC(210)-003-a Rated for International Surge Wave Shapes Wave Shape IPPSM Standard A 2/10 GR-1089-CORE 100 10/700 ITU-T K.20/21/45 45 10/1000 GR-1089-CORE 30 Device Symbol Line ............................................... UL Recognized Component G1 G2 Description The TISP9110LDM is a programmable overvoltage protection device designed to protect modern dual polarity supply rail ringing SLICs (Subscriber Line Interface Circuits) against overvoltages on the telephone line. Overvoltages can be caused by lightning, a.c. power contact and induction. Four separate protection structures are used; two positive and two negative to provide optimum protection during Metallic (Differential) and Longitudinal (Common Mode) protection conditions in both polarities. Dynamic protection performance is specified under typical international surge waveforms from Telcordia GR-1089CORE, ITU-T K.44 and YD/T 950. Ground Line SD-TISP9-001-a The TISP9110LDM is programmed by connecting the G1 and G2 gate terminals to the negative (-V(BAT)) and positive (+V(BAT)) SLIC Battery supplies respectively. This creates a protector operating at typically +1.4 V above +V(BAT) and -1.4 V below -V(BAT) under a.c. power induction and power contact conditions. The protector gate circuitry incorporates 4 separate buffer transistors designed to provide independent control for each protection element. The gate buffer transistors minimize supply regulation issues by reducing the gate current drawn to around 5 mA, while the high voltage base emitter structures eliminate the need for expensive reverse bias protection gate diodes. The TISP9110LDM is rated for common surges contained in regulatory requirements such as ITU-T K.20, K.45, Telcordia GR-1089-CORE, YD/T 950. By the use of appropriate overcurrent protection devices such as the Bourns® Multifuse® and Telefuse™ devices, circuits can be designed to comply with modern telecom standards. How To Order Device Package Carrier TISP9110LDM 8-SOIC (210 mil) Embossed Tape Reeled *RoHS Directive 2002/95/EC Jan 27 2003 including Annex AUGUST 2004 – REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. For Lead Free Termination Finish Order As TISP9110LDMR-S Marking Code Standard Quantity 9110L 2000 TISP9110LDM Overvoltage Protector Absolute Maximum Ratings, TA = 25 °C (Unless Otherwise Noted) Rating Symbol Value Unit VDRM -120 +120 V Repetitive peak off-state voltage VG1(Line) = 0, VG2 ≥ +5 V VG2(Line) = 0, VG1 ≥ -5 V Non-repetitive peak impulse current (see Notes 1, 2, 3 and 4) 2/10 µs (Telcordia GR-1089-CORE) 5/310 µs (ITU-T K.20, K.21 & K.45, K.44 open-circuit voltage wave shape 10/700 µs) 10/1000 µs (Telcordia GR-1089-CORE) IPPSM ±100 ±45 ±30 A ITSM 9.0 5.0 1.7 A Non-repetitive peak on-state current, 50 Hz / 60 Hz (see Notes 1, 2, 3 and 5) 0.2 s 1s 900 s Maximum negative battery supply voltage VG1M -110 V Maximum positive battery supply voltage VG2M +110 V ∆V(BAT)M 220 V TJ -40 to +150 °C Tstg -65 to +150 °C Maximum differential battery supply voltage Junction temperature Storage temperature range NOTES: 1. Initially the device must be in thermal equilibrium with TJ = 25 °C. The surge may be repeated after the device returns to its initial conditions. 2. The rated current values may be applied to either of the Line to Ground terminal pairs. Additionally, both terminal pairs may have their rated current values applied simultaneously (in this case the Ground terminal current will be twice the rated current value of a single terminal pair). 3. Rated currents only apply if pins 6 & 7 (Ground) are connected together. 4. Applies for the following bias conditions: VG1 = -20 V to -110 V, VG2 = 0 V to +110 V. 5. EIA/JESD51-2 environment and EIA/JESD51-7 high effective thermal conductivity test board (multi-layer) connected with 0.6 mm printed wiring track widths. Electrical Characteristics for any Section, TA = 25 °C (Unless Otherwise Noted) Parameter Test Conditions VD = VDRM, VG1(Line) = 0, VG2 ≥ +5 V ID Off-state current VD = VDRM, VG2(Line) = 0, VG1 ≥ -5 V Min Typ TA = 25 °C TA = 85 °C TA = 25 °C TA = 85 °C Max Unit -5 -50 +5 +50 µA IG1(Line) Negative-gate leakage current VG1(Line) = -220 V -5 µA IG2(Line) Positive-gate leakage current VG2(Line) = +220 V +5 µA VG1L(BO) Gate - Line impulse breakover voltage VG1 = -100 V, IT = -100 A (see Note 6) VG1 = -100 V, IT = -30 A VG2L(BO) Gate - Line impulse breakover voltage VG2 = +100 V, IT = +100 A (see Note 6) VG2 = +100 V, IT = +30 A IH- Negative holding current IG1T Negative-gate trigger current IT = -5 A, tp(g) ≥ 20 µs, VG1 = -60 V IG2T Positive-gate trigger current IT = 5 A, tp(g) ≥ 20 µs, VG2 = 60 V CO Line - Ground off-state capacitance NOTE: VG1 = -60 V, IT = -1 A, di/dt = 1 A/ms f = 1 MHz, VD = -3 V, G1 & G2 open circuit 2/10 µs 10/1000 µs -15 -11 V 2/10 µs 10/1000 µs +15 +11 V +5 mA -5 mA -150 mA 32 pF 6. Voltage measurements should be made with an oscilloscope with limited bandwidth (20 MHz) to avoid high frequency noise. AUGUST 2004 – REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. TISP9110LDM Overvoltage Protector Thermal Characteristics, TA = 25 °C (Unless Otherwise Noted) Parameter RθJA NOTE Test Conditions Junction to ambient thermal resistance Min Typ Max Unit 55 °C/W EIA/JESD51-7 PCB, EIA/JESD51-2 Environment, PTOT = 4 W (See Note 7) 7. EIA/JESD51-7 high effective thermal conductivity test board (multi-layer) connected with 0.6 mm printed wiring track widths. Parameter Measurement Information +i Quadrant I IPPSM Switching Characteristic ITSM ITRM V(BO) IH V G1 -v VD ID ID VD V G2 +v IH V(BO) ITRM Quadrant III ITSM Switching Characteristic IPPSM -i Figure 1. Voltage-Current Characteristic Unless Otherwise Noted, All Voltages are Referenced to the Ground Terminal AUGUST 2004 – REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. PM-TISP9-001-a TISP9110LDM Overvoltage Protector Typical Characteristics OFF-STATE CAPACITANCE vs OFF-STATE VOLTAG E TC-TISP9-001-a Co - Off-state Capacitance - pF 45 40 35 30 25 20 15 10 0.1 NON-REPETITIVE PEAK ON-STATE CURRENT vs CURRENT DURATION ITSM(t) - Non-Repetitive Peak On-State Current - A 50 Thermal Information TJ = 25 °C V d = 1 Vrms 1 10 V D - Off-state Voltage - V Figure 2. 100 TI-TISP9-001-a 15 V GEN = 600 Vrms, 50/60 Hz RGEN = 1.4*V GEN/ITSM(t) EIA/JESD51-2 ENVIRONMENT EIA/JESD51-7 PCB, TA = 25 °C SIMULTANEOUS OPERATION OF R AND T TERMINALS. GROUND TERMINAL CURRENT = 2 x ITSM(t) 10 9 8 7 6 5 4 3 2 1.5 1 0.1 1 10 100 1000 t - Current Duration - s Figure 3. AUGUST 2004 – REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. TISP9110LDM Overvoltage Protector APPLICATIONS INFORMATION Overcurrent Protection SLIC SLIC PROTECTOR Tip C1 220 nF C2 220 nF Ring TISP9110LDM +V BAT D1 -VBAT Figure 4. Typical Application Diagram GR-1089-Core Intra Building Overcurrent Protection 1 GR-1089-CORE Overcurrent Protection 2 ITU-T K20 (Basic) Overcurrent Protection 3 + t° MF-SM013-250 F1a B0500T + t° 35 Ω CPTC * 2027-35 GDT (Bourns) Telcordia GR-1089-CORE Issue 3 compliant LFR (Custom) + t° MF-SM013-250 F1b B0500T ITU-T K20 (Enhanced) Overcurrent Protection 4 + t° 35 Ω CPTC * Agreed Primary Figure 5. Typical Overcurrent Protection “TISP” is a trademark of Bourns, Ltd., a Bourns Company, and is Registered in U.S. Patent and Trademark Office. “Bourns” is a registered trademark of Bourns, Inc. in the U.S. and other countries. AUGUST 2004 – REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. AI-TISP9-001-a