*R oH V SC AV ER OM AI SIO PL LA N IA BL S NT E TISP8200M, BUFFERED P-GATE SCR DUAL TISP8201M, BUFFERED N-GATE SCR DUAL COMPLEMENTARY BUFFERED-GATE SCRS FOR DUAL POLARITY SLIC OVERVOLTAGE PROTECTION TISP8200M & TISP8201M High Performance Protection for SLICs with +ve & -ve Battery Supplies TISP8200M D Package (Top View) TISP8200M, Negative Overvoltage Protector – Wide 0 to -90 V Programming Range – Low 5 mA max. Gate Triggering Current – High -150 mA min. Holding Current G1 1 8 NC K1 2 7 A K2 3 6 A G2 4 5 NC MDRXAKC TISP8201M, Positive Overvoltage Protector – Wide 0 to +90 V Programming Range – Low -5 mA max. Gate Triggering Current – 20 mA min. Holding Current NC - No internal connection TISP8200M Device Symbol K1 Rated for International Surge Wave Shapes Wave Shape Itsp Standard 2/10 µs 10/700 µs 10/1000 µs Telcordia GR-1089-CORE ITU-T K.20, K.21 & K.45 Telcordia GR-1089-CORE G1 A 210 70 45 A A G2 Surface Mount Small-Outline Package K2 SDRXAJB ............................................ UL Recognized Components TISP8201M D Package (Top View) Description The TISP8200M/TISP8201M combination has been designed to protect dual polarity supply rail monolithic SLICs (Subscriber Line Interface Circuits) against overvoltages on the telephone line caused by lightning, a.c. power contact and induction. Protection against negative overvoltages is given by the TISP8200M. Protection against positive overvoltages is given by the TISP8201M. Both parts are in 8-pin smalloutline surface mount packages. The TISP8200M has an array of two buffered P-gate SCRs with a common anode connection. Each SCR cathode and gate has a separate terminal connection. The NPN buffer transistors reduce the gate supply current. G1 1 8 NC A1 2 7 K A2 3 6 K G2 4 5 NC MDRXALC NC - No internal connection TISP8201M Device Symbol A1 G1 In use, the cathodes of the TISP8200M SCRs are connected to the two conductors of the POTS line (see applications information). The gates are connected to the appropriate negative voltage battery feed of the SLIC driving the line conductor pair. This ensures that the TISP8200M protection voltage tracks the SLIC negative supply voltage. The anode of the TISP8200M is connected to the SLIC common. K K G2 A2 SDRXAKB How To Order Device Package Carrier For Standard Termination Finish Order As For Lead Free Termination Finish Order As TISP8200M D (8-pin Small-Outline) Embossed Tape Reeled TISP8200MDR TISP8200MDR-S TISP8201M D (8-pin Small-Outline) Embossed Tape Reeled TISP8201MDR TISP8201MDR-S *RoHS Directive 2002/95/EC Jan 27 2003 including Annex MAY 1998 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. TISP8200M & TISP8201M Description (Continued) Negative overvoltages are initially clipped close to the SLIC negative supply by emitter follower action of the NPN buffer transistor. If sufficient clipping current flows, the SCR will regenerate and switch into a low voltage on-state condition. As the overvoltage subsides, the high holding current of the SCR prevents d.c. latchup. The TISP8201M has an array of two buffered N-gate SCRs with a common cathode connection. Each SCR anode and gate has a separate terminal connection. The PNP buffer transistors reduce the gate supply current. In use, the anodes of the TISP8201M SCRs are connected to the two conductors of the POTS line (see applications information). The gates are connected to the appropriate positive voltage battery feed of the SLIC driving that line pair. This ensures that the TISP8201M protection voltage tracks the SLIC positive supply voltage. The cathode of the TISP8201M is connected to the SLIC common. Positive overvoltages are initially clipped close to the SLIC positive supply by emitter follower action of the PNP buffer transistor. If sufficient clipping current flows, the SCR will regenerate and switch into a low voltage on-state condition. As the overvoltage subsides, the SLIC pulls the conductor voltage down to its normal negative value and this commutates the conducting SCR into a reverse biassed condition. Absolute Maximum Ratings for TISP8200M, T A = 25 °C (Unless Otherwise Noted) Rating Symbol Value Unit Repetitive peak off-state voltage, TISP8200M VGK = 0 VDRM -120 V Repetitive peak reverse voltage, VGA = -70 V VRRM 120 V Non-repetitive peak on-state pulse current, (see Notes 1 and 2) 10/1000 µs (Telcordia/Bellcore GR-1089-CORE, Issue 2, February 1999, Section 4) 5/310 µs (ITU-T K.20, K.21& K.45, K.44 open-circuit voltage wave shape 10/700 µs) ITSP 2/10 µs (Telcordia/Bellcore GR-1089-CORE, Issue 2, February 1999, Section 4) -45 -70 A -210 Non-repetitive peak on-state current, 50/60 Hz (see Notes 1, 2 and 3) 100 ms 1s 5s 300 s 900 s Non-repetitive peak gate current, 2/10 µs pulse, cathode commoned (see Note 1) ITSM -11 -6.5 -3.4 -1.4 -1.3 A I GSM 10 A Junction temperature TJ -55 to +150 °C Storage temperature range Tstg -65 to +150 °C NOTES: 1. Initially, the protector must be in thermal equilibrium with -40 °C ≤ TJ ≤ 85 °C. The surge may be repeated after the device returns to its initial conditions. 2. These non-repetitive rated currents are peak values. The rated current values may be applied to any cathode-anode terminal pair. Above 85 °C, derate linearly to zero at 150 °C lead temperature. 3. These non-repetitive rated terminal currents are for the TISP8200M and TISP8201M together. Device (A) terminal positive current values are conducted by the TISP8201M and (K) terminal negative current values by the TISP8200M. MAY 1998 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. TISP8200M & TISP8201M Absolute Maximum Ratings for TISP8201M, TA = 25 °C (Unless Otherwise Noted) Rating Symbol Value Unit Repetitive peak off-state voltage, VGA = 0 VDRM 120 V Repetitive peak reverse voltage, VGK = 70 V VRRM -120 V Non-repetitive peak on-state pulse current, (see Notes 1 and 2) 10/1000 µs (Telcordia (Bellcore) GR-1089-CORE, Issue 2, February 1999, Section 4) 5/310 µs (ITU-T K.20, K.21& K.45, K.44 open-circuit voltage wave shape 10/700 µs) 45 ITSP A 70 2/10 µs (Telcordia (Bellcore) GR-1089-CORE, Issue 2, February 1999, Section 4) 210 Non-repetitive peak on-state current, 50/60 Hz (see Notes 1, 2 and 3) 100 ms 1s 5s 300 s 900 s 11 6.5 3.4 1.4 1.3 ITSM Non-repetitive peak gate current, 2/10 µs pulse, cathode commoned (see Note 1) A I GSM -10 A Junction temperature TJ -55 to +150 °C Storage temperature range Tstg -65 to +150 °C NOTES: 1. Initially, the protector must be in thermal equilibrium with -40 °C ≤ TJ ≤ 85 °C. The surge may be repeated after the device returns to its initial conditions. 2. These non-repetitive rated currents are peak values. The rated current values may be applied to any cathode-anode terminal pair. Above 85 °C, derate linearly to zero at 150 °C lead temperature. 3. These non-repetitive rated terminal currents are for the TISP8200M and TISP8201M together. Device (A) terminal positive current values are conducted by the TISP8201M and (K) terminal negative current values by the TISP8200M. Recommended Operating Conditions See Figure 10 C1, C2 Gate decoupling capacitor Series resistance for Telcordia GR-1089-CORE first-level and second-level surge survival R1, R2 Series resistance for ITU-T K.20, K.21 and K.45 coordination with a 400 V primary protector Min Typ Max Unit 100 220 nF 15 10 20 20 Ω MAY 1998 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. TISP8200M & TISP8201M Electrical Characteristics for TISP8200M, TA = 25 °C (Unless Otherwise Noted) Parameter ID IR Off-state current Test Conditions VD = VDRM, VGK = 0 Max Unit TJ = 0 °C Min -5 µA TJ = 85 °C -50 µA TJ = 0 °C 5 µA 50 µA -82 V Reverse current VR = VRRM, VGA = -70 V V(BO) Breakover voltage dv/dt = -250 V/ms, Source Resistance = 300 Ω, VGA = -80 V V(BO) TJ = 85 °C Breakover voltage 2/10 waveshape, (IK) IT = -100 A, di/dt max. = -58 A/µs, VGA = -80 V IH Holding current (IK) IT = -1 A, di/dt = 1 A/ms, VGA = -80 V IGT Gate trigger current (IK) IT = -5 A, t p(g) ≥ 20 µs, VGA = -80 V Coff NOTE Off-state capacitance Typ f = 1 MHz, Vd = 1 V, VGA = -80 V, (see Note 4) -95 -150 V mA 5 VD = 0 35 VD = -5 V 20 VD = -50 V 10 mA pF 4: These capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit. The unmeasured device terminals are a.c. connected to the guard terminal of the bridge. Electrical Characteristics for TISP8201M, TA = 25 °C (Unless Otherwise Noted) Parameter Test Conditions Min Typ Max Unit TJ = 0 °C 5 µA TJ = 85 °C 50 µA TJ = 0 °C -5 µA TJ = 85 °C -50 µA ID Off-state current VD = VDRM, VGA = 0 IR Reverse current VR = VRRM, VGK = 70 V V(BO) Breakover voltage dv/dt = 250 V/ms, Source Resistance = 300 Ω, VGK = 80 V 82 V V(BO) Breakover voltage 2/10 waveshape, (IA) IT = 100 A, di/dt max. = 58 A/µs, VGK = 80 V 95 V -5 mA IH Holding current (IA) IT = 1 A, di/dt = -1 A/ms, VGK = 80 V IGT Gate trigger current (IA) IT = 5 A, t p(g) ≥ 20 µs, VGK = 80 V Coff Off-state capacitance f = 1 MHz, Vd = 1 V, VGK = 80 V, (see Note 4) NOTE +20 mA VD = 0 35 VD = 5 V 20 VD = 50 V 10 pF 4: These capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit. The unmeasured device terminals are a.c. connected to the guard terminal of the bridge. Thermal Characteristics Parameter RθJA Junction to free air thermal resistance Test Conditions Ptot = 0.52 W, TA = 70°C, 5 cm 2, FR4 PCB MAY 1998 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. Min Typ Max Unit 160 °C/W TISP8200M & TISP8201M Parameter Measurement Information +i Quadrant I Blocking Characteristic VGK(BO) VGA -v VD IR IRRM ID VR VRRM +v IH V(BO) ITSM Quadrant III ITSP Switching Characteristic PM8XACB -i Figure 1. TISP8200M KA Terminal Characteristic +i Quadrant I ITSP Switching Characteristic ITSM V(BO) IH -v VRRM VR ID IR IRRM VD +v VGK VGA(BO) Quadrant III Blocking Characteristic PM8XABB -i Figure 2. TISP8201M AK Terminal Characteristic MAY 1998 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. TISP8200M & TISP8201M APPLICATIONS INFORMATION Operation of SLICs using Positive and Negative Voltage Supply Rails Figure 3 shows a typical powering arrangement for a multi-supply rail SLIC. VBATR is a positive supply and VBATL and VBATH are negative supplies. VBATH is more negative than VBATL. With the positive and negative supply switches S2 and S1 in the positions shown, the line driver amplifiers are powered between 0 V and VBATL. This mode minimizes the power consumption for short loop transmission. For long loops, the driver voltage is increased by operating S1 to connect VBATH. To generate ringing, S2 is operated to apply VBATR, powering the drivers from a total supply voltage of VBATR - VBATH. These conditions are shown in Figure 4. SLIC S2 S1 LINE LINE DRIVERS SUPPLY SWITCHES 0V VBATR VBATL VBATH AI8XAF Figure 3. SLIC with Voltage Supply Switching VBATR VSLICR VPKRING /2 0V VPKRING /2 0V VBATR - VBATH VDCRING VPKRING /2 VPKRING /2 VBATL VSLICH VBATH SHORT LOOP LONG LOOP VBATH RINGING AI8XAG Figure 4. Driver Supply Voltage Levels Conventional ringing is typically unbalanced ground or battery backed. To minimize the supply voltage required, most multi-rail SLICs use balanced ringing as shown in Figure 4. The ringing has d.c., VDCRING, and a.c., VPKRING, components. A 70 V rms a.c. ring signal has a peak value, VPKRING, of 99 V. If the d.c. component was 20 V, then the total voltage swing needed would be 99 + 20 = 119 V. There are internal losses in the SLIC from the positive supply, VSLICR, and the negative supply, VSLICH. The sum of these two losses generally amounts to a total of 10 V. This makes a total supply rail value of 119 + 10 = 129 V. In practice, the voltage might be distributed as VBATR = +60 V and VBATH = -70 V. These values are nominal and some extra voltage should be provided to cover power supply voltage tolerance. MAY 1998 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. TISP8200M & TISP8201M SLIC Parameter Values The table below shows some details of currently available SLICs using positive and negative supply rails. Manufacturer INFINEON‡ LEGERITY™‡ SLIC SERIES SLIC-S‡ SLIC-E‡ ISLIC™‡ SLIC # PEB4264 PEB 4265 79R251 Data Sheet Issue 14/07/2000 14/07/2000 -/08/2000 Short Circuit Current ±130 ±130 ±150 Unit mA VBATH max. -70 -90 -85 V VBATR max. +50 +90 +85 V VBATR-VBATH max. 90 160 150 V AC Ringing for: 45 85 65 V rms VBATH -54 -70 -68 V VBATR +36 +80 +52 V VBATR-VBATH 90 150 120 R or T Power Max. < 10 ms TBA 10 R or T Overshoot < 10 ms -5 R or T Overshoot < 1 ms -10 +10 -10 +10 R or T Overshoot < 10 µs -10 +30 -10 +30 R or T Overshoot < 1 µs Line Feed Resistance 5 V 10 -15 20 + 30 20 + 30 V V -10 R or T Overshoot < 250 ns V W 15 50 V V Ω ‡ Legerity, the Legerity logo and ISLIC are the trademarks of Legerity, Inc. (formerly AMD’s Communication Products Division). Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. The maximum total voltage, VBATR - VBATH, is normally about 10 % less than the sum of the maximum VBATR and maximum VBATH values. In terms of voltage overshoot, ±10 V is needed for 1 µs and ±15 V for 250 ns. It is important to define the protector overshoot under actual circuit conditions. For example, if the series line feed resistor was 20 Ω, R1 in Figure 10, and Telcordia GR-1089-CORE 2/10 and 10/1000 first level impulses were applied, the peak protector currents would be 100 A and 33 A. Therefore, the protector voltage overshoot should be measured at 100 A, 2/10 and 33 A, 10/1000. Using the table values for maximum battery voltage and minimum overshoot gives a requirement of ±105 V from the output to ground and ±175 V between outputs. There needs to be temperature guard banding for the change in protector characteristics with temperature. To cover down to -40 °C, the 25 °C protector minimum values become ±120 V referenced to ground, ±190 V between outputs and 100 V or -100 V on the gate. Operation of Gated Protectors Figure 5 shows how the TISP8200M and TISP8201M limit overvoltages. The TISP8200M SCR sections limit negative overvoltages and the TISP8201M SCR sections limit positive overvoltages. The TISP8200M (buffered) gate is connected to the negative SLIC battery feed voltage (VBATH) to provide the protection reference voltage. Negative overvoltages are initially clipped close to the SLIC negative supply rail value (VBATH) by the conduction of the TISP8200M transistor base-emitter and the SCR gate-cathode junctions. If sufficient current is available from the overvoltage, then the SCR will crowbar into a low voltage ground referenced on-state condition. As the overvoltage subsides, the high holding current of the SCR prevents d.c. latchup with the SLIC output current. MAY 1998 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. TISP8200M & TISP8201M Operation of Gated Protectors (Continued) VBATR 0V IG TISP 8200M TISP 8201M RING C2 100 nF IA SLIC IK TIP IG VBATH C1 100 nF AI8XAD 0V Figure 5. Overvoltage Conditions The negative protection voltage, V(BO), will be the sum of the gate supply (VBATH) and the TISP8200M peak gate(terminal)-cathode voltage (VGT). Under a.c. overvoltage conditions VGT will be less than 2.0 V. The integrated transistor buffer in the TISP8200M greatly reduces protector’s source and sink current loading on the V BATH supply. Without the transistor, the SCR gate current would charge the VBATH supply. An electronic power supply is not usually designed to be charged like a battery. As a result, the electronic supply would switch off and the SCR gate current would provide the SLIC supply current. Normally the SLIC current would be less than the gate current, which would cause the supply voltage to increase and destroy the SLIC by a supply overvoltage. Older designs using just SCRs needed to incorporate a sacrificial zener diode across the supply line to go short if the supply voltage increased too much. The integrated transistor buffer removes the charging problem and the need for a safety zener. Fast rising impulses will cause short term overshoots in gate-cathode voltage. The negative protection voltage under impulse conditions will also be increased if there is a long connection between the gate decoupling capacitor, C1, and the gate terminal. During the initial rise of a fast impulse, the gate current (I G) is the same as the cathode current (IK). Rates of 60 A/µs can cause inductive voltages of 0.6 V in 2.5 cm of printed wiring track. To minimize this inductive voltage increase of protection voltage, the length of the capacitor to gate terminal tracking should be minimized. The TISP8201M (buffered) gate is connected to the positive SLIC battery feed voltage (VBATR) to provide the protection reference voltage. Positive overvoltages are initially clipped close to the SLIC positive supply rail value (VBATR ) by the conduction of the TISP8201M transistor base-emitter and the SCR gate-anode junctions. If sufficient current is available from the overvoltage, then the SCR will crowbar into a low voltage ground referenced on-state condition. As the overvoltage subsides the SLIC pulls the conductor voltage down to its normal negative value and this commutates the conducting SCR into a reverse biassed condition. Voltage Stress Levels on the TISP8200M and TISP8201M Figure 6 shows the protector electrodes. The package terminal designated gate, G, is the transistor base, B, electrode connection and so is marked as B (G). The following junctions are subject to voltage stress: Transistor EB and CB, SCR AK (reverse and off state). This clause covers the necessary testing to ensure the junctions are good. Testing transistor EB and SCR AK reverse: The highest reverse EB voltage and reverse AK voltage occurs during the overshoot period of the other protector. For the TISP8200M, the SCR has VBATR plus the TISP8201M overshoot above VBATR . The transistor EB has an additional VBATH voltage applied (see Figure 7). The reverse current, IR, flowing into the K terminal will be the sum of the transistor IEB and the actual internal SCR IR . The reverse voltage applied to the K terminal is the TISP8201M protection voltage, V (BO) (VBATR plus overshoot), and the G terminal has VBATH. Similarly for the TISP8201M, IR is measured with the TISP8200M V(BO) applied and it is the sum of the transistor IEB and the actual internal SCR IR. VBATR is applied to the G terminal. MAY 1998 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. TISP8200M & TISP8201M Voltage Stress Levels on the TISP8200M and TISP8201M (Continued) Testing transistor CB and SCR AK off state: The highest AK voltage occurs during the overshoot period of the protector. To make sure that the SCR blocking junction does not break down during this period, a d.c. test for off-state current can be applied at the overshoot voltage value. To avoid transistor CB current amplification by the transistor gain, the transistor base-emitter is shorted during this test (see Figure 8). Summary: Two tests are needed to verify the protector junctions. Maximum current values for IR and ID are required. TISP 8201M A E VBATR K C B (G) 0V 0V RING OR TIP A C K E B (G) VBATH TISP 8200M AI8XAH Figure 6. Protector Electrodes IR A V(BO) 8201M IR (internal) 0V IEB TISP 8201M VBATR B (G) 0V IR (internal) B (G) K IEB VBATH V(BO) 8200M TISP 8200M IR AI8XAJ Figure 7. Reverse Current Verification ID TISP 8201M A V(BO) 8201M ID (internal) B (G) ICB 0V 0V ICB ID (internal) V(BO) 8200M B (G) K ID TISP 8200M AI8XAK Figure 8. Off-State Current Verification MAY 1998 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. TISP8200M & TISP8201M TISP8200M and TISP8201M Voltage Overshoot Figure 9 shows typical overshoots on a 100 A 2/10 waveshape. Both devices are under 10 V peak, which meets the needs of the SLICs listed earlier. Line Protection with TISP8200M and TISP8201M Figure 10 shows a typical circuit for single line protection using one TISP8200M and one TISP8201M. The series resistor values limit the test impulse currents to within the protector ratings. TISP8201M 2/10 OVERSHOOT TISP8200M 2/10 OVERSHOOT AI8XAMA 20 AI8XANA 20 (IA) IT = +100 A VGK = +80 V (IK) IT = -100 A VGA = -80 V 10 Overshoot Voltage - V Overshoot Voltage - V 10 0 0 -10 -10 -20 -20 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 Time - ns 300 Time - ns Figure 9. Voltage Overshoot Referenced to Gate Bias Voltage VBATR 0V R1 TISP 8201M C2 100 nF TISP 8200M RING GR-1089-CORE R1 = 15 Ω min. (1st & 2 nd level) SLIC ITU-T K.20 & K.21 R1 = 10 Ω min for coordination TIP R1 V BATH C1 100 nF AI8XAE Figure 10. Line Protection with TISP8200M and TISP8201M MAY 1998 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. 0V 400 500 TISP8200M & TISP8201M MECHANICAL DATA Device Symbolization Code Devices are coded as below. Device TISP8200M TISP8201M Symbolization 8200M 8201M MAY 1998 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. TISP8200M & TISP8201M MECHANICAL DATA D008 Plastic Small Outline Package This small-outline package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The compound will withstand soldering temperature with no deformation, and circuit performance characteristics will remain stable when operated in high humidity conditions. Leads require no additional cleaning or processing when used in soldered assembly. D008 8-pin Small Outline Microelectronic Standard Package MS-012, JEDEC Publication 95 4. 80 - 5. 00 (0.189 - 0. 19 7) 5. 80 - 6. 20 (0.228 - 0.244) 8 7 6 5 1 2 3 4 INDEX 3. 81 - 4. 00 (0.150 - 0.157) 1. 35 - 1.75 (0.053 - 0.069) 7° N O M 3 P la ces 0. 25 - 0.50 x 45 °N O M (0.010 - 0.020) 0. 10 2 - 0.203 (0.004 - 0.008) 0. 28 - 0.79 (0.011 - 0. 03 1) DIMENSIONS ARE: NOTES: A. B. C. D. Pin Spacing 1. 27 (0.050) (see Note A) 6 P laces 0. 36 - 0.51 (0.014 - 0.020) 8 P laces 0. 19 0 - 0.229 (0.0075 - 0. 00 90) 4. 60 - 5.21 (0.181 - 0.205) 7° NOM 4 P la ces 4° ± 4° 0. 51 - 1.12 (0.020 - 0.044) MILLIMETERS (INCHES) Leads are within 0.25 (0.010) radius of true position at maximum material condition. Body dimensions do not include mold flash or protrusion. Mold flash or protrusion shall not exceed 0.15 (0.006). Lead tips to be planar within ±0.051 (0.002). MAY 1998 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications. MD XXAAE TISP8200M & TISP8201M MECHANICAL DATA D008 Tape Dimensions D008 Package (8-pin Small Outline) Single-Sprocket Tape 1. 50 - 1.60 (.059 - .063 ) 3. 90 - 4.10 (.154 - .161 ) 7. 90 - 8.10 (.311 - .319) 1. 95 - 2.05 (.077 - .081) 0. 8 MIN . (.03) 5. 40 - 5.60 (.213 - .220 ) 1. 5 MIN . (.059) 6. 30 - 6. 50 (.248 - .256) Carrier Tape Direction of Feed Embossment NOTES: A. Taped devices are supplied on a reel of the following dimensions:Reel diameter: Reel hub diameter: Reel axial hole: 0. 40 (.016) 11 .70 - 12.30 (.461 - .484 ) Cover 0 MIN . Tape 2. 0 - 2.2 (.079 - .087 ) MDXXATC 330 +0.0/-4.0 (12.99 +0.0/-.157) 10 0 ±2. 0 (3.937 ±.079) 13.0 ±0.2 (.512 ±.008) B. 2500 devices are on a reel. “TISP” is a trademark of Bourns, Ltd., a Bourns Company, and is Registered in U.S. Patent and Trademark Office. “Bourns” is a registered trademark of Bourns, Inc. in the U.S. and other countries. MAY 1998 - REVISED FEBRUARY 2005 Specifications are subject to change without notice. Customers should verify actual device performance in their specific applications.