FAIRCHILD 100336PC

Revised August 2000
100336
Low Power 4-Stage Counter/Shift Register
General Description
The 100336 operates as either a modulo-16 up/down
counter or as a 4-bit bidirectional shift register. Three
Select (Sn) inputs determine the mode of operation, as
shown in the Function Select table. Two Count Enable
(CEP, CET) inputs are provided for ease of cascading in
multistage counters. One Count Enable (CET) input also
doubles as a Serial Data (D0) input for shift-up operation.
For shift-down operation, D3 is the Serial Data input. In
counting operations the Terminal Count (TC) output goes
LOW when the counter reaches 15 in the count/up mode or
0 (zero) in the count/down mode. In the shift modes, the TC
output repeats the Q3 output. The dual nature of this TC/Q3
output and the D0/CET input means that one interconnection from one stage to the next higher stage serves as the
link for multistage counting or shift-up operation. The indi-
vidual Preset (Pn) inputs are used to enter data in parallel
or to preset the counter in programmable counter applications. A HIGH signal on the Master Reset (MR) input overrides all other inputs and asynchronously clears the flipflops. In addition, a synchronous clear is provided, as well
as a complement function which synchronously inverts the
contents of the flip-flops. All inputs have 50 kΩ pull-down
resistors.
Features
■ 40% power reduction of the 100136
■ 2000V ESD protection
■ Pin/function compatible with 100136
■ Voltage compensated operating range = −4.2V to −5.7V
■ Available to industrial grade temperature range
Ordering Code:
Order Number
Package Number
Package Description
100336SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100336PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100336QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100336QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (−40°C to +85°C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
24-Pin DIP/SOIC
28-Pin PLCC
Logic Symbol
© 2000 Fairchild Semiconductor Corporation
DS010584
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100336 Low Power 4-Stage Counter/Shift Register
August 1989
100336
Function Select Table
Pin Descriptions
S2
S1
S0
L
L
L
Parallel Load
Function
Pin Names
Description
L
L
H
L
H
L
L
H
H
Shift Right
H
L
L
Count Down
S0–S2
Select Inputs
H
L
H
Clear
MR
Master Reset Input
H
H
L
Count Up
P0–P3
Preset Inputs
H
H
H
Hold
D3
Serial Data Input
TC
Terminal Count Output
Q0–Q3
Data Outputs
Q0–Q3
Complementary Data Outputs
CP
Clock Pulse Input
Complement
CEP
Count Enable Parallel Input (Active LOW)
Shift Left
D0/CET
Serial Data Input/Count Enable
Trickle Input (Active LOW)
Truth Table
Q0 = LSB
Inputs
Outputs
MR S2 S1 S0 CEP D0/CET D3 CP Q3 Q2 Q1 Q0
L
L
L
L
X
X
X
L
L
L
L
H
X
X
X
L
H
L
X
X
X
L
L
H
H
X
X
X
L
H
L
L
L
L
X
L
H
L
L
H
L
X
L
H
L
L
X
H
X
L
H
L
H
X
X
X
L
H
H
L
L
L
X
L
H
H
L
H
L
X
L
H
H
L
X
H
L
H
H
H
X
H
L
L
L
H
L
L
H
L
H
H
L
H
P3 P2 P1 P0
TC
Mode
L
Preset (Parallel Load)
Q3 Q2 Q1 Q0
L
Invert
D3 Q3 Q2 Q1
D3
Shift to LSB
Q2 Q1 Q0 D0 Q3 (Note 1) Shift to MSB
(Q0–3) minus 1
1
Count Down
X Q3 Q2 Q1 Q0
1
Count Down with CEP not active
H
Count Down with CET not active
L
H
Clear
(Q0–3) plus 1
X Q3 Q2 Q1 Q0
L
L
L
2
Count Up
X Q3 Q2 Q1 Q0
2
Count Up with CEP not active
X
X Q3 Q2 Q1 Q0
H
Count Up with CET not active
X
X
X Q3 Q2 Q1 Q0
H
Hold
X
X
X
X
L
L
L
L
L
H
X
X
X
X
L
L
L
L
L
L
X
X
X
X
L
L
L
L
L
H
H
X
X
X
X
L
L
L
L
L
Asynchronous
H
L
L
X
L
X
X
L
L
L
L
L
Master Reset
H
H
L
L
X
H
X
X
L
L
L
L
H
H
H
L
H
X
X
X
X
L
L
L
L
H
H
H
H
L
X
X
X
X
L
L
L
L
H
H
H
H
H
X
X
X
X
L
L
L
L
H
1 = L if Q0–Q3 = LLLL
H if Q0–Q3 ≠ LLLL
2 = L if Q0–Q3 = HHHH
H if Q0–Q3 ≠ HHHH
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
= LOW-to-HIGH Transition
Note 1: Before the clock, TC is Q3
After the clock, TC is Q2
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100336
Logic Diagram
3
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100336
Absolute Maximum Ratings(Note 2)
Storage Temperature (TSTG)
−65°C to +150 °C
+150 °C
Maximum Junction Temperature (TJ)
VEE Pin Potential to Ground Pin
Input Voltage (DC)
Recommended Operating
Conditions
Case Temperature (TC)
−7.0V to +0.5V
Output Current (DC Output HIGH)
−50 mA
ESD (Note 3)
≥ 2000V
0°C to +85°C
Commercial
VEE to +0.5V
−40°C to +85°C
Industrial
−5.7V to −4.2V
Supply Voltage (VEE)
Note 2: Absolute maximum ratings are those values beyond which the
device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 3: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
DC Electrical Characteristics (Note 4)
VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C
Symbol
Parameter
Min
Typ
Max
Units
VOH
Output HIGH Voltage
−1025
−955
−870
mV
VIN =VIH (Max)
Conditions
Loading with
VOL
Output LOW Voltage
−1830
−1705
−1620
mV
or VIL (Min)
50Ω to −2.0V
VOHC
Output HIGH Voltage
−1035
mV
VIN = VIH(Min)
Loading with
VOLC
Output LOW Voltage
−1610
mV
or VIL (Max)
50Ω to −2.0V
VIH
Input HIGH Voltage
−1165
−870
mV
Guaranteed HIGH Signal
VIL
Input LOW Voltage
−1830
−1475
mV
Guaranteed LOW Signal
IIL
Input LOW Current
0.50
IIH
Input HIGH Current
IEE
Power Supply Current
for All Inputs
for All Inputs
µA
240
−165
−80
µA
VIN = VIL (Min)
VIN = VIH (Max)
Inputs Open
Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.
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100336
Commercial Version (Continued)
DIP AC Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol
Parameter
TC = 0°C
Min
fSHIFT
Shift Frequency
tPLH
Propagation Delay
tPHL
CP to Qn, Qn
tPLH
Propagation Delay
tPHL
CP to TC (Shift)
tPLH
Propagation Delay
tPHL
CP to TC (Count)
tPLH
Propagation Delay
tPHL
MR to Qn, Qn
tPLH
Propagation Delay
tPHL
MR to TC (Count)
tPHL
Propagation Delay
MR to TC (Shift)
tPLH
Propagation Delay
tPHL
D0/CET to TC
tPLH
Propagation Delay
tPHL
Sn to TC
tTLH
Transition Time
tTHL
20% to 80%, 80% to 20%
tS
Setup Time
tH
tPW(H)
Max
300
TC = +25°C
Min
Max
300
TC = +85°C
Min
Units
Conditions
Max
300
MHz
Figures 2, 3
Figures 1, 3
1.00
2.00
1.00
2.00
1.00
2.00
ns
2.10
3.50
2.10
3.50
2.10
3.70
ns
2.40
4.40
2.40
4.40
2.60
4.70
ns
1.40
2.50
1.40
2.50
1.50
2.60
ns
2.80
5.10
2.90
5.20
3.10
5.50
ns
2.40
4.00
2.40
4.00
2.50
4.10
ns
1.80
3.10
1.80
3.10
1.90
3.30
ns
1.90
4.10
1.90
4.10
2.10
4.40
ns
0.35
1.20
0.35
1.20
0.35
1.20
ns
Figures 1, 3
ns
Figures 6, 4
ns
Figure 6
ns
Figures 3, 4
D3
1.00
1.00
1.00
Pn
1.50
1.50
1.50
D0/CET
1.30
1.30
1.30
CEP
1.40
1.40
1.40
Sn
3.40
3.40
3.40
MR (Release Time)
2.60
2.60
2.60
D3
0.40
0.40
0.40
Pn
0.30
0.30
0.30
D0/CET
0.30
0.30
0.30
CEP
0.20
0.20
0.20
Sn
0.10
0.10
0.10
2.00
2.00
2.00
(Note 5)
Figures 1, 7, 8
(Note 5)
Figures 1, 9
(Note 5)
Figures 1, 4
(Note 5)
Figures 1, 12
(Note 5)
Figures 1, 10, 11
(Note 5)
Figures 1, 5
(Note 5)
Hold Time
Pulse Width HIGH
CP, MR
Note 5: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching.
5
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100336
SOIC and PLCC AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol
Parameter
TC = 0°C
Min
fSHIFT
Shift Frequency
tPLH
Propagation Delay
tPHL
CP to Qn, Qn
tPLH
Propagation Delay
tPHL
CP to TC (Shift)
tPLH
Propagation Delay
tPHL
CP to TC (Count)
tPLH
Propagation Delay
tPHL
MR to Qn, Qn
tPLH
Propagation Delay
tPHL
MR to TC (Count)
tPHL
Propagation Delay
MR to TC (Shift)
tPLH
Propagation Delay
tPHL
D0/CET to TC
tPLH
Propagation Delay
tPHL
Sn to TC
tTLH
Transition Time
tTHL
20% to 80%, 80% to 20%
tS
Setup Time
tH
tPW(H)
350
TC = +25°C
Min
Max
350
TC = +85°C
Min
Units
Conditions
Max
350
MHz
Figures 2, 3
Figures 1, 2
1.00
1.80
1.00
1.80
1.00
1.80
ns
2.10
3.30
2.10
3.30
2.10
3.50
ns
2.40
4.20
2.40
4.20
2.60
4.50
ns
1.40
2.30
1.40
2.30
1.50
2.40
ns
2.80
4.90
2.90
5.00
3.10
5.30
ns
2.40
3.80
2.40
3.80
2.50
3.90
ns
1.80
2.90
1.80
2.90
1.90
3.10
ns
1.90
3.90
1.90
3.90
2.10
4.20
ns
0.35
1.10
0.35
1.10
0.35
1.10
ns
Figures 1, 3
ns
Figures 4, 6
D3
0.90
0.90
0.90
Pn
1.40
1.40
1.40
D0/CET
1.20
1.20
1.20
CEP
1.30
1.30
1.30
Sn
3.30
3.30
3.30
MR (Release Time)
2.50
2.50
2.50
D3
0.30
0.30
0.30
Pn
0.20
0.20
0.20
D0/CET
0.20
0.20
0.20
CEP
0.10
0.10
0.10
Sn
0.00
0.00
0.00
2.00
2.00
2.00
(Note 6)
Figures 1, 7, 8
(Note 6)
Figures 1, 9
(Note 6)
Figures 1, 4
(Note 6)
Figures 1, 12
(Note 6)
Figures 1, 10, 11
(Note 6)
Figures 1, 5
(Note 6)
Hold Time
Pulse Width HIGH
CP, MR
tOSHL
Max
ns
ns
Maximum Skew Common Edge
Output-to-Output Variation
Figure 6
Figures 3, 4
PLCC Only
200
200
200
ps
200
200
200
ps
230
230
230
ps
245
245
245
ps
(Note 7)
Clock to Output Path
tOSLH
Maximum Skew Common Edge
Output-to-Output Variation
PLCC Only
(Note 7)
Clock to Output Path
tOST
Maximum Skew Opposite Edge
Output-to-Output Variation
PLCC Only
(Note 7)
Clock to Output Path
tPS
Maximum Skew
Pin (Signal) Transition Variation
PLCC Only
(Note 7)
Clock to Output Path
Note 6: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching.
Note 7: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite
directions both HL and LH (tOST). Parameters tOST and tps guaranteed by design
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100336
Industrial Version
PLCC DC Electrical Characteristics (Note 8)
VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C
TC = −40°C
TC = 0°C to +85°C
Symbol
Parameter
Min
Max
Min
Max
Units
Conditions
VOH
Output HIGH Voltage
−1085
−870
−1025
−870
mV
VIN =VIH (Max)
Loading with
VOL
Output LOW Voltage
−1830
−1575
−1830
−1620
mV
or VIL (Min)
50Ω to −2.0V
VOHC
Output HIGH Voltage
−1095
mV
VIN = VIH(Min)
Loading with
VOLC
Output LOW Voltage
−1610
mV
or VIL (Max)
50Ω to −2.0V
VIH
Input HIGH Voltage
−1170
−870
−1165
−870
mV
Guaranteed HIGH Signal for All Inputs
VIL
Input LOW Voltage
−1830
−1480
−1830
−1475
mV
Guaranteed LOW Signal for All Inputs
IIL
Input LOW Current
0.50
µA
VIN = VIL (Min)
IIH
Input HIGH Current
IEE
Power Supply Current
−1035
−1565
0.50
240
−165
−75
−165
240
µA
VIN = VIH (Max)
−80
mA
Inputs Open
Note 8: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.
PLCC AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND
Symbol
Parameter
fSHIFT
Shift Frequency
tPLH
Propagation Delay
tPHL
CP to Qn, Qn
tPLH
Propagation Delay
tPHL
CP to TC (Shift)
tPLH
Propagation Delay
tPHL
CP to TC (Count)
tPLH
Propagation Delay
tPHL
MR to Qn, Qn
tPLH
Propagation Delay
tPHL
MR to TC (Count)
tPHL
Propagation Delay
MR to TC (Shift)
tPLH
Propagation Delay
tPHL
D0/CET to TC
tPLH
Propagation Delay
tPHL
Sn to TC
tTLH
Transition Time
tTHL
20% to 80%, 80% to 20%
tS
Setup Time
tH
tPW(H)
TC = −40°C
Min
Max
325
TC = +25°C
Min
Max
350
TC = +85°C
Min
Max
350
Units
MHz
Conditions
Figures 2, 3
Figures 1, 3
1.00
1.80
1.00
1.80
1.00
1.80
ns
2.00
3.30
2.10
3.30
2.10
3.50
ns
2.40
4.20
2.40
4.20
2.60
4.50
ns
1.40
2.30
1.40
2.30
1.50
2.40
ns
2.80
4.90
2.90
5.00
3.10
5.30
ns
2.40
3.80
2.40
3.80
2.50
3.90
ns
1.70
2.90
1.80
2.90
1.90
3.10
ns
1.80
3.90
1.90
3.90
2.10
4.20
ns
0.20
1.90
0.35
1.10
0.35
1.10
ns
Figures 1, 3
ns
Figure 6
ns
Figure 6
ns
Figures 3, 4
D3
1.40
0.90
0.90
Pn
1.70
1.40
1.40
D0/CET
1.80
1.20
1.20
CEP
1.80
1.30
1.30
Sn
3.30
3.30
3.30
MR (Release Time)
2.60
2.50
2.50
D3
0.90
0.30
0.30
Pn
1.00
0.20
0.20
D0/CET
0.70
0.20
0.20
CEP
0.60
0.10
0.10
Sn
0.00
0.00
0.00
2.20
2.00
2.00
(Note 9)
Figures 1, 7, 8
(Note 9)
Figures 1, 9
(Note 9)
Figures 1, 4
(Note 9)
Figures 1, 12
(Note 9)
Figures 1, 10, 11
(Note 9)
Figures 1, 5
(Note 9)
Hold Time
Pulse Width HIGH CP, MR
Note 9: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching.
7
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100336
Test Circuitry
Notes:
VCC, VCCA = +2V, VEE = −2.5V
L1, L2 and L3 = equal length 50Ω impedance lines
RT = 50Ω terminator internal to scope
Decoupling 0.1 µF from GND to VCC and VEE
All unused outputs are loaded with 50Ω to GND
CL = Fixture and stray capacitance ≤ 3 pF
FIGURE 1. AC Test Circuit
Notes:
For shift right mode, +1.05V is applied at S0.
The feedback path from output to input should be as short as possible.
FIGURE 2. Shift Frequency Test Circuit (Shift Left)
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100336
Switching Waveforms
FIGURE 3. Propagation Delay (Clock) and Transition Times
FIGURE 4. Propagation Delay (Reset)
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100336
Switching Waveforms
(Continued)
FIGURE 5. Propagation Delay (Serial Data, Selects)
Notes:
tS is the minimum time before the transition of the clock that information must be present at the data input.
tH is the minimum time after the transition of the clock that information must remain unchanged at the data input.
FIGURE 6. Setup and Hold Time
Note: Shift Right Mode; S0 = H, S1 = H, S2 = L.
FIGURE 7. Propagation Delay, Clock to Terminal Count (Shift Right Mode)
Note: Shift Left Mode; S0 = L, S1 = H, S2 = L.
FIGURE 8. Propagation Delay, Clock to Terminal Count (Shift Left Mode)
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100336
Switching Waveforms
(Continued)
Note:
*Decimal representation of binary outputs.
Count Up: S0 = L, S1 = H, S2 = H; Count Down: S 0 = L, S1 = L, S2 = H.
Measurement taken at 50% point of waveform.
FIGURE 9. Propagation Delay, Clock to Terminal Count (Count Up and Count Down Modes)
Note: Shift Right Mode; S0 = H, S1 = H, S2 = L.
FIGURE 10. Propagation Delay, Master Reset to Terminal Count (Shift Right Mode)
Note: Shift Left Mode; S0 = L, S1 = H, S2 = L.
FIGURE 11. Propagation Delay, Master Reset to Terminal Count (Shift Left Mode)
Note:
*Decimal representation of binary outputs. Count Up Mode: S0 = L, S1 = H, S2 = H.
Note:
*Decimal representation of binary outputs. Count Down Mode: S0 = L, S1 = L, S2 = H.
FIGURE 12. Propagation Delay, Master Reset to Terminal Count (Count Up and Count Down Modes)
11
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100336
Applications
3-Stage Divider, Preset Count Down Mode
Note: If S0 = S1 = S 2 = LOW, then TC = LOW
Slow Expansion Scheme
Fast Expansion Scheme
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100336
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
Package Number N24E
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100336 Low Power 4-Stage Counter/Shift Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Package Number V28A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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