AD ADD8502

a
Integrated LCD
Grayscale Generator
ADD8502
FEATURES
Two Mask Programmable Sets of Five Reference Levels
Dual 10-Bit DACs for Flicker Offset and Range Adjustment
Integrated VCOM Switching
Single-Supply Operation: 5.0 V
Low Supply Current: 300 A
Global Power Save Mode: 1 A Max
Fast Settling Time for Load Change: 20 s
Stable with 20 nF/100 Loads
CMOS/TTL Input Levels
APPLICATIONS
Color TFT Cell Phones
Color TFT PDAs
FUNCTIONAL BLOCK DIAGRAM
REV2
VDD
VP0
VDD
VDD/2
VREF+
10-BIT
DAC A
VREF–
GND
VN0
R
R
VN4
A0
V0
A1
V1
A2
V2
A3
V3
A4
V4
VP0
R
VL
MUX
The ADD8502 is an integrated, high accuracy, programmable
grayscale generator. Two sets of five output reference voltages
are mask programmed to 0.2% resolution. The outputs switch
between the two sets of five levels. The reference levels are selected
from a 512 tap resistor network using a via mask.
ADD8502 includes two serially addressable, 10-bit digital-toanalog converters (DACs) and five fast, low current buffers.
The dual DACs set the endpoint voltages applied to the resistor
network to adjust for flicker and range. The two power save modes
can reduce the total current to less than 1 µA and feature fast
recovery time from Shutdown/Sleep Mode. The ADD8502
accepts CMOS or TTL inputs for all controls, including the
common drive circuit levels.
ADD8502 operates over the industrial temperature range from
–40°C to +85°C and is available in a space-saving 24-lead
4 mm 4 mm frame chip scale package.
SCK
INTERFACE LOGIC
GENERAL DESCRIPTION
DIN
CS-LD
DIGITAL
CORE
VP4
POWER
SAVE
LOGIC
VN4
R
VP4
PSK
R
VN0
GS1
GS2
R
VDD/2
VREF+
10-BIT
DAC B
VREF–
R
VDD
VCOM
LOGIC
COM_M
COM
REV1 CM CV4
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
ADD8502–SPECIFICATIONS (@ V
Parameter
Symbol
SYSTEM ACCURACY
VOUT Error
Swing Error1
Mean Error2
Mean Error between Adjacent Channels3
Mean Error between V0 and V44
DAC ACCURACY
Resolution
Differential Nonlinearity
Integral Nonlinearity5
Offset Error
Gain Error
DD
= 5.0 V, 40C ≤ TA ≤ 85C, unless otherwise noted.)
Conditions
Min
(VPn – VNn) – (VPi – VNi)
(VPn+ VNn)/2 – (VPi + VNi)/2)
DNL
INL
Typ
Max
Unit
3
1
3
3
3
20
17
21
21
25
mV
mV
mV
mV
mV
10
± 0.25
± 0.5
± 0.4
± 0.15
Bits
LSB
LSB
% of FSR
% of FSR
mA
mA
µA
V/µs
µs
V/µs
µs
Degrees
OUTPUT CHARACTERISTICS
Output Current
Short Circuit Current
Output Leakage Current in High-Z Mode
Slew Rate
Settling Time to 1%
Slew Rate5
Settling Time to 1%5
Phase Margin
IOUT
ISC
ILEAKAGE
SR
tS
SR
tS
φo
(VDD – 1 V)
Short to Ground
High-Z Mode
RL = 100 kΩ
V0 to V4 Step Size
LD =100 Ω Series 16 nF
V0 to V4 Step Size
25
60
0.01
1.25
8
0.7
8
67
VCOM SWITCHES ACTIVE IMPEDANCE
COM to VDD
COM to GND
COM to COM_M
COM to V4
Z
Z
Z
Z
See Table IV
25
25
25
25
MASK PROGRAMMABLE
RESISTOR CHAIN
Resistor Matching
RMATCH
POWER SUPPLY
Supply Voltage
Supply Current
Shutdown Supply Current
Sleep Supply Current
Shutdown Recovery Time
Sleep Recovery Time
VDD
ISY
ISY-GLB
ISY-GS1-3
I = 20 mA
Any Two Segments between
512 Resistor String
VDD = 5 V; No Load
Full Shutdown Mode
Mid 3 Buffers Shutdown
Global PD to 1%
V1–V3 Off to 1%
12
12
50
50
50
50
1
4.5
190
140
LOGIC SUPPLY
Logic Input Voltage Level
Logic Input Current
VL
IVL
2.3
DIGITAL I/O
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Current
Digital Input Capacitance
VIH
VIL
IIN
CIN
VL 0.7
GND ≤ VIN ≤ 5.5 V
1.0
Ω
Ω
Ω
Ω
%
5
270
0.2
175
23
10
5.5
400
1
210
30
15
V
µA
µA
µA
µs
µs
3.3
0.01
5.5
1
V
µA
VL 0.3
±1
10
V
V
µA
pF
NOTES
1
Swing error is a comparison of measured V OUT step versus theoretical V OUT step. Theoretical values can be found on the Mask Tap Point Option sheet.
2
Mean error is measured V OUT mean versus theoretical V OUT mean (see Figure 3).
3
Mean errors between two adjacent channels versus theoretical (see Figure 3).
4
Mean errors between V0 and V4 versus theoretical (see Figure 3).
5
Slew rate and settling time are measured between the output resistor and the capacitor (see Figure 1) .
RL
100
Specifications subject to change without notice.
CL
16nF
VCOM
Figure 1. Slew Rate Diagram
–2–
REV. 0
ADD8502
Table I. Serial Data Timing Characteristics
Parameter
Symbol
Min Typ Max
Unit
SCK Cycle Time
SCK High Time
SCK Low Time
CS-LD Setup Time
Data Setup Time
Data Hold Time
LSB SCK High to CS-LD High
Minimum CS-LD High Time
SCK to CS-LD Active Edge Setup Time
CS-LD High to SCK Positive Edge
SCK Frequency (Square Wave)
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
100
45
45
20
5
5
5
10
5
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
10
NOTES
1
All input signals are specified with rise/fall time –5 ns (10% to 90% of V DD) and timed from a voltage level
of (VS + VIH)/2.
2
See Figure 2.
t5
t1
SCK
t9
DIN
C3
t8
t3
t6
C2
t2
X1
t7
t10
X0
t4
CS-LD
Figure 2. Serial Write Interface
VP0
VO
SEE NOTE 2 ON SPECIFICATIONS TABLE
VN0
V0 – V1
SEE NOTE 3 ON SPECIFICATIONS TABLE
VP1
V1
VN1
SEE NOTE 4 ON
SPECIFICATIONS TABLE
VN2
VP2
V2
VN3
SEE NOTE 1 ON SPECIFICATIONS TABLE
V3
VP3
VN4
VP4
V4
Figure 3. Output Wave Form Diagram
REV. 0
–3–
ADD8502
ABSOLUTE MAXIMUM RATINGS*
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VL to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . . . . . . . –0.3 V to +7 V
VOUT to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V
VCOM to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering, 10 sec)
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Package Type
JA1
JB2
Unit
24-Lead LFCSP (ACP)
34.8
13
°C/W
NOTES
1
θJA is specified for worst-case conditions, i.e., θJA is specified for device soldered
in circuit board for surface-mount packages.
2
ψJB is applied for calculating the junction temperature by reference to the board
temperature.
*Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
ADD8502ACP
–40°C to +85°C 24-Lead LFCSP CP-24
Available in 7” reel only.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADD8502 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
ADD8502
24 23
VDD
NC
REV2
GS2
GS1
PSK
PIN CONFIGURATION
22 21 20 19
VL 1
DIN 2
PIN 1
IDENTIFIER
18
V0
17
V1
V2
SCK 3
ADD8502
16
CS-LD 4
TOP VIEW
15
V3
14
V4
13
GND
(Not to Scale)
CM 5
NC
NC
10 11 12
NC
9
COM_M
8
COM
7
REV1
CV4 6
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Name
I/O
Description
Logic Supply Voltage. Connect to supply used for system logic. Can accept 2.7 V to VDD.
When CS is LOW, the input on this pin is shifted into the internal shift register on
the rising edge of SCK.
Accepts up to 10 MHz input. The rising edge on this clock will shift the data on
DIN Pin into the internal shift registers.
When CS-LD is LOW, SCK is enabled for shifting data on the DIN input into the
internal shift register on the rising edge of SCK. Data is loaded MSB first.
When CM is LOW, COM will output the voltage level input on COM_M.
When CM is HIGH, COM levels will be determined by the input on REV1.
If CV4 is HIGH, V4 output is the output of the op amp A4. If CV4 is LOW, V4 is
connected to COM and op amp A4 is shut down. Refer to Table II.
With CM HIGH, a HIGH on REV1 will cause COM to output the voltage level
input at VDD. A LOW on REV1 will cause COM to output the voltage level input
at GND.
Unused Pin
Unused Pin
If CM is LOW, COM will output the voltage input at COM_M. If CM is HIGH,
COM will output the voltage input at VDD when REV1 is HIGH and will output
the voltage input at GND when REV1 is LOW. Refer to Table II.
COM_M is a system voltage reference input between 2.5 V and 3.5 V. This may
be the system 3.3 V supply.
Unused Pin
Ground. Nominally 0 V.
Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF).
When PSK is LOW, these outputs will be Hi-Z.
Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF).
When PSK is LOW or GS1 and GS2 = HIGH, these outputs will be Hi-Z.
Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF).
When PSK is LOW or GS1 and GS2 = HIGH, these outputs will be Hi-Z.
Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF).
When PSK is LOW or GS1 and GS2 = HIGH, these outputs will be Hi-Z.
Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF).
When PSK is LOW, these outputs will be Hi-Z.
Supply Voltage. Nominally 5 V.
Unused Pin
1
2
VL
DIN
Logic Select Pin
Serial Data Input
I
I
3
SCK
Serial Clock
I
4
CS-LD
Load
I
5
CM
I
6
CV4
Logic Control 2
for VCOM
Logic Control V4
7
REV1
Logic Control 1
for VCOM
I
8
9
10
NC
NC
COM
No Connect
No Connect
Common Output
11
COM_M
12
13
14
NC
GND
V4
Common System
VREF
No Connect
Ground
Output
I
O
15
V3
Output
O
16
V2
Output
O
17
V1
Output
O
18
V0
Output
O
19
20
VDD
NC
Supply
No Connect
I
REV. 0
I
O
I
–5–
ADD8502
Pin No. Mnemonic Name
I/O Description
21
REV2
Reference Output
Select
I
22
GS2
Sleep Mode
Select
I
23
GS1
Sleep Mode
Select
I
24
PSK
Global Power
Shutdown
I
When PSK is HIGH and GS1 or GS2 is LOW, then INVERT selects the output
levels on V0 to V4. If INVERT is HIGH, outputs V0 to V4 are connected to
reference levels VP0 to VP4, respectively. If INVERT is LOW, outputs V0 to V4
are connected to reference levels VN0 to VN4, respectively. When PSK is HIGH
and GS1 and GS2 are HIGH, V1–V3 are, Hi-Z state, but V0 and V4 are still
connected to reference levels VP0 and VP4 when INVERT is HIGH. Outputs V0
and V4 switch to VN0 and VN4 when REV is LOW.
When GS1 and GS2 are HIGH, the middle three output buffers are shut down
and V1, V2, and V3 are put into Hi-Z states. Other combinations of GS1 and GS2
leave the outputs of A1 to A3 fully active.
When GS1 and GS2 are HIGH, the middle three output buffers are shut down
and V1, V2, and V3 are Hi-Z. Other combinations of GS1 and GS2 leave the
outputs of A1 to A3 fully active.
When PSK is pulled LOW, the chip will be put into the full Power-Down Mode.
The DACs, resistor ladder network preamps, and output buffers will all be shut
down, and A0 to A4 will be in Hi-Z states. Recovery from full power-down to
normal operation is within 30 µs.
All digital inputs accept CMOS or TTL logic levels.
–6–
REV. 0
Typical Performance Characteristics–ADD8502
250
5
VDD = 5V
DAC B
3
SHUTDOWN CURRENT – A
INTEGRAL NONLINEARITY – %LSB
VDD = 5V
DAC A
1
–1
–3
–5
0
128
256
384
512
640
CODE – LSB
768
896
150
100
50
0
40
1025
25
TEMPERATURE – C
5
190
DAC A
VDD = 5V
VDD = 5V
SLEEP SUPPLY CURRENT – A
185
3
1
1
3
5
DAC B
0
128
256
384
512
640
CODE – LSB
768
896
180
175
170
165
160
155
40
1024
25
TEMPERATURE – C
0.5
350
VDD = 5V
VDD = 5V
DAC A
300
SUPPLY CURRENT – A
0
OFFSET ERROR – LSB
85
TPC 5. Sleep Supply Current vs. Temperature
TPC 2. DAC Differential Nonlinearity
0.5
1.0
1.5
2.0
DAC B
2.5
250
200
150
100
50
3.0
40
25
TEMPERATURE – C
0
40
85
TPC 3. Offset Error vs. Temperature
REV. 0
85
TPC 4. Shutdown Current vs. Temperature
TPC 1. DAC Integral Nonlinearity
DIFFERENTIAL NONLINEARITY – %LSB
200
25
TEMPERATURE – C
TPC 6. Supply Current vs. Temperature
–7–
85
ADD8502
350
10.0
SYSTEM SUPPLY CURRENT – A
VDD = 5V
9.5
SLEEP RECOVERY TIME – s
300
250
200
150
100
9.0
8.5
8.0
7.5
2
4
3
5
6
7.0
40
7
25
TEMPERATURE – C
VDD – V
TPC 7. System Supply Current at Full Power
85
TPC 10. Sleep Recovery Time vs. Temperature
10
400
VDD = 5V
350
SYSTEM SUPPLY CURRENT – nA
8
300
6
LEAKAGE – nA
250
200
150
4
2
100
0
50
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD – V
5.5
6.0
6.5
2
40
7.0
25
TEMPERATURE – C
TPC 8. System Supply Current at Shutdown
85
TPC 11. Output Leakage
28
0
VDD = 5V
VDD = 5V
0
26
0
25
VOLTAGE – 2V/DIV
SHUTDOWN RECOVERY TIME – s
27
24
23
22
REV2
0
0
0
V0
21
0
20
0
19
18
40
25
TEMPERATURE – C
0
85
0
TPC 9. Shutdown Recovery Time vs. Temperature
0
0
0
0
0
0
TIME – 10s/DIV
0
0
0
0
TPC 12. V0 Output Swing Response to REV2
–8–
REV. 0
ADD8502
25
400
VDD = 5V
350
20
FREQUENCY
RON – 300
15
10
250
200
150
100
5
50
0
40
25
TEMPERATURE – C
0
–15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9
OUTPUT VOLTAGE MEAN ERROR
85
TPC 13. VCOM Switch-On-Resistance vs. Temperature
MEAN ERROR BETWEEN ADJACENT CHANNEL – mV
TPC 16. VOUT Swing Mean vs. Distribution
800
700
FREQUNECY
600
500
400
300
200
100
0
–23
–18
–13
–8
–3
2
7
OUTPUT VOLTAGE – mV
12
17
22
TPC 14. VOUT Error Distribution
1.5
VP3–VP4
1.0
0.5
VP2–VP3
0
VP1–VP2
VP0–VP1
–0.5
–1.0
40
25
TEMPERATURE – C
85
MEAN ERROR CHANNEL-TO-CHANNEL – mV
0.6
1.5
V0
1.0
SWING ERROR – mV
2.0
TPC 17. Mean Error between Adjacent Channel
vs. Temperature
2.0
0.5
V1
0
V2
–0.5
V3
–1.0
–1.5
–2.0
V4
–2.5
40
25
TEMPERATURE – C
0.4
0.2
VN2–VN3
0
0.2
0.4
VN3–VN4
VN1–VN2
0.6
0.8
1.0
1.2
1.4
40
85
VN0–VN1
25
TEMPERATURE – C
85
TPC 18. Mean Error between Adjacent Channel
vs. Temperature
TPC 15. Swing Error vs. Temperature
REV. 0
11 13 15
–9–
ADD8502
2.0
10
VDD = 5V
1.5
9
1.0
RISING EDGE
8
0.5
TIME – s
MEAN ERROR V0–V4 – mV
VP0–VP4
0
0.5
1.0
7
6
1.5
FALLING EDGE
VN0–VN4
5
2.0
2.5
40
25
TEMPERATURE – C
4
40
85
45
TEMPERATURE – C
125
TPC 22. Settling Time at VOUT vs. Temperature
TPC 19. Mean Error between V0 and V4 vs. Temperature
5
0
VL = 2.5V
0
SOURCE
4
OUTPUT VOLTAGE – V
VOLTAGE – 500mV/DIV
0
0
VTH HIGH
0
VTH LOW
0
SINK
3
2
0
1
0
0
0
0
0
0
0
0
0
0
TIME – 500mV/DIV
0
0
0
0
0
20
40
60
OUTPUT CURRENT – mA
80
TPC 23. Output Current Source and Sink
TPC 20. REV1 Hysteresis
1.40
VDD = 5V
1.35
SLEW RATE – V/s
1.30
SLEW RATE FALLING
1.25
1.20
SLEW RATE RISING
1.15
1.10
1.05
1.00
40
25
TEMPERATURE – C
85
TPC 21. Slew Rate vs. Temperature
–10–
REV. 0
ADD8502
OPERATION
Transfer Function
The transfer function for the ADD8502 is given in the following
equations:
1. Digital-to-analog transfer function for DAC A. An output can
be derived from Equation 1 as:
D 
V  
VOUTA =  DD   1 + A 
 2 
1024 
(1)
2. Digital-to-analog transfer function for DAC B. An output can
be derived from Equation 2 as:
 D  V 
VOUTB =  B   DD 
 1024   2 
(2)
3. Using any programmed tap point from the 512 resistor string,
the system output can be derived from Equation 3:
 TX 
+ VOUTB
 512 
Equations 1–3 will provide a theoretical calculation of the outputs. The actual will vary with load, process, and architecture.
See Specifications table.
SERIAL INTERFACE
The ADD8502 has a 3-wire serial interface (CS-LD, SCK, and
DIN). The writing sequence begins by bringing the CS-LD line
LOW. Data on the DIN line is clocked into the 16-bit shift register on the rising edge of SCK. The serial clock frequency can be
as high as 10 MHz. When the last data bit is clocked in,
CS-LD line needs to be brought HIGH to load the DAC registers and the operation mode is dependent upon the control bits.
Input Shift Register
Where DA and DB are decimal equivalents of the binary codes
that are loaded to the DAC Register from 0 to 1023.
VTX = (VOUTA − VOUTB )
VOUTA = 4.941 V
VOUTB = 0.244 V
VTX = 4.831 V
(3)
Where TX is any tap point of the 512 resistor string. It is mask
programmable. VTX is the voltage output at any output (VO, ... V4)
and will switch between two voltages depending on the mask
programmed tap points.
Example: VDD = 5 V, DA = 1,000, DB = 100, and TX = 500.
The input shift register is 16 bits wide (see Figure 4). The first
four control bits (C3, C2, C1, and C0) are used to set the different
operating modes of the device. The next 10 bits are the data bits
and the last two bits are “Don’t Cares.” This composes a full word
that is transferred to the DAC register on the rising edge of CS-LD.
In a normal write sequence, the CS-LD line is kept LOW for at
least 16 rising edges of SCK and then it is brought HIGH to
update the DACs. However, if CS-LD is brought HIGH before
the 16th rising edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as invalid.
Neither an update of the DAC register contents nor a change in
the operation mode occurs.
DB0 (LSB)
DB15 (MSB)
C3
C2
C1
CONTROL BITS
C0
D9
D8
D7
D6
D5
D4
D3
DATA BITS
Figure 4. Input Register Contents
REV. 0
–11–
D2
D1
D0
X1
X0
DON’T
CARE
ADD8502
Table II. DAC Control Function
Control Code
C3 C2 C1 C0
Status
Input Register
Status
DAC Register
(Sleep/Wake)
Power-Down Status
Comments
0
0
0
0
No Change
No Update
No Change
No operation; power-down status unchanged
(part stays in Wake or Sleep Mode).
0
0
0
1
Load DAC A
No Update
No Change
Load input Register A with data. DAC outputs
unchanged. Power-down status unchanged.
0
0
1
0
Load DAC B
No Update
No Change
Load input Register B with data. DAC outputs
unchanged. Power-down status unchanged.
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1
0
0
0
No Change
Update Outputs
Wake
Load both DAC registers with existing contents
of input registers. Update DAC outputs. Part
wakes up.
1
0
0
1
Load DAC A
Update Outputs
Wake
Load input Register A. Load DAC registers with
new contents of input register A and existing
contents of Register B. Update DAC outputs.
Part wakes up.
1
0
1
0
Load DAC B
Update Outputs
Wake
Load input Register B. Load DAC registers with
new contents of input Register B and existing
contents of Register A. Update DAC outputs.
Part wakes up.
1
1
0
1
1
0
1
0
1
1
0
1
No Change
No Update
Wake
Part wakes up. Input and DAC registers
unchanged. DAC outputs reflect existing
contents of DAC registers.
1
1
1
0
No Change
No Update
Sleep
Power down the IC, put in into Sleep Mode.
1
1
1
1
Load DACs
A, B with Same
10-Bit Code
Update
Outputs
Wake
Load both input registers. Load both DAC
registers with new contents of input registers.
Update DAC outputs. Part wakes up.
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Modes of Operation
The ADD8502 has various modes of operation, such as updating
both DACs simultaneously or changing the power-down status
(Sleep/Wake). These are selected by writing the appropriate
4-bit control code (C0–C3). The details for each mode are
summarized in Table II.
Low Power Serial Interface
To reduce the power consumption of the device ever further, the
interface only powers up fully when the device is being written
to. As soon as the 16-bit control word has been written to the
part, the SCK and DIN input buffers are powered down. They
only power up again following a falling edge of CS-LD.
Double-Buffered Interface
The ADD8502 has double-buffered interfaces consisting of two
banks of registers: input and DAC. The input register is connected directly to the input shift register, and the digital code is
transferred to the relevant input register on completion of a
valid write sequence. The DAC register contains the digital
code used by the resistor string.
Access to the DAC register is controlled by the control codes,
C0 to C3. The user can update both DACs simultaneously as
well as individually. It depends on the selected control codes to
update individual output or both outputs simultaneously.
Initial Power-Up Condition
The ADD8502 has preset DAC conditions when its initially
powered on. The DACs are loaded with 1110 1011 11 for the
upper DAC and 0000 1010 00 for the lower DAC. The part is
powered up in a normal operation mode (Wake Status).
Power-Down Modes
The ADD8502 has two shutdown modes. One mode is to fully
shut down the device using PSK or the digital serial control code,
and the other mode is to shut down V1 to V3 buffers using GS1
and GS2. See Table III for the priority of the shutdown control
functions.
–12–
REV. 0
ADD8502
The ADD8502 will have a quiescent current less than 1 µA when
it is fully shut down and all output buffers are switched to a high
impedance state. The only active circuitries are the digital logics
and the latches for the serial control. When the device is brought
back from Sleep Mode to normal operation, it will use the last
serial word to update the DACs or a new control code or data if
any was loaded when the part was in Sleep Mode; i.e., the contents
of the input register, DAC register, and power-down status shown
in Table II is retained as long as VDD and VL are on.
The second power save mode (mid 3 buffers are shut down) is
using GS1 and GS2. In a condition where both GS1 and GS2
logics are HIGH, the output buffers (V1, V2, and V3) are shut
down and switched into a high impedance state.
Table III. Shutdown Control Function
VCOM Logic
VCOM operation is described in Table IV. The VCOM logic is
always active and its logic inputs are CM, REV1, and CV4.
When CM is LOW, COM is connected to COM_M. When CM
is HIGH, COM is determined by the logic input of REV1. If
REV1 is HIGH, COM is connected to VDD. When REV1 is
LOW, COM is connected to GND.
CV4 controls the V4 output. If CV4 goes LOW, V4 is connected
to COM and A4 is shut down with its output in a Hi-Z state.
When CV4 is HIGH, the switch connecting V4 to COM is open
and A4 is in normal operation mode.
Table IV. VCOM Logic Control
Inputs
Outputs
CM
REV1
CV4
VCOM
V4
L
X
L
COM_M
COM
Normal Operation
L
X
H
COM_M
A4
H
Normal Operation
H
L
L
GND
COM
H
L
Normal Operation
H
H
L
VDD
COM
Wake
H
H
Mid 3 Buffers are Shutdown
H
L
H
GND
A4
H
Sleep
X
X
Full Shutdown
H
H
H
VDD
A4
L
X
X
X
Full Shutdown
X = Don’t Care
PSK
Serial
Control
GS1
GS2
Operation
Mode
H
Wake
L
L
H
Wake
L
H
Wake
H
X = Don’t Care
REV. 0
–13–
ADD8502
VL
VDD
SCK
LOGIC LEVEL
TRANSLATOR
DIN
LOGIC LEVEL
TRANSLATOR
CS-LD
LOGIC LEVEL
TRANSLATOR
PSK
LOGIC LEVEL
TRANSLATOR
GS1
LOGIC LEVEL
TRANSLATOR
V0
V1
V2
V3
ADD8502
CORE
GS2
V4
LOGIC LEVEL
TRANSLATOR
COM
REV1
LOGIC LEVEL
TRANSLATOR
REV2
LOGIC LEVEL
TRANSLATOR
CM
LOGIC LEVEL
TRANSLATOR
CV4
LOGIC LEVEL
TRANSLATOR
COM_M
VL
VDD
GND
Figure 5. CST ESD and Logic Level Translation Scheme
ADD8502 Description
•
The ADD8502 uses logic level translators to convert external
logic levels to levels suitable for use in the ADD8502 core.
•
The logic level translators are intended to be powered from
the same supply voltage as is used to power the external
logic driving the ADD8502.
•
VDD may be powered down while normal voltages are present
on the VL and logic input pins.
•
VDD and VL are independent and can be in the range 0 V to
5.5 V.
•
No damage to the digital inputs will occur with applied
voltages up to 7 V (see Absolute Maximum Ratings section
of data sheet).
•
No current will flow between VDD and VL under normal
operating conditions.
•
Logic voltages can be present on the logic input pins even if
VL is powered down. Inputs are limited by max supply rating
of 7 V.
•
Digital input pins have ESD protection connected to GND.
•
All other input and output pins have ESD protection connected
to GND and VDD.
–14–
REV. 0
ADD8502
VOUTA
ADD8502-000 MASK OPTION
DAC A
Table V. Default Power-Up Conditions
DAC Setpoints (0 ≤ D ≤ 1023)
Upper DAC
Lower DAC
Decimal Code
Voltage
Unit
943
40
4.8022
0.0977
V
V
Resistor Tap Points (0 ≤ X ≤ 512)
Tap Point
Voltage
Unit
450
271
203
137
3
31
215
290
367
509
4.2325
2.5878
1.9630
1.3565
0.1252
0.3825
2.0732
2.7624
3.4699
4.7747
V
V
V
V
V
V
V
V
V
V
VP0
VN4
VP1
VN3
VP2
VN2
VP3
VN1
VP4
VN0
DAC B
VP0
VP1
VP2
VP3
VP4
VN0
VN1
VN2
VN3
VN4
Supply voltage = 5 V
REV. 0
VOUTB
Figrue 6. Tap Point References
Tap point voltages can be derived from the following equation:
X
[VOUTA − VOUTB ]
512
Where VOUTA and VOUTB can be derived from the transfer functions under the Operation Section of the datasheet.
Vx = VOUTB +
The ADD8502 uses a single resistor string consisting of 512
individual elements. Both sets of reference voltages (VP0–VP4,
VN0–VN4) are generated from this single string. Two separate
resistor networks are shown to demonstrate the tap points, which
are changeable by mask option and completely independent of
each other.
–15–
ADD8502
OUTLINE DIMENSIONS
0.60 MAX
4.0
BSC SQ
PIN 1
INDICATOR
12 MAX
0.25
MIN
0.60 MAX
0.50
BSC
3.75
BSC SQ
TOP
VIEW
0.50
0.40
0.30
BOTTOM
VIEW
13
12
7
PIN 1
INDICATOR
1
24
19
18
6
2.25
1.70
0.75
2.50
REF
0.70 MAX
0.65 NOM
0.05 MAX
0.02 NOM
0.25
REF
SEATING
PLANE
0.30
0.23
0.18
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
PRINTED IN U.S.A.
1.00
0.90
0.85
C02944–0–8/02(0)
24-Lead Frame Chip Scale Package [LFCSP]
4x4 mm Body
(CP-24)
–16–
REV. 0