DAC8534 DAC 8534 ® SBAS254D – SEPTEMBER 2002 – REVISED MARCH 2004 Quad Channel, Low Power, 16-Bit, Serial Input DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION ● ● ● ● ● ● ● The DAC8534 is a quad channel, 16-bit Digital-to-Analog Converter (DAC) offering low-power operation and a flexible serial host interface. Each on-chip precision output amplifier allows rail-to-rail output swing to be achieved over the supply range of 2.7V to 5.5V. The device supports a standard 3-wire serial interface capable of operating with input data clock frequencies up to 30MHz for IOVDD = 5V. ● ● ● ● ● POWER SUPPLY: +2.7V to +5.5V microPOWER OPERATION: 950µA at 5V 16-BIT MONOTONIC OVER TEMPERATURE SETTLING TIME: 10µs to ±0.003% FSR ULTRA-LOW AC CROSSTALK: –100dB typ POWER-ON RESET TO ZERO-SCALE ON-CHIP OUTPUT BUFFER AMPLIFIER WITH RAIL-TO-RAIL OPERATION DOUBLE BUFFERED INPUT ARCHITECTURE SIMULTANEOUS OR SEQUENTIAL OUTPUT UPDATE AND POWER-DOWN 16 CHANNEL BROADCAST CAPABILITY SCHMITT-TRIGGERED INPUTS TSSOP-16 PACKAGE The DAC8534 requires an external reference voltage to set the output range of each DAC channel. Also incorporated into the device is a power-on reset circuit which ensures that the DAC outputs power up at zero-scale and remain there until a valid write takes place. The DAC8534 provides a per channel power-down feature, accessed over the serial interface, that reduces the current consumption to 200nA per channel at 5V. The low-power consumption of this device in normal operation makes it ideally suited to portable battery-operated equipment and other low-power applications. The power consumption is 5mW at 5V, reducing to 4µW in power-down mode. APPLICATIONS ● ● ● ● ● ● PORTABLE INSTRUMENTATION CLOSED-LOOP SERVO-CONTROL PROCESS CONTROL DATA ACQUISITION SYSTEMS PROGRAMMABLE ATTENUATION PC PERIPHERALS The DAC8534 is available in a TSSOP-16 package with a specified operating temperature range of –40°C to +105°C. AVDD IOVDD VREFH Data Buffer A DAC Register A VOUTA DAC A VOUTB VOUTC DAC Register D Data Buffer D VOUTD DAC D 18 SYNC SCLK DIN 24-Bit Serial-toParallel Shift Register GND Buffer Control Register Control Power-Down Control Logic Resistor Network 8 A0 A1 LDAC ENABLE VREFL Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. Copyright © 2002-2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) AVDD to GND ........................................................................ –0.3V to +6V Digital Input Voltage to GND ............................... –0.3V to +AVDD + 0.3V VOUTA to VOUTD to GND .................................... –0.3V to + AVDD + 0.3V Operating Temperature Range ...................................... –40°C to +105°C Storage Temperature Range ......................................... –65°C to +150°C Junction Temperature Range (TJ max) ........................................ +150°C Power Dissipation .......................................................... (TJ max – TA)/θJA θJA Thermal Impedance ......................................................... 118°C/W θJC Thermal Impedance ........................................................... 29°C/W Lead Temperature, Soldering: Vapor Phase (60s) ............................................................... +215°C Infrared (15s) ........................................................................ +220°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION PRODUCT DAC8534 PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFICATION TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY TSSOP-16 PW –40°C to +105°C D8534I " " " " DAC8534IPW DAC8534IPWR Tube, 90 Tape and Reel, 2000 " NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. ELECTRICAL CHARACTERISTICS AVDD = +2.7V to +5.5V, –40°C to +105°C, unless otherwise specified. DAC8534 PARAMETER CONDITIONS MIN TYP MAX UNITS PERFORMANCE (1) STATIC Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Zero-Scale Error Drift Full-Scale Error Gain Error Gain Temperature Coefficient Channel-to-Channel Matching PSRR OUTPUT CHARACTERISTICS (2) Output Voltage Range Output Voltage Settling Time Slew Rate Capacitive Load Stability Code Change Glitch Impulse Digital Feedthrough DC Crosstalk AC Crosstalk DC Output Impedance Short-Circuit Current Power-Up Time AC PERFORMANCE SNR (1st 19 Harmonics Removed) THD SFDR SINAD 16 16-Bit Monotonic 0.25 +5 ±7 –0.15 ±3 8 0.75 RL = 2kΩ, CL = 200pF 0 To ±0.003% FSR 0200H to FD00H RL = 2kΩ; 0pF < CL < 200pF RL = 2kΩ; CL = 500pF RL = ∞ RL = 2kΩ 1LSB Change Around Major Carry 1kHz sine Wave AVDD = +5V AVDD = +3V Coming Out of Power-Down Mode AVDD = +5V Coming Out of Power-Down Mode AVDD = +3V BW = 20kHz, AVDD = 5V FOUT = 1kHz 8 12 1 470 1000 20 0.5 0.25 –100 1 50 20 ±0.0987 ±1 +20 –1.0 ±1.0 VREFH 10 –96 Bits % of FSR LSB mV µV/°C % of FSR % of FSR ppm of FSR/°C mV mV/V V µs µs V/µs pF pF nV-s nV-s LSB dB Ω mA mA 2.5 µs 5 µs 94 67 69 65 dB dB dB dB NOTES: (1) Linearity calculated using a reduced code range of 485 to 64714; output unloaded. (2) Ensured by design and characterization, not production tested. DAC8534 2 www.ti.com SBAS254D ELECTRICAL CHARACTERISTICS (Cont.) AVDD = +2.7V to +5.5V, –40°C to +105°C, unless otherwise specified. DAC8534 PARAMETER CONDITIONS REFERENCE INPUT Reference Current MIN VREF = AVDD = +5V VREF = AVDD = +3V Reference Input Range Reference Input Impedance TYP MAX UNITS 135 80 180 120 AVDD µA µA V kΩ ±1 0.8 0.6 3 µA V V V V pF 5.5 5.5 V V 0 37 LOGIC INPUTS (2) Input Current VINL, Input LOW Voltage VINL, Input LOW Voltage VINH, Input HIGH Voltage VINH, Input HIGH Voltage Pin Capacitance IOVDD IOVDD IOVDD IOVDD POWER REQUIREMENTS AVDD IOVDD AIDD (normal mode) IOIDD = = = = +5V +3V +5V +3V 2.4 2.1 2.7 2.7 DAC Active and Excluding Load Current AIDD = +3.6V to +5.5V AIDD = +2.7V to +3.6V AIDD (all power-down modes) AIDD = +3.6V to +5.5V AIDD = +2.7V to +3.6V 10 20 µA VIH = IOVDD and VIL = GND VIH = IOVDD and VIL = GND 0.95 0.9 1.6 1.5 mA mA VIH = IOVDD and VIL = GND VIH = IOVDD and VIL = GND 0.8 0.05 1 1 µA µA ILOAD = 2mA, AVDD = +5V 89 POWER EFFICIENCY IOUT/IDD TEMPERATURE RANGE Specified Performance –40 % +105 °C NOTES: (1) Linearity calculated using a reduced code range of 485 to 64714; output unloaded. (2) Ensured by design and characterization, not production tested. PIN CONFIGURATION PIN DESCRIPTIONS Top View TSSOP VOUTA 1 PIN NAME DESCRIPTION 1 VOUTA Analog output voltage from DAC A. 2 VOUTB Analog output voltage from DAC B. 2 VREFH Positive reference voltage input. 4 AVDD Power supply input, +2.7V to +5.5V. 5 VREFL Negative reference voltage input. 6 GND 7 VOUTC 8 VOUTD Analog output voltage from DAC D. 9 SYNC Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes LOW, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock (unless SYNC is taken HIGH before this edge in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC8534). 10 SCLK Serial Clock Input. Data can be transferred at rates up to 30MHz. 11 DIN Serial Data Input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock input. 12 13 14 15 IOVDD A0 A1 ENABLE 16 LDAC Digital Input-Output Power Supply Address 0 — sets device address, see Table II. Address 1 — sets device address, see Table II. Active LOW, ENABLE LOW connects the SPI interface to the serial port. Load DACs, rising edge triggered loads all DAC registers. 16 LDAC VOUTB 2 15 ENABLE VREFH 3 14 A1 AVDD 4 13 A0 VREFL 5 12 IOVDD GND 6 11 DIN VOUTC 7 10 SCLK VOUTD 8 9 DAC8534 SYNC DAC8534 SBAS254D Ground reference point for all circuitry on the part. Analog output voltage from DAC C. 3 www.ti.com TIMING CHARACTERISTICS(1, 2) AVDD = +2.7V to +5.5V; all specifications –40°C to +105°C unless otherwise noted. DAC8534 PARAMETER DESCRIPTION CONDITIONS MIN SCLK Cycle Time IOVDD = AVDD = 2.7V to 3.6V IOVDD = AVDD = 3.6V to 5.5V 50 33 ns ns t2 SCLK HIGH Time IOVDD = AVDD = 2.7V to 3.6V IOVDD = AVDD = 3.6V to 5.5V 26 15 ns ns t3 SCLK LOW Time IOVDD = AVDD = 2.7V to 3.6V IOVDD = AVDD = 3.6V to 5.5V 22.5 13 ns ns t4 SYNC Falling Edge to SCLK Rising Edge Setup Time IOVDD = AVDD = 2.7V to 3.6V IOVDD = AVDD = 3.6V to 5.5V 0 0 ns ns t5 Data Setup Time IOVDD = AVDD = 2.7V to 3.6V IOVDD = AVDD = 3.6V to 5.5V 5 5 ns ns t6 Data Hold Time IOVDD = AVDD = 2.7V to 3.6V IOVDD = AVDD = 3.6V to 5.5V 4.5 4.5 ns ns t7 24th SCLK Falling Edge to SYNC Rising Edge IOVDD = AVDD = 2.7V to 3.6V IOVDD = AVDD = 3.6V to 5.5V 0 0 ns ns t8 Minimum SYNC HIGH Time IOVDD = AVDD = 2.7V to 3.6V IOVDD = AVDD = 3.6V to 5.5V 50 33 ns ns t9 24th SCLK Falling Edge to SYNC Falling Edge IOVDD = AVDD = 2.7V to 5.5V 130 ns t1 (3) TYP MAX UNITS NOTES: (1) All input signals are specified with tR = tF = 3ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2. (2) See Serial Write Operation timing diagram, below. (3) Maximum SCLK frequency is 30MHz at IOVDD = AVDD = +3.6V to +5.5V and 20MHz at IOVDD = AVDD = +2.7V to +3.6V. SERIAL WRITE OPERATION t1 SCLK t9 1 24 t8 t3 t4 t2 t7 SYNC t6 t5 DIN DB23 DB0 DB23 DAC8534 4 www.ti.com SBAS254D TYPICAL CHARACTERISTICS At TA = +25°C, unless otherwise noted. 64 48 32 16 0 –16 –32 –48 –64 CHANNEL A LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE AVDD = 5V LE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 0.5 0.0 –0.5 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE CHANNEL C AVDD = 5V 64 48 32 16 0 –16 –32 –48 –64 CHANNEL D AVDD = 5V 1.0 DLE (LSB) DLE (LSB) 0.5 0.0 –0.5 0.0 –0.5 Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE CHANNEL A AVDD = 2.7V 64 48 32 16 0 –16 –32 –48 –64 CHANNEL B AVDD = 2.7V 1.0 DLE (LSB) 1.0 0.5 0.0 –0.5 –1.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code 0.5 0.0 –0.5 –1.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code DAC8534 SBAS254D 0.5 –1.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH LE (LSB) LE (LSB) 0.0 –0.5 Digital Input Code –1.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) 0.5 Digital Input Code 1.0 64 48 32 16 0 –16 –32 –48 –64 AVDD = 5V –1.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH LE (LSB) LE (LSB) –1.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 64 48 32 16 0 –16 –32 –48 –64 CHANNEL B 1.0 DLE (LSB) DLE (LSB) 1.0 64 48 32 16 0 –16 –32 –48 –64 5 www.ti.com TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE CHANNEL C 64 48 32 16 0 –16 –32 –48 –64 AVDD = 2.7V LE (LSB) LE (LSB) 64 48 32 16 0 –16 –32 –48 –64 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE AVDD = 2.7V 1.0 0.5 DLE (LSB) DLE (LSB) 1.0 CHANNEL D 0.0 –0.5 0.5 0.0 –0.5 –1.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH –1.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code ZERO-SCALE ERROR vs TEMPERATURE ZERO-SCALE ERROR vs TEMPERATURE 10 10 CH D AVDD = VREF = 5V CH C AVDD = VREF = 2.7V 8 8 Error (mV) Error (mV) 6 6 4 CH A CH C CH B CH D 4 2 2 0 CH B 0 –40 CH A –10 20 50 80 –2 –40 110 –10 20 110 20 CH C 15 15 CH D CH C CH D To avoid clipping of the output signal during the test, VREF = AVDD – 10mV, AVDD = 2.7V, VREF = 2.69V 10 To avoid clipping of the output signal during the test, VREF = AVDD – 10mV, AVDD = 5V, VREF = 4.99V Error (mV) 10 Error (mV) 80 FULL-SCALE ERROR vs TEMPERATURE FULL-SCALE ERROR vs TEMPERATURE 20 5 50 Temperature (°C) Temperature (°C) CH B 5 0 0 –5 –5 CH A CH B CH A –10 –40 –10 20 50 80 –10 –40 110 –10 20 50 80 110 Temperature (°C) Temperature (°C) DAC8534 6 www.ti.com SBAS254D TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, unless otherwise noted. SINK CURRENT CAPABILITY (ALL CHANNELS) 0.150 SOURCE CURRENT CAPABILITY (ALL CHANNELS) 5.00 VREF = AVDD – 10mV DAC loaded with 0000H 0.125 VREF = AVDD – 10mV DAC Loaded with FFFFH AVDD = 5V 4.95 VOUT (V) VOUT (V) 0.100 0.075 AVDD = 5V 4.90 0.050 4.85 0.025 AVDD = 2.7V 0.000 4.80 0 1 2 3 4 0 5 1 2 3 4 5 ISOURCE (mA) ISINK (mA) SUPPLY CURRENT vs DIGITAL INPUT CODE SOURCE CURRENT CAPABILITY (ALL CHANNELS) 2.70 1200 VREF = AVDD – 10mV DAC Loaded with FFFFH AVDD = 2.7V 2.65 AVDD = VREF = 5V 1000 AIDD (µA) VOUT (V) 800 2.60 600 AVDD = VREF = 2.7V 400 2.55 200 0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 2.50 0 1 2 3 4 5 ISOURCE (mA) Digital Input Code SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 1000 1200 AVDD = VREF = 5V 950 1000 900 AIDD (µA) AIDD (µA) 800 AVDD = VREF = 2.7V 600 400 Reference Current Included All Channels Powered, No Load. 850 800 750 700 200 650 600 0 –40 –10 20 50 80 2.7 110 Temperature (°C) DAC8534 SBAS254D 3.05 3.4 3.75 4.1 4.45 AVDD (V) 4.8 5.15 5.5 7 www.ti.com TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, unless otherwise noted. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE HISTOGRAM OF CURRENT CONSUMPTION 1750 1500 TA = 25°C, SYNC Input (All others inputs = GND) Reference Current Included 1650 AVDD = VREF = 5V Reference Current Included 1450 1000 AVDD = VREF = 5V 1350 Frequency AIDD + IOIDD (µA) 1550 1250 1150 500 1050 AVDD = VREF = 2.7V 950 850 750 1150 1120 VLOGIC (V) 1090 5.0 1060 4.5 1030 4.0 1000 3.5 970 3.0 940 2.5 910 2.0 880 1.5 850 1.0 790 0.5 820 0 0 AIDD (µA) HISTOGRAM OF CURRENT CONSUMPTION 1500 5.5 AVDD = VREF = 2.7V Reference Current Included 5.0 4.5 EXITING POWER-DOWN MODE AVDD = VREF = 5V Power-Up Code = FFFFH 4.0 Frequency VOUT (V) 1000 3.5 3.0 2.5 2.0 1.5 500 1.0 0.5 0.0 –0.5 Time (3µs/div) 1060 1030 1000 970 940 910 880 850 820 790 760 730 0 AIDD (µA) OUTPUT GLITCH (Worst Case) OUTPUT GLITCH (Mid-Scale) 2.52 VOUT (V, 10mV/div) 2.51 2.50 AVDD = VREF = 5V Code 7FFFH to 8000H to 7FFFH (Glitch Occurs Every N • 4096 Code Boundary) 2.49 2.48 2.47 2.46 4.72 4.70 4.68 VOUT (V, 20mV/div) 2.53 AVDD = VREF = 5V Code EFFFH to F000H to EFFFH (Glitch Occurs Every N • 4096 Code Boundary) 4.66 4.64 4.62 4.60 4.58 2.45 4.56 2.44 4.54 2.43 Time (1µs/div) Time (1µs/div) DAC8534 8 www.ti.com SBAS254D TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, unless otherwise noted. ABSOLUTE ERROR 20 AVDD = VREF = 5V TA = 25°C 16 Output Error (mV) 14 6 Channel D Output Channel B Output 12 10 8 6 4 Channel B Output Channel D Output 2 0 –2 –4 Channel A Output –8 Channel C Output –10 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Channel C Output 0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code FULL-SCALE SETTLING TIME (Large Signal) HALF-SCALE SETTLING TIME (Large Signal) 6 3.0 AVDD = VREF = 5.5V Output Loaded with 2kΩ and 200pF to GND 5 AVDD = VREF = 5V Output Loaded with 2kΩ and 200pF to GND 2.5 2.0 VOUT (V) 4 VOUT (V) 4 –6 Channel A Output 2 3 1.5 2 1.0 1 0.5 0 0 Time (12µs/div) Time (12µs/div) FULL-SCALE SETTLING TIME (Large Signal) HALF-SCALE SETTLING TIME 3.5 AVDD = VREF = 2.7V Output Loaded with 2kΩ and 200pF to GND 3.0 1.5 VOUT (V) 2.5 VOUT (V) AVDD = VREF = 2.7V TA = 25°C 8 Output Error (mV) 18 ABSOLUTE ERROR 10 2.0 1.5 1.0 1.0 0.5 AVDD = VREF = 2.7V Output Loaded with 2kΩ and 200pF to GND 0.5 0 0 Time (12µs/div) Time (12µs/div) DAC8534 SBAS254D 9 www.ti.com TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, unless otherwise noted. SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY 98 0 AVDD = VREF = 5V FS = 52ksps, –1dB FSR Digital Input Measurement Bandwidth = 20kHz –10 96 –20 AVDD = 5V 94 –30 THD (dB) SNR (dB) TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY 92 AVDD = 2.7V 90 –40 THD –50 –60 –70 88 AVDD = VREF –1dB FSR Digital Input, FS = 52ksps Measurement Bandwidth = 20kHz 86 –80 3rd-Harmonic –90 84 2nd-Harmonic –100 0 500 1.0k 1.5k 2.0k 2.5k 3.0k 3.5k 4.0k 4.5k 0 500 1.0k Output Frequency (Hz) 4.0k AVDD = VREF = 2.7V FS = 52ksps, –1dB FSR Digital Input Measurement Bandwidth = 20kHz –10 –20 Output Voltage –30 THD (dB) 3.5k FULL-SCALE SETTLING TIME (Small-Signal-Positive Going Step) TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY 0 1.5k 2.0k 2.5k 3.0k Output Frequency (Hz) –40 THD –50 –60 –70 Small-Signal Settling Time 5mV/div –80 Trigger Pulse –90 2nd-Harmonic 3rd-Harmonic –100 0 500 1.0k 1.5k 2.0k 2.5k 3.0k Output Frequency (Hz) 3.5k 4.0k Time (2µs/div) Output Voltage FULL-SCALE SETTLING TIME (Small-Signal-Negative Going Step) Small-Signal Settling Time 5mV/div Trigger Pulse Time (2µs/div) DAC8534 10 www.ti.com SBAS254D THEORY OF OPERATION VREFH DAC SECTION RDIVIDER The architecture of each channel of the DAC8534 consists of a resistor-string DAC followed by an output buffer amplifier. Figure 1 shows a simplified block diagram of the DAC architecture. VREFH 50kΩ VREF 2 R R 50kΩ To Output Amplifier (2x Gain) 70kΩ DAC Register VOUT REF (+) Resistor String REF(–) VREFL R FIGURE 1. DAC8534 Architecture. R The input coding for each device is unipolar straight binary, so the ideal output voltage is given by: VOUT X = 2 • VREFL + (VREF H − VREF L) • VREFL DIN 65536 FIGURE 2. Resistor String. where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 65535. VOUTX refers to channel A or through D. RESISTOR STRING The resistor string section is shown in Figure 2. It is simply a divide-by-2 resistor followed by a string of resistors. The code loaded into the DAC register determines at which node on the string the voltage is tapped off. This voltage is then applied to the output amplifier by closing one of the switches connecting the string to the amplifier. OUTPUT AMPLIFIER Each output buffer amplifier is capable of generating rail-torail voltages on its output which approaches an output range of 0V to AVDD (gain and offset errors must be taken into account). Each buffer is capable of driving a load of 2kΩ in parallel with 1000pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical characteristics. SERIAL INTERFACE The DAC8534 uses a 3-wire serial interface (SYNC, SCLK, and DIN), which is compatible with SPI™, QSPI™, and Microwire™ interface standards, as well as most DSPs. See the Serial Write Operation timing diagram for an example of a typical write sequence. The write sequence begins by bringing the SYNC line LOW. Data from the DIN line is clocked into the 24-bit shift register on each falling edge of SCLK. The serial clock frequency can be as high as 30MHz, making the DAC8534 compatible with highspeed DSPs. On the 24th falling edge of the serial clock, the last data bit is clocked into the shift register and the shift register gets locked. Further clocking does not change the shift register data. Once 24 bits are locked into the shift register, the 8MSBs are used as control bits and the 16LSBs are used as data. After receiving the 24th falling clock edge, DAC8534 decodes the 8 control bits and 16 data bits to perform the required function, without waiting for a SYNC rising edge. A new SPI sequence starts at the next falling edge of SYNC. A rising edge of SYNC before the 24-bit sequence is complete resets the SPI interface; no data transfer occurs. At this point, the SYNC line may be kept LOW or brought HIGH. In either case, the minimum delay time from the 24th falling SCLK edge to the next falling SYNC edge must be met in order to properly begin the next cycle. To assure the lowest power consumption of the device, care should be taken that the digital input levels are as close to each rail as possible. (Please refer to the “Typical Characteristics” section for the “Supply Current vs Logic Input Voltage” transfer characteristic curve.) IOVDD AND VOLTAGE TRANSLATORS The IOVDD pin powers the digital input structures of the DAC8534. For single-supply operation, it could be tied to AVDD. For dual-supply operation, the IOVDD pin provides interface flexibility with various CMOS logic families and it should be connected to the logic supply of the system. Analog circuits and internal logic of the DAC8534 use AVDD as the supply voltage. The external logic high inputs get translated to AVDD by level shifters. These level shifters use the IOVDD voltage as a DAC8534 SBAS254D 11 www.ti.com reference to shift the incoming logic HIGH levels to AVDD. IOVDD is ensured to operate from 2.7V to 5.5V regardless of the AVDD voltage, which ensures compatibility with various logic families. Although specified down to 2.7V, IOVDD will operate at as low as 1.8V with degraded timing and temperature performance. For lowest power consumption, logic VIH levels should be as close as possible to IOVDD, and logic VIL levels should be as close as possible to GND voltages. INPUT SHIFT REGISTER The input shift register (SR) of the DAC8534 is 24 bits wide, as shown in Figure 3, and is made up of 8 control bits (DB16-DB23) and 16 data bits (DB0-DB15). The first two control bits (DB22 and DB23) are the address match bits. The DAC8534 offers additional hardware-enabled addressing capability allowing a single host to talk to up to four DAC8534s through a single SPI bus without any glue logic, enabling up to 16-channel operation. The state of DB23 should match the state of pin A1; similarly, the state of DB22 should match the state of pin A0. If there is no match, the control command and the data (DB21...DB0) are ignored by the DAC8534. That is, if there is no match, the DAC8534 is not addressed. Address matching can be overridden by the broadcast update, as will be explained. DAC8534s get updated with previously stored data (or powerdown). If DB18 = 1, then SR data (or power-down) updates all channels of all DAC8534s in the system. This broadcast update feature allows the simultaneous update of up to 16 channels. Power-down/data selection is as follows: DB16 is a power-down flag. If this flag is set, then DB15 and DB14 select one of the four power-down modes of the device as described in Table I. If DB16 = 1, DB15 and DB14 no longer represent the two MSBs of data, they represent a power-down condition described in Table I. Similar to data, power-down conditions can be stored at the temporary registers of each DAC. It is possible to update DACs simultaneously either with data, power-down, or a combination of both. Please refer to Table II for more information. PD0 (DB16) PD1 (DB15) PD2 (DB14) OPERATING MODE 1 0 0 Output High Impedance 1 0 1 Output Typically 1kΩ to GND 1 1 0 Output Typically 100kΩ to GND 1 1 1 Output High Impedance TABLE I. DAC8534 Power-Down Modes. SYNC INTERRUPT LD 1 (DB20) and LD 0 (DB21) control the updating of each analog output with the specified 16-bit data value or powerdown command. Bit DB19 is a “Don’t Care” bit which does not affect the operation of the DAC8534 and can be 1 or 0. The DAC Channel Select Bits (DB17, DB18) control the destination of the data (or power-down command) from DAC A through DAC D. The final control bit, PD0 (DB16), selects the powerdown mode of the DAC8534 channels. In a normal write sequence, the SYNC line is kept LOW for at least 24 falling edges of SCLK and the addressed DAC register is updated on the 24th falling edge. However, if SYNC is brought HIGH before the 24th falling edge, it acts as an interrupt to the write sequence; the shift register is reset and the write sequence is discarded. Neither an update of the data buffer contents, DAC register contents, nor a change in the operating mode occurs (see Figure 4). The DAC8534 also supports a number of different load commands. The load commands include broadcast commands to address all the DAC8534s on an SPI bus. The load commands can be summarized as follows: POWER-ON RESET DB21 = 0 and DB20 = 0: Single-channel store. The temporary register (data buffer) corresponding to a DAC selected by DB18 and DB17 is updated with the contents of SR data (or power-down). DB21 = 0 and DB20 = 1: Single-channel update. The temporary register and DAC register corresponding to a DAC selected by DB18 and DB17 are updated with the contents of SR data (or power-down). DB21 = 1 and DB20 = 0: Simultaneous update. A channel selected by DB18 and DB17 gets updated with the SR data, and simultaneously, all the other channels get updated with previous stored data (or power-down). DB21 = 1 and DB20 = 1: Broadcast update. All the DAC8534s on the SPI bus respond, regardless of address matching. If DB18 = 0, then SR data gets ignored, all channels from all The DAC8534 contains a power-on reset circuit that controls the output voltage during power-up. On power-up, the DAC registers are filled with zeros and the output voltages are set to zero-scale; they remain there until a valid write sequence and load command is made to the respective DAC channel. This is useful in applications where it is important to know the state of the output of each DAC output while the device is in the process of powering up. No device pin should be brought high before power is applied to the device. POWER-DOWN MODES The DAC8534 utilizes four modes of operation. These modes are accessed by setting three bits (PD2, PD1, and PD0) in the shift register and performing a “Load” action to the DACs. The DAC8534 offers a very flexible power-down interface based on channel register operation. A channel consists of a DB23 A1 DB12 A0 LD1 LD0 X D10 D9 D8 D7 DAC Select 1 DAC Select 0 PD0 D15 D14 D13 D12 D4 D3 D2 D1 D0 DB11 D11 DB0 D6 D5 FIGURE 3. DAC8534 Data Input Register Format. DAC8534 12 www.ti.com SBAS254D D23 D22 D21 D20 A1 A0 Load 1 Load 0 D19 D18 D17 Don’t Care DAC Sel 1 DAC Sel 0 D16 D15 D14 D13-D0 PD0 MSB MSB-1 MSB-2...LSB DESCRIPTION (Address Select) 0/1 (A0 and A1 should correspond to the package address set via pins 13 and 14.) This address selects 1 of 4 possible devices on a single SPI data bus based on each device’s address pin(s) state. See Below 0/1 0 0 X 0 0 0 Data Write To Buffer A w/Data 0 0 X 0 1 0 Data Write To Buffer B w/Data 0 0 X 1 0 0 Data Write To Buffer C w/Data 0 0 X 1 1 0 Data 0 0 X (00, 01, 10, or 11) 1 0 1 X (00, 01, 10, or 11) 0 0 1 X (00, 01, 10, or 11) 1 1 0 X (00, 01, 10, or 11) 0 1 0 X (00, 01, 10, or 11) 1 Write To Buffer D w/Data 0 (see Table I) Write To Buffer (selected by DB17 and DB18) w/Power-Down Command Write To Buffer w/Data and Load DAC (selected by DB17 and DB18) Data (see Table I) 0 Write To Buffer w/Power-Down Command and Load DAC (selected by DB17 and DB18) Write To Buffer w/Data (selected by DB17 and DB18) and Load All DACs Data 0 (see Table I) Write To Buffer w/Power-Down Command (selected by DB17 and DB18) and Load All DACs Broadcast Modes X X 1 1 X 0 X X X X X 1 1 X 1 X 0 Data X X 1 1 X 1 X 1 Load All DACs, All Device, and All Buffers with Stored Data Write To All Devices and Load All Dacs, with SR Data (see Table I) 0 Write To All Devices w/Power-Down Command in SR TABLE II. Control Matrix. 24th Falling Edge SCLK 1 2 1 24th Falling Edge 2 SYNC Invalid Write-Sync Interrupt: SYNC HIGH Before 24th Falling Edge DIN DB23 DB22 Valid Write-Buffer/DAC Update: SYNC HIGH After 24th Falling Edge DB0 DB23 DB22 DB1 DB0 FIGURE 4. Interrupt and Valid SYNC Timing. single 16-bit DAC with power-down circuitry, a temporary storage register (TR), and a DAC register (DR). TR and DR are both 18-bit wide. Two MSBs represent power-down condition and 16LSBs represent data for TR and DR. By adding bits 17 and 18 to TR and DR, a power-down condition can be temporarily stored and used just like data. Internal circuits ensure that DB15 and DB14 get transfered to TR17 and TR16 (DR17 and DR16), when DB16 = 1. The DAC8534 treats the power-down condition like data and all the operational modes are still valid for power-down. It is possible to broadcast a power-down condition to all the DAC8534s in a system, or it is possible to simultaneously power-down a channel while updating data on other channels. DB16, DB15, and DB14 = 100 represent a power-down condition with Hi-Z output impedance for a selected channel. Same is true for 111. 101 represents a power-down condition with 1k output impedance and 110 represents a power-down condition with 100k output impedance. When both bits are set to 0 or 1, the device enters a highimpedance state with a typical power consumption of 3pA at 5V. For the two low impedance output modes, however, the supply current falls to 100nA at 5V (50nA at 3V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the device is known while it is in power-down mode. There are three different options for power-down: the output is connected internally to GND through a 1kΩ resistor, a 100kΩ resistor, or it is left open-circuited (High-Impedance). The output stage is illustrated in Figure 5. All analog circuitry is shut down when the power-down mode is activated. Each DAC will exit power-down when PD0 is set to 0, new data is written to the Data Buffer, and the DAC channel receives a “Load” command. The time to exit powerdown is typically 2.5µs for AVDD = 5V and 5µs for AVDD = 3V (see the Typical Characteristics). DAC8534 SBAS254D 13 www.ti.com Resistor String DAC Amplifier VOUTX Power-down Circuitry Resistor Network FIGURE 5. Output Stage During Power-Down (High-Impedance). OPERATION EXAMPLES Example 1: Write to Data Buffer A; Through Buffer D; Load DAC A Through DAC D Simultaneously • 1st—Write to Data Buffer A: A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 ...... DB1 DB0 0 0 0 0 X 0 0 0 D15 ..... D1 D0 • 2nd—Write to Data Buffer B: A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 ...... DB1 DB0 0 0 0 0 X 0 1 0 D15 ..... D1 D0 • 3rd—Write to Data Buffer C: A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 ...... DB1 DB0 0 0 0 0 X 1 0 0 D15 ..... D1 D0 • 4th—Write to Data Buffer D and simultaneously update all DACs: A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 ...... DB1 DB0 0 0 1 0 X 1 1 0 D15 ..... D1 D0 The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously settle to the specified values upon completion of the 4th write sequence. (The “Load” command moves the digital data from the data buffer to the DAC register at which time the conversion takes place and the analog output is updated. “Completion” occurs on the 24th falling SCLK edge after SYNC LOW.) Example 2: Load New Data to DAC A Through DAC D Sequentially • 1st—Write to Data Buffer A and Load DAC A: DAC A output settles to specified value upon completion: A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 ...... DB1 DB0 0 0 0 1 X 0 0 0 D15 ..... D1 D0 • 2nd—Write to Data Buffer B and Load DAC B: DAC B output settles to specified value upon completion: A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 ...... DB1 DB0 0 0 0 1 X 0 1 0 D15 ..... D1 D0 • 3rd—Write to Data Buffer C and Load DAC C: DAC C output settles to specified value upon completion: A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 ...... DB1 DB0 0 0 0 1 X 1 0 0 D15 ..... D1 D0 • 4th—Write to Data Buffer D and Load DAC D: DAC D output settles to specified value upon completion: A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 ...... DB1 DB0 0 0 0 1 X 1 1 0 D15 ..... D1 D0 After completion of each write cycle, DAC analog output settles to the voltage specified. Example 3: Power-Down DAC A and DAC B to 1kΩ and Power-Down DAC C and DAC D to 100kΩ Simultaneously • Write power-down command to Data Buffer A: DAC A to 1kΩ. A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 DB14 DB13 ........ 0 0 0 0 X 0 0 1 0 1 X ........ DAC8534 14 www.ti.com SBAS254D • Write power-down command to Data Buffer B: DAC B to 1kΩ. A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 DB14 DB13 ........ 0 0 0 0 X 0 1 1 0 1 X ........ • Write power-down command to Data Buffer C: DAC C to 100kΩ. A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 DB14 DB13 ........ 0 0 0 0 X 1 0 1 1 0 X ........ • Write power-down command to Data Buffer D: DAC D to 100kΩ and Simultaneously Update all DACs. A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 DB14 DB13 ........ 0 0 1 0 X 1 1 1 1 0 X ........ The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously power-down to each respective specified mode upon completion of the 4th write sequence. Example 4: Power-Down DAC A Through DAC D to High-Impedance Sequentially: • Write power-down command to Data Buffer A and Load DAC A: DAC A output = High-Z: A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 DB14 DB13 ........ 0 0 0 1 X 0 0 1 1 1 X ........ • Write power-down command to Data Buffer B and Load DAC B: DAC B output = High-Z: A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 DB14 DB13 ........ 0 0 0 1 X 0 1 1 1 1 X ........ • Write power-down command to Data Buffer C and Load DAC C: DAC C output = High-Z: A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 DB14 DB13 ........ 0 0 0 1 X 1 0 1 1 1 X ........ • Write power-down command to Data Buffer D and Load DAC D: DAC D output = High-Z: A1 A0 LD1 LD0 DC DAC Sel 1 DAC Sel 0 PD0 DB15 DB14 DB13 ........ 0 0 0 1 X 1 1 1 1 1 X ........ The DAC A, DAC B, DAC C, and DAC D analog outputs sequentially power-down to high-impedance upon completion of the 1st, 2nd, 3rd, and 4th write sequences, respectively. LDAC FUNCTIONALITY The DAC8534 offers both a software and hardware simultaneous update function. The DAC8534 double-buffered architecture has been designed so that new data can be entered for each DAC without disturbing the analog outputs. The software simultaneous update capability is controlled by the Load 1 (LD1) and Load 0 (LD0) control bits. By setting Load 1 equal to “1” all of the DAC registers will be updated on the falling edge of the 24th clock signal. When the new data has been entered into the device, all of the DAC outputs can be updated simultaneously and synchronously with the clock. The internal DAC register is edge triggered and not level triggered, therefore, when the LDAC pin signal is transitioned from LOW to HIGH, the digital word currently in the DAC input register is latched. Additionally, it allows the DAC input registers to be written to at any point; then, the DAC output voltages can be asynchronously changed via the LDAC pin. The LDAC trigger should only be used after the buffers are properly updated through software. If DAC outputs are desired to be updated through software only, the LDAC pin must be tied low permanently. MICROPROCESSOR INTERFACING DAC8534 to 8051 INTERFACE See Figure 6 for a serial interface between the DAC8534 and a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the 8051 drives SCLK of the DAC8534, while RXD drives the serial data line of the device. The SYNC signal is derived from a bit-programmable pin on the port of the 8051. In this case, port line P3.3 is used. When data is to be transmitted to the DAC8534, P3.3 is taken LOW. The 8051 transmits data in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left LOW after the first eight bits are transmitted, then a second and third write cycle is initiated to transmit the remaining data. P3.3 is taken HIGH following the completion of the third write cycle. The 8051 outputs the serial data in a format which presents the LSB first, while the DAC8534 requires its data with the MSB as the first bit received. The 8051 transmit routine must therefore take this into account, and “mirror” the data as needed. DAC8534 SBAS254D 15 www.ti.com DAC8534 to TMS320 DSP INTERFACE 80C51/80L51(1) DAC8534(1) P3.3 SYNC TXD SCLK RXD DIN Figure 9 shows the connections between the DAC8534 and a TMS320 Digital Signal Processor (DSP). A Single DSP can control up to four DAC8534s without any interface logic. DAC8534 NOTE: (1) Additional pins omitted for clarity. Positive Supply AVDD FIGURE 6. DAC8534 to 80C51/80L51 Interface. 0.1µF 10µF TMS320 DSP DAC8534 to Microwire INTERFACE FSX Figure 7 shows an interface between the DAC8534 and any Microwire compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the DAC8534 on the rising edge of the CK signal. DX CLKX SYNC DIN SCLK VOUTA Output A VOUTD Output D Reference Input VREFH VREFL 0.1µF 1µF to 10µF GND MicrowireTM DAC8534(1) CS SYNC SK SCLK SO DIN FIGURE 9. DAC8534 to TMS320 DSP. APPLICATIONS CURRENT CONSUMPTION NOTE: (1) Additional pins omitted for clarity. Microwire is a registered trademark of National Semiconductor. FIGURE 7. DAC8534 to Microwire Interface. DAC8534 to 68HC11 INTERFACE Figure 8 shows a serial interface between the DAC8534 and the 68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC8534, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7), similar to the 8051 diagram. 68HC11(1) DAC8534(1) PC7 SYNC SCK SCLK MOSI DIN NOTE: (1) Additional pins omitted for clarity. FIGURE 8. DAC8534 to 68HC11 Interface. The 68HC11 should be configured so that its CPOL bit is 0 and its CPHA bit is 1. This configuration causes data appearing on the MOSI output to be valid on the falling edge of SCLK. When data is being transmitted to the DAC, the SYNC line is held LOW (PC7). Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. (Data is transmitted MSB first.) In order to load data to the DAC8534, PC7 is left LOW after the first eight bits are transferred, then a second and third serial write operation is performed to the DAC. PC7 is taken HIGH at the end of this procedure. The DAC8534 typically consumes 250µA at AVDD = 5V and 225µA at AVDD = 3V for each active channel, including reference current consumption. Additional current consumption can occur at the digital inputs if VIH << IOVDD. For most efficient power operation, CMOS logic levels are recommended at the digital inputs to the DAC. In power-down mode, typical current consumption is 200nA per channel. A delay time of 10ms to 20ms after a powerdown command is issued to the DAC is typically sufficient for the power-down current to drop below 10µA. DRIVING RESISTIVE AND CAPACITIVE LOADS The DAC8534 output stage is capable of driving loads of up to 1000pF while remaining stable. Within the offset and gain error margins, the DAC8534 can operate rail-to-rail when driving a capacitive load. Resistive loads of 2kΩ can be driven by the DAC8534 while achieving a typical load regulation of 1%. As the load resistance drops below 2kΩ, the load regulation error increases. When the outputs of the DAC are driven to the positive rail under resistive loading, the PMOS transistor of each Class-AB output stage can enter into the linear region. When this occurs, the added IR voltage drop deteriorates the linearity performance of the DAC. This only occurs within approximately the top 20mV of the DAC’s output voltage characteristic. The reference voltage applied to the DAC8534 may be reduced below the supply voltage applied to AVDD in order to eliminate this condition if good linearity is a requirement at full-scale (under resistive loading conditions). CROSSTALK AND AC PERFORMANCE The DAC8534 architecture uses separate resistor strings for each DAC channel in order to achieve ultra-low crosstalk performance. DC crosstalk seen at one channel during a full- DAC8534 16 www.ti.com SBAS254D scale change on the neighboring channel is typically less than 0.5LSBs. The AC crosstalk measured (for a full-scale, 1kHz sine wave output generated at one channel, and measured at the remaining output channel) is typically under –100dB. In addition, the DAC8534 can achieve typical AC performance of 96dB SNR (Signal-to-Noise Ratio) and 65dB THD (Total Harmonic Distortion), making the DAC8534 a solid choice for applications requiring high SNR at output frequencies at or below 4kHz. OUTPUT VOLTAGE STABILITY The DAC8534 exhibits excellent temperature stability of 5ppm/°C typical output voltage drift over the specified temperature range of the device. This enables the output voltage of each channel to stay within a ±25µV window for a ±1°C ambient temperature change. Good Power-Supply Rejection Ratio (PSRR) performance reduces supply noise present on AVDD from appearing at the outputs to well below 10µV-s. Combined with good DC noise performance and true 16-bit differential linearity, the DAC8534 becomes a perfect choice for closed-loop control applications. USING THE REF02 AS A POWER SUPPLY FOR THE DAC8534 Due to the extremely low supply current required by the DAC8534, a possible configuration is to use a REF02 +5V precision voltage reference to supply the required voltage to the DAC8534's supply input as well as the reference input, as shown in Figure 10. This is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5V. The REF02 will output a steady supply voltage for the DAC8534. If the REF02 is used, the current it needs to supply to the DAC8534 is 1.085mA typical and 1.78mA max for AVDD = 5V. When a DAC output is loaded, the REF02 also needs to supply the current to the load. The total typical current required (with a 5kΩ load on a given DAC output) is: 1.085mA + (5V/ 5kΩ) = 2.085mA +15 +5V REF02 SETTLING TIME AND OUTPUT GLITCH PERFORMANCE Settling time to within the 16-bit accurate range of the DAC8534 is achievable within 10µs for a full-scale code change at the input. Worst-case settling times between consecutive code changes is typically less than 2µs, enabling update rates up to 500ksps for digital input signals changing code-to-code. The high-speed serial interface of the DAC8534 is designed in order to support these high update rates. For full-scale output swings, the output stage of each DAC8534 channel typically exhibits less than 100mV of overshoot and undershoot when driving a 200pF capacitive load. Code-to-code change glitches are extremely low given that the code-to-code transition does not cross an Nx4096 code boundary. Due to internal segmentation of the DAC8534, code-to-code glitches occur at each crossing of an Nx4096 code boundary. These glitches can approach 100nVs for N = 15, but settle out within ~2µs. AIDD + IREF 3-Wire Serial Interface SYNC AVDD, VREF SCLK DAC8534 VOUT = 0V to 5V DIN FIGURE 10. REF02 as a Power Supply to the DAC8534. BIPOLAR OPERATION USING THE DAC8534 The DAC8534 has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 11. The circuit shown will give an output voltage range of ±VREF. Rail-to-rail operation at the amplifier output is achievable using an amplifier such as the OPA703, as shown in Figure 11. R2 10kΩ +5V +5V R1 10kΩ OPA703 DAC8534 VOUTX ±5V AVDD, VREF 10µF 0.1µF -5V (Other pins omitted for clarity.) FIGURE 11. Bipolar Operation with the DAC8534. DAC8534 SBAS254D 17 www.ti.com The output voltage for any input code can be calculated as follows: D R1 + R 2 VOUT X = VREF • – VREF • 65536 R1 R • 2 R1 where D represents the input code in decimal (0–65535). With VREF = 5V, R1 = R2 = 10kΩ: 10 • D VOUT X = – 5V 65536 This is an output voltage range of ±5V with 0000H corresponding to a –5V output and FFFFH corresponding to a +5V output. Similarly, using VREF = 2.5V, a ±2.5V output voltage range can be achieved. LAYOUT A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The DAC8534 offers single-supply operation, and it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it will be to keep digital noise from appearing at the output. Due to the single ground pin of the DAC8534, all return currents, including digital and analog return currents for the DAC, must flow through a single point. Ideally, GND would be connected directly to an analog ground plane. This plane would be separate from the ground connection for the digital components until they were connected at the power-entry point of the system. The power applied to AVDD should be well regulated and low noise. Switching power supplies and DC/DC converters will often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. As with the GND connection, AVDD should be connected to a positive power-supply plane or trace that is separate from the connection for digital logic until they are connected at the power-entry point. In addition, a 1µF to 10µF capacitor in parallel with a 0.1µF bypass capacitor is strongly recommended. In some situations, additional bypassing may be required, such as a 100µF electrolytic capacitor or even a “Pi” filter made up of inductors and capacitors—all designed to essentially low-pass filter the supply, removing the highfrequency noise. Up to four DAC8534 devices can be used on a single SPI bus without any glue logic to create a high channel count solution. Special attention is required to avoid digital signal integrity problems when using multiple DAC8534s on the same SPI bus. Signal integrity of SYNC, SCLK, and DIN lines will not be an issue as long as the rise times of these digital signals are longer than six times the propagation delay between any two DAC8534 devices. Propagation speed is approximately six inches/ns on standard PCBs. Therefore, if the digital signal risetime is 1ns, the distance between any two DAC8534 devices is recommended not to exceed 1 inch. If the DAC8534s have to be further apart on the PCB, the signal rise times should be reduced by placing series resistors at the drivers for SYNC, SCLK, and DIN lines. If the largest distance between any two DAC8534s has to be six inches, the risetime should be reduced to 6ns with an RC network formed by the series resistor at the digital driver and the total trace and input capacitance on the PCB. DAC8534 18 www.ti.com SBAS254D MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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