TOREX XC6118N08CGR-G

XC6118 Series
ETR0213-003
Voltage Detector with Separated Sense Pin & Delay Capacitor Pin
■GENERAL DESCRIPTION
The XC6118 series is a low power consumption voltage detector with high accuracy detection, manufactured using CMOS
process and laser trimming technologies.
Since the sense pin is separated from the power supply pin, it allows the IC to monitor the other power supply.
The XC6118 can maintain the state of detection even when voltage of the monitored power supply drops to 0V.
Moreover, a release delay time can be adjusted by the external capacitor connected to the Cd pin.
The VOUT pin is available in both CMOS and N-channel open drain output configurations.
■APPLICATIONS
■FEATURES
●Microprocessor reset circuitry
High Accuracy
●Charge voltage monitors
●Memory battery back-up switch circuits
●Power failure detection circuits
■TYPICAL APPLICATION CIRCUIT
:±2％(Detect Voltage≧1.5V)
:±30mV(Detect Voltage＜1.5V)
Low Power Consumption
: 0.4μA(Detect, VIN=1.0V) (TYP.)
: 0.8μA(Release, VIN=1.0V)(TYP.)
Detect Voltage Range
: 0.8V～5.0V (0.1V increments)
Operating Voltage Range
: 1.0V～6.0V
Temperature Characteristics : ±100ppm/℃(TYP.)
Output Configuration
: CMOS, N-channel open drain
Operating Temperature Range : -40℃～+85℃
Separated Sense Pin
: Power supply separation
Built-in delay time
: Release delay time adjustable
Packages
: USP-4, SOT-25
■TYPICAL PERFORMANCE
CHARACTERISTICS
●Output Voltage vs. Sense Voltage
XC6118C25AGR
(No Pull-Up resistor needed for
CMOS output product)
Output Voltage: VOUT (V)
Ta=25℃
Monitering
Power
別電源
supply
7.0
6.0
VIN=6.0V
5.0
4.0
4.0V
3.0
2.0
1.0
1.0V
0.0
-1.0
0
1
2
3
4
5
6
Sense Voltage: VSEN (V)
1/20
XC6118 Series
■PIN CONFIGURATION
Cd/NC
2
VOUT 1
3 VSEN
5
VSS
4
VIN
USP-4
（BOTTOM VIEW）
SOT-25
（TOP VIEW）
* In the XC6118xxxA/B series, the dissipation pad
should not be short-circuited with other pins.
* In the XC6118xxxC/D series, when the dissipation
pad is short-circuited with other pins, connect it to
the NC pin (No.2) pin before use.
■PIN ASSIGNMENT
PIN NUMBER
USP-4
SOT-25
1
2
2
3
4
5
1
5
4
3
2
PIN NAME
FUNCTION
VOUT
Cd
NC
VSEN
VIN
VSS
Output (Detect ”L”)
Delay Capacitance (*1)
No Connection
Sense
Input
Ground (*2)
NOTE:
*1: With the VSS pin of the USP-4 package, a tab on the backside is used as the pin No.5.
*2: In the case of selecting no built-in delay capacitance pin type, the delay capacitance (Cd) pin will
be used as the NC.
■PRODUCT CLASSIFICATION
●Ordering Information
XC6118①②③④⑤⑥-⑦(*1)
DESIGNATOR
DESCRIPTION
①
Output Configuration
②③
Detect Voltage
④
Options
SYMBOL
C
CMOS output
N
N-ch open drain output
08~50
Packages
Taping Type (*2)
e.g. 18 → 1.8V
A
Built-in delay capacitance pin, hysteresis 5% (TYP.)(Standard*)
B
Built-in delay capacitance pin, hysteresis less than 1%(Standard*)
C
D
⑤⑥-⑦
DESCRIPTION
No built-in delay capacitance pin, hysteresis 5% (TYP.)
(Semi-custom)
No built-in delay capacitance pin, hysteresis less than 1%
(Semi-custom)
GR-G
USP-4 (Halogen & Antimony free)
MR-G
SOT-25 (Halogen & Antimony free)
*When delay function isn’t used, open the delay capacitance pin before use.
(*1)
(*2)
2/20
The ”-G” suffix indicates that the products are Halogen and Antimony free as well as being fully RoHS compliant.
The device orientation is fixed in its embossed tape pocket.
For reverse orientation, please contact your local Torex sales office or representative.
(Standard orientation: ⑤R-⑦, Reverse orientation: ⑤L-⑦)
XC6118
Series
■BLOCK DIAGRAMS
(1) XC6118CxxA
*The delay capacitance pin (Cd) is not
connected to the circuit in the block diagram of
XC6118CxxC (semi-custom).
(2) XC6118CxxB
*The delay capacitance pin (Cd) is not
connected to the circuit in the block diagram of
XC6118CxxD (semi-custom).
(3) XC6118NxxA
*The delay capacitance pin (Cd) is not
connected to the circuit in the block diagram of
XC6118NxxC (semi-custom).
(4) XC6118NxxB
*The delay capacitance pin (Cd) is not
connected to the circuit in the block diagram of
XC6118NxxD (semi-custom).
3/20
XC6118 Series
■ABSOLUTE MAXIMUM RATINGS
●XC6118xxxA/B
PARAMETER
Input Voltage
Output Current
XC6118C (*1)
Output Voltage
XC6118N (*2)
Sense Pin Voltage
Delay Capacitance Pin Voltage
Delay Capacitance Pin Current
USP-4
Power Dissipation
SOT-25
Operating Temperature Range
Storage Temperature Range
Ta=25℃
SYMBOL
RATINGS
UNITS
VIN
IOUT
VSS-0.3～7.0
10
VSS-0.3～VIN+0.3
VSS-0.3～7.0
VSS-0.3～7.0
VSS-0.3～VIN+0.3
5.0
120
250
-40～+85
-55～+125
V
mA
VOUT
VSEN
VCD
ICD
Pd
Ta
Tstg
●XC6118xxxC/D
PARAMETER
Input Voltage
Output Current
XC6118C (*1)
Output Voltage
(*2)
XC6118N
Sense Pin Voltage
USP-4
Power Dissipation
SOT-25
Operating Temperature Range
Storage Temperature Range
NOTE:
*1: CMOS output
*2: N-ch open drain output
4/20
V
V
V
mA
mW
o
o
C
C
Ta=25℃
SYMBOL
RATINGS
UNITS
VIN
IOUT
VSS-0.3～7.0
10
VSS-0.3～VIN+0.3
VSS-0.3～7.0
VSS-0.3～7.0
120
250
-40～+85
-55～+125
V
mA
VOUT
VSEN
Pd
Ta
Tstg
V
V
mW
o
o
C
C
XC6118
Series
■ELECTRICAL CHARACTERISTICS
●XC6118xxxA
Ta=25℃
PARAMETER
SYMBOL
CONDITIONS
Operating Voltage
VIN
VDF(T)=0.8～5.0V
Detect Voltage
MIN.
(*1)
TYP.
1.0
MAX.
UNITS
CIRCUITS
6.0
V
-
VDF
VIN=1.0～6.0V
E-1
V
①
Hysteresis Width
VHYS
VIN=1.0～6.0V
E-2
V
①
Detect Voltage
ΔVDF/
Line Regulation
(ΔVIN・VDF)
VIN=1.0～6.0V
±0.1
%/V
①
μA
②
μA
②
mA
③
mA
④
μA
③
VSEN=VDF×0.9
Supply Current 1
(*2)
ISS1
VIN=1.0V
0.4
1.0
VIN=6.0V
0.4
1.0
VIN=1.0V
0.8
1.6
VIN=6.0V
0.9
1.8
VSEN=VDF×1.1
Supply Current 2
(*2)
ISS2
VSEN=0V, VDS=0.5V(Nch)
IOUT1
Output Current
(*3)
VIN=1.0V
0.1
0.7
VIN=2.0V
0.8
1.6
VIN=3.0V
1.2
2.0
VIN=4.0V
1.6
2.3
VIN=5.0V
1.8
2.4
VIN=6.0V
1.9
2.5
VSEN=6.0V,
IOUT2
VDS=0.5V(Pch)
VIN=1.0V
VIN=6.0V
Leakage
Current
CMOS Output
ILEAK
N-ch Open Drain
Sense Resistance
(*4)
Delay Resistance
(*5)
Delay capacitance pin
Sink Current
Delay Capacitance Pin Threshold
Voltage
Undefined Operation
Detect Delay Time
(*6)
(*7)
Release Delay Time
(*8)
-0.08
-1.00
-0.70
0.20
VIN=6.0V, VSEN=6.0V,
VOUT=6.0V, Cd: Open
0.20
Output
Temperature Characteristics
-0.30
ΔVDF/
(ΔTopr・VDF)
RSEN
RDELAY
ICD
VTCD
VUNS
tDF0
tDR0
o
o
0.40
-40 C≦Ta≦85 C
±100
ppm/ C
o
①
VSEN=5.0V VIN=0V
E-4
MΩ
⑤
MΩ
⑥
μA
⑥
V
⑦
VSEN=6.0V VIN=5.0V
Cd=0V
1.6
Cd=0.5V, VIN=1.0V
2.0
2.4
200
VSEN=6.0V VIN=1.0V
0.4
0.5
0.6
VSEN=6.0V VIN=6.0V
2.9
3.0
3.1
0.3
0.4
V
⑧
30
230
μs
⑨
30
200
μs
⑨
VIN=VSEN=0～1.0V
VIN=6.0V, VSEN=6.0→0V
Cd: Open
VIN=6.0V, VSEN=0→6.0V
Cd: Open
NOTE:
*1: VDF (T): Nominal detect voltage
*2: Current to the sense resistor is not included.
*3: IOUT2 is applied only to the XC6118C series (CMOS output).
*4: It is calculated from the voltage value and the current value of the VSEN.
*5: It is calculated from the voltage value of the VIN and the current value of the Cd.
*6: Maximum VOUT voltage when VIN is changed from 0V to 1.0V under connecting the VIN pin to the VSEN pin.
This value is effective only to the XC6118C series (CMOS output).
*7: Delay time from the time of VSEN=VDF to the time of VOUT= 0.6V when the VSEN falls.
*8: Delay time from the time of VIN= VDF +VHYS to the time of VOUT = 5.4V when the VSEN rises.
5/20
XC6118 Series
■ELECTRICAL CHARACTERISTICS (Continued)
●XC6118xxxB
Ta=25℃
PARAMETER
SYMBOL
CONDITIONS
Operating Voltage
VIN
VDF(T)=0.8～5.0V
Detect Voltage
MIN.
(*1)
TYP.
1.0
MAX.
UNITS
CIRCUITS
6.0
V
-
VDF
VIN=1.0～6.0V
E-1
V
①
Hysteresis Width
VHYS
VIN=1.0～6.0V
E-3
V
①
Detect Voltage
ΔVDF/
Line Regulation
(ΔVIN・VDF)
VIN=1.0～6.0V
±0.1
%/V
①
μA
②
μA
②
mA
③
mA
④
μA
③
ppm/ C
o
①
VSEN=VDF×0.9
Supply Current 1
(*2)
ISS1
VIN=1.0V
0.4
1.0
VIN=6.0V
0.4
1.0
VIN=1.0V
0.8
1.6
VIN=6.0V
0.9
1.8
VSEN=VDF×1.1
Supply Current 2
(*2)
ISS2
VSEN=0V VDS=0.5V(Nch)
IOUT1
Output Current
(*3)
VIN=1.0V
0.1
0.7
VIN=2.0V
0.8
1.6
VIN=3.0V
1.2
2.0
VIN=4.0V
1.6
2.3
VIN=5.0V
1.8
2.4
VIN=6.0V
1.9
2.5
VSEN=6.0V VDS=0.5V(Pch)
IOUT2
VIN=1.0V
-0.30
-0.08
VIN=6.0V
-1.00
-0.70
CMOS
Leakage
Output
Current
N-ch Open
ILEAK
0.20
VIN=6.0V, VSEN=6.0V,
VOUT=6.0V, Cd: Open
0.20
Drain Output
Temperature Characteristics
Sense Resistance
(*4)
Delay Resistance
(*5)
Delay capacitance pin
Sink Current
Delay Capacitance Pin
Threshold Voltage
Undefined Operation
Detect Delay Time
(*6)
(*7)
Release Delay Time
(*8)
ΔVDF/
(ΔTopr・VDF)
o
o
-40 C≦Ta≦85 C
RSEN
VSEN=5.0V VIN=0V
RDELAY
VSEN=6.0V VIN=5.0V Cd=0V
ICD
Cd=0.5V, VIN=1.0V
VTCD
VUNS
tDF0
tDR0
0.40
±100
E-4
1.6
2.0
2.4
200
MΩ
⑤
MΩ
⑥
μA
⑥
V
⑦
VSEN=6.0V VIN=1.0V
0.4
0.5
0.6
VSEN=6.0V VIN=6.0V
2.9
3.0
3.1
0.3
0.4
V
⑧
30
230
μs
⑨
30
200
μs
⑨
VIN=VSEN=0～1.0V
VIN=6.0V, VSEN=6.0→0V
Cd: Open
VIN=6.0V, VSEN=0→6.0V
Cd: Open
NOTE:
*1: VDF (T): Nominal detect voltage
*2: Current to the sense resistor is not included.
*3: IOUT2 is applied only to the XC6118C series (CMOS output).
*4: It is calculated from the voltage value and the current value of the VSEN.
*5: It is calculated from the voltage value of the VIN and the current value of the Cd.
*6: Maximum VOUT voltage when VIN is changed from 0V to 1.0V under connecting the VIN pin to the VSEN pin.
This value is effective only to the XC6118C series (CMOS output).
*7: Delay time from the time of VSEN=VDF to the time of VOUT= 0.6V when the VSEN falls.
*8: Delay time from the time of VIN= VDF +VHYS to the time of VOUT= 5.4V when the VSEN rises.
6/20
XC6118
Series
■ELECTRICAL CHARACTERISTICS (Continued)
●XC6118xxxC
Ta=25℃
PARAMETER
SYMBOL
Operating Voltage
VIN
CONDITIONS
MIN.
(*1)
VDF(T)=0.8～5.0V
TYP.
1.0
MAX.
UNITS
CIRCUITS
6.0
V
-
Detect Voltage
VDF
VIN=1.0～6.0V
E-1
V
①
Hysteresis Width
VHYS
VIN=1.0～6.0V
E-2
V
①
VIN=1.0～6.0V
±0.1
%/V
①
μA
②
μA
②
mA
③
mA
④
μA
③
ppm/ C
o
①
MΩ
⑤
Detect Voltage
ΔVDF/
Line Regulation
(ΔVIN・VDF)
VSEN=VDF×0.9
Supply Current 1
(*2)
ISS1
VIN=1.0V
0.4
1.0
VIN=6.0V
0.4
1.0
VIN=1.0V
0.8
1.6
VIN=6.0V
0.9
1.8
VSEN=VDF×1.1
Supply Current 2
(*2)
ISS2
VSEN=0V VDS=0.5V(Nch)
IOUT1
Output Current
(*3)
VIN=1.0V
0.1
0.7
VIN=2.0V
0.8
1.6
VIN=3.0V
1.2
2.0
VIN=4.0V
1.6
2.3
VIN=5.0V
1.8
2.4
VIN=6.0V
1.9
2.5
VSEN=6.0V VDS=0.5V(Pch)
IOUT2
VIN=1.0V
-0.30
-0.08
VIN=6.0V
-1.00
-0.70
CMOS
Leakage
Output
Current
Nch Open Drain
ILEAK
VIN=6.0V, VSEN=6.0V,
VOUT=6.0V, Cd: Open
Output
Temperature Characteristics
Sense Resistance
(*4)
Undefined Operation
Detect Delay Time
(*5)
(*6)
Release Delay Time
(*7)
ΔVDF/
o
o
0.20
0.20
0.40
-40 C≦Ta≦85 C
±100
RSEN
VSEN=5.0V VIN=0V
E-4
VUNS
VIN=VSEN=0～1.0V
0.3
0.4
V
⑦
tDF0
VIN=6.0V, VSEN=6.0→0V
30
230
μs
⑨
tDR0
VIN=6.0V, VSEN=0→6.0V
30
200
μs
⑨
(ΔTopr・VDF)
NOTE:
*1: VDF (T): Nominal detect voltage
*2: Current to the sense resistor is not included.
*3: IOUT2 is applied only to the XC6118C series (CMOS output).
*4: It is calculated from the voltage value and the current value of the VSEN.
*5: Maximum VOUT voltage when VIN is changed from 0V to 1.0V under connecting the VIN pin to the VSEN pin.
This value is effective only to the XC6118C series (CMOS output).
*6: Delay time from the time of VSEN=VDF to the time of VOUT= 0.6V when the VSEN falls.
*7: Delay time from the time of VIN= VDF +VHYS to the time of VOUT= 5.4V when the VSEN rises.
7/20
XC6118 Series
■ELECTRICAL CHARACTERISTICS (Continued)
Ta=25℃
●XC6118xxxD
PARAMETER
SYMBOL
Operating Voltage
VIN
CONDITIONS
MIN.
(*1)
VDF(T)=0.8～5.0V
TYP.
1.0
MAX.
UNITS
CIRCUITS
6.0
V
-
Detect Voltage
VDF
VIN=1.0～6.0V
E-1
V
①
Hysteresis Width
VHYS
VIN=1.0～6.0V
E-3
V
①
VIN=1.0～6.0V
±0.1
%/V
①
μA
②
μA
②
mA
③
mA
④
μA
③
o
①
Detect Voltage
ΔVDF/
Line Regulation
(ΔVIN・VDF)
VSEN=VDF×0.9
Supply Current 1
(*2)
ISS1
VIN=1.0V
0.4
1.0
VIN=6.0V
0.4
1.0
VIN=1.0V
0.8
1.6
VIN=6.0V
0.9
1.8
VSEN=VDF×1.1
Supply Current 2
(*2)
ISS2
VSEN=0V VDS=0.5V(Nch)
IOUT1
Output Current
(*3)
VIN=1.0V
0.1
0.7
VIN=2.0V
0.8
1.6
VIN=3.0V
1.2
2.0
VIN=4.0V
1.6
2.3
VIN=5.0V
1.8
2.4
VIN=6.0V
1.9
2.5
VSEN=6.0V VDS=0.5V(Pch)
IOUT2
VIN=1.0V
-0.30
-0.08
VIN=6.0V
-1.00
-0.70
CMOS
Leakage
Output
Current
Nch Open
ILEAK
VIN=6.0V, VSEN=6.0V,
VOUT=6.0V, Cd: Open
Drain Output
Temperature Characteristics
Sense Resistance
(*4)
Undefined Operation
Detect Delay Time
(*5)
(*6)
Release Delay Time
(*7)
ΔVDF/
o
o
0.20
0.20
0.40
-40 C≦Ta≦85 C
±100
RSEN
VSEN=5.0V VIN=0V
E-4
MΩ
⑤
VUNS
VIN=VSEN=0～1.0V
0.3
0.4
V
⑦
tDF0
VIN=6.0V VSEN=6.0→0V
30
230
μs
⑨
tDR0
VIN=6.0V VSEN=0→6.0V
30
200
μs
⑨
(ΔTopr・VDF)
ppm/ C
NOTE:
*1: VDF (T): Nominal detect voltage
*2: Current to the sense resistor is not included.
*3: IOUT2 is applied only to the XC6118C series (CMOS output).
*4: It is calculated from the voltage value and the current value of the VSEN.
*5: Maximum VOUT voltage when VIN is changed from 0V to 1.0V under connecting the VIN pin to the VSEN pin.
This value is effective only to the XC6118C series (CMOS output).
*6: Delay time from the time of VSEN=VDF to the time of VOUT= 0.6V when the VSEN falls.
*7: Delay time from the time of VIN= VDF +VHYS to the time of VOUT = 5.4V when the VSEN rises.
8/20
XC6118
Series
■VOLTAGE CHART
SYMBOL
PARAMETER
NOMINAL
VOLTAGE
VDF(T)
(V)
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
E-1
DETECT VOLTAGE
(V)
(*1)
E-2
E-3
E-4
HYSTERESIS RANGE
(V)
HYSTERESIS RANGE
(V)
SENSE RESISTANCE
(MΩ)
VDF
MIN.
0.770
0.870
0.970
1.070
1.170
1.270
1.370
1.470
1.568
1.666
1.764
1.862
1.960
2.058
2.156
2.254
2.352
2.450
2.548
2.646
2.744
2.842
2.940
3.038
3.136
3.234
3.332
3.430
3.528
3.626
3.724
3.822
3.920
4.018
4.116
4.214
4.312
4.410
4.508
4.606
4.704
4.802
4.900
VHYS
MAX.
0.830
0.930
1.030
1.130
1.230
1.330
1.430
1.530
1.632
1.734
1.836
1.938
2.040
2.142
2.244
2.346
2.448
2.550
2.652
2.754
2.856
2.958
3.060
3.162
3.264
3.366
3.468
3.570
3.672
3.774
3.876
3.978
4.080
4.182
4.284
4.386
4.488
4.590
4.692
4.794
4.896
4.998
5.100
MIN.
0.015
0.017
0.019
0.021
0.023
0.025
0.027
0.029
0.031
0.033
0.035
0.037
0.039
0.041
0.043
0.045
0.047
0.049
0.051
0.053
0.055
0.057
0.059
0.061
0.063
0.065
0.067
0.069
0.071
0.073
0.074
0.076
0.078
0.080
0.082
0.084
0.086
0.088
0.090
0.092
0.094
0.096
0.098
VHYS
MAX.
0.066
0.074
0.082
0.090
0.098
0.106
0.114
0.122
0.131
0.085
0.147
0.155
0.163
0.171
0.180
0.188
0.196
0.204
0.212
0.220
0.228
0.237
0.245
0.253
0.261
0.269
0.277
0.286
0.294
0.302
0.310
0.318
0.326
0.335
0.343
0.351
0.359
0.367
0.375
0.384
0.392
0.400
0.408
MIN.
0
RSEN
MAX.
0.008
0.009
0.010
0.011
0.012
0.013
0.014
0.015
0.016
0.017
0.018
0.019
0.020
0.021
0.022
0.023
0.024
0.026
0.027
0.028
0.029
0.030
0.031
0.032
0.033
0.034
0.035
0.036
0.037
0.038
0.039
0.040
0.041
0.042
0.043
0.044
0.045
0.046
0.047
0.048
0.049
0.050
0.051
MIN.
TYP.
10
20
13
24
15
28
NOTE:
*1: When VDF(T)≦1.4V, the detection accuracy is ±30mV.
When VDF(T)≧1.5V, the detection accuracy is ±2%.
9/20
XC6118 Series
■TEST CIRCUITS
Circuit 2
Circuit 1
R=100kΩ
VIN
(No resistor needed for
VSEN
CMOS output products)
VOUT
XC6118 Series
V
Cd
VSS
Circuit 4
Circuit 3
VIN
VIN
VSEN
VOUT
VSEN
VOUT
XC6118 Series
A
XC6118 Series
A
Cd
Cd
VSS
VSS
Circuit 5
Circuit 6
VIN
VSEN
VOUT
XC6118 Series
A
Cd
VSS
Circuit 8
Circuit 7
R=100kΩ
VIN
VSEN
(No resistor needed for
VOUT
CMOS output products)
XC6118 Series
V
V
Cd
VSS
Circuit 9
R=100kΩ
(No resistor needed for CMOS output products)
Waveform Measurement Point
*No delay capacitance pin available in the XC6118xxxC/D series.
10/20
XC6118
Series
■OPERATIONAL EXPLANATION
A typical circuit example is shown in Figure 1, and the timing chart of Figure 1 is shown in Figure 2.
*The XC6118N series (N-ch open
drain output) requires a pull-up
resistor for pulling up output.
Figure 1: Typical application circuit example
Sense Pin Voltage: VSEN(MIN.:0V
MAX.:6.0V)
Release Voltage: VDF+VHYS
Detect Voltage: VDF
Delay Capacitance Pin Voltage: VCD(MIN.:VSS, MAX.:VIN)
Delay Capacitance Pin Threshold Voltage: VTCD
Output Voltage Pin Voltage: VOUT (MIN.:VSS MAX:VIN)
Figure 2: The timing chart of Figure 1
①
As an early state, the sense pin is applied sufficiently high voltage (6.0V MAX.) and the delay capacitance (Cd) is charged
to the power supply input voltage, (VIN: 1.0V MIN., 6.0V MAX.). While the sense pin voltage (VSEN) starts dropping to
reach the detect voltage (VDF) (VSEN>VDF), the output voltage (VOUT) keeps the “High” level (=VIN).
* If a pull-up resistor of the XC6118N series (N-ch open drain) is connected to added power supply different from the input
voltage pin, the “High” level will be a voltage value where the pull-up resistor is connected.
②
When the sense pin voltage keeps dropping and becomes equal to the detect voltage (VSEN =VDF), an N-ch transistor (M1)
for the delay capacitance (Cd) discharge is turned ON, and starts to discharge the delay capacitance (Cd). An inverter
(Inv.1) operates as a comparator of the reference voltage VIN, and the output voltage changes into the “Low” level (=VSS).
The detect delay time [tDF] is defined as time which ranges from VSEN=VDF to the VOUT of “Low” level (especially, when the
Cd pin is not connected: tDF0).
③
While the sense pin voltage keeps below the detect voltage, the delay capacitance (Cd) is discharged to the ground voltage
(=VSS) level. Then, the output voltage maintains the “Low” level while the sense pin voltage increases again to reach the
release voltage (VSEN< VDF +VHYS).
11/20
XC6118 Series
■OPERATIONAL EXPLANATION (Continued)
④
When the sense pin voltage continues to increase up to the release voltage level (VDF+VHYS), the N-ch transistor (M1) for
the delay capacitance (Cd) discharge will be turned OFF, and the delay capacitance (Cd) will start discharging via a delay
resistor (Rdelay). The inverter (Inv.1) will operate as a comparator (Rise Logic Threshold: VTLH=VTCD, Fall Logic
Threshold: VTHL=VSS) while the sense pin voltage keeps higher than the detect voltage (VSEN > VDF).
⑤
While the delay capacitance pin voltage (VCD) rises to reach the delay capacitance pin threshold voltage (VTCD) with the
sense pin voltage equal to the release voltage or higher, the sense pin will be charged by the time constant of the RC series
circuit. Assuming the time to the release delay time (tDR), it can be given by the formula (1).
tDR=-Rdelay×Cd×ln(1-VTCD/VIN) …(1)
The release delay time can also be briefly calculated with the formula (2) because the delay resistance is 2.0MΩ(TYP.) and
the delay capacitance pin voltage is VIN /2 (TYP.)
tDR=Rdelay×Cd×0.69 …(2)
*：Rdelay is 2.0MΩ（TYP.）
As an example, presuming that the delay capacitance is 0.68μF, tDR is :
2.0×106×0.68×10-6×0.69=938(ms)
* Note that the release delay time may remarkably be short when the delay capacitance (Cd) is not discharged to the ground
(=VSS) level because time described in ③ is short.
⑥
When the delay capacitance pin voltage reaches to the delay capacitance pin threshold voltage (VCD=VTCD), the inverter
(Inv.1) will be inverted. As a result, the output voltage changes into the “High” (=VIN) level. tDR0 is defined as time which
ranges from VSEN=VDF+VHYS to the VOUT of “High” level without connecting to the Cd.
⑦
While the sense voltage is higher than the detect voltage (VSEN > VDF), the delay capacitance pin is charged until the delay
capacitance pin voltage becomes the input voltage level. Therefore, the output voltage maintains the “High”(=VIN) level.
●Function Chart
VSEN
Cd
L
H
L
H
L
H
L
H
L
H
TRANSITION OF VOUT CONDITION *1
①
②
L
⇒
L
⇒
L
H
L
⇒
⇒
H
H
*1: VOUT transits from condition ① to ② because of the combination of VSEN and Cd.
●Example
ex. 1) VOUT ranges from ‘L’ to ‘H’ in case of VSEN = ‘H’ (VDR≧VSEN), Cd=’H’ (VTCD≧Cd) while VOUT is ‘L’.
ex. 2) VOUT maintains ‘H’ when Cd ranges from ‘H’ to ‘L’, VSEN=’H’ and Cd=’L’ when VOUT becomes ‘H’ in ex.1.
●Release Delay Time Chart
DELAY
CAPACITANCE [Cd]
(μF)
RELEASE DELAY TIME [tDR]
(TYP.)
(ms)
RELEASE DELAY TIME [tDR] *2
(MIN. ~ MAX.)
(ms)
0.010
0.022
0.047
0.100
0.220
0.470
1.000
13.8
30.4
64.9
138
304
649
1380
11.0 ~ 16.6
24.3 ~ 36.4
51.9 ~ 77.8
110 ~ 166
243 ~ 364
519 ~ 778
1100 ~ 1660
* The release delay time values above are calculated by using the formula (2).
*2: The release delay time (tDR) is influenced by the delay capacitance Cd.
12/20
XC6118
Series
■NOTES ON USE
1. Use this IC within the stated maximum ratings. Operation beyond these limits may cause degrading or permanent damage
to the device.
2. The power supply input pin voltage drops by the resistance between power supply and the VIN pin, and by through current at
operation of the IC.
At this time, the operation may be wrong if the power supply input pin voltage falls below the minimum
operating voltage range. In CMOS output, for output current, drops in the power supply input pin voltage similarly occur.
Moreover, in CMOS output, when the VIN pin and the sense pin are short-circuited and used, oscillation of the circuit may
occur if the drops in voltage, which caused by through current at operation of the IC, exceed the hysteresis voltage. Note it
especially when you use the IC with the VIN pin connected to a resistor.
3. When the setting voltage is less than 1.0V, be sure to separate the VIN pin and the sense pin, and to apply the voltage over
1.0V to the VIN pin.
4. Note that a rapid and high fluctuation of the power supply input pin voltage may cause a wrong operation.
5. Power supply noise may cause operational function errors, Care must be taken to put the capacitor between VIN-GND and
test on the board carefully.
6. When there is a possibility of which the power supply input pin voltage falls rapidly (e.g.: 6.0V to 0V) at release operation
with the delay capacitance pin (Cd) connected to a capacitor, use a Schottky barrier diode connected between the VIN pin
and the Cd pin as the Figure 3 shown below.
7. In N channel open drain output, VOUT voltage at detect and release is determined by resistance of a pull up resistor
connected at the VOUT pin. Please choose proper resistance values with refer to Figure 4;
During detection: VOUT = VPULL / (1+RPULL / RON)
VPULL: Pull up voltage
RON(※1)：On resistance of N channel driver M3 can be calculated as VDS / IOUT1 from electrical characteristics,
For example, when (※2) RON = 0.5 / 0.8×10-3 = 625Ω（MIN.）at VIN=2.0V, VPULL = 3.0V and VOUT ≦0.1V at detect,
RPULL= (VPULL /VOUT-1)×RON= (3 / 0.1-1)×625≒18ｋΩ
In this case, RPULL should be selected higher or equal to 18kΩ in order to keep the output voltage less than 0.1V during
detection.
(※1) RON is bigger when VIN is smaller, be noted.
(※2) For calculation, Minimum VIN should be chosen among the input voltage range.
During releasing：VOUT = VPULL / (1 + RPULL / ROFF)
VPULL：Pull up voltage
ROFF：On resistance of N channel driver M3 is 15MΩ（MIN.） when the driver is off (as to VOUT / ILEAK)
For example：when VPULL = 6.0V and VOUT ≧ 5.99V,
RPULL = (VPULL / VOUT-1)×ROFF = (6/5.99-1)×15×106 ≒25 kΩ
In this case, RPULL should be selected smaller or equal to 25 kΩ in order to obtain output voltage higher than 5.99V during
releasing.
R=100kΩ
VIN
(No resistor needed for
CMOS output products)
VSEN
VIN
VOUT
VSEN
VOUT
Cd
Cd
VSS
NOTE：ROFF=VOUT/ILEAK
Figure 3: Circuit example with the delay capacitance pin (Cd)
connected to a Schottky barrier diode
Figure 4: Circuit example of XC6118N Series
13/20
XC6118 Series
■TYPICAL PERFORMANCE CHARACTERISTICS
(1) Supply Current vs. Sense Voltage
XC6118C25Ax
VIN=3.0V
Supply Current: ISS (μA)
2.0
Ta=85℃
1.5
25℃
1.0
0.5
-40℃
0.0
0
1
2
3
4
5
6
Sense Voltage: VSEN (V)
(2) Supply Current vs. Input Voltage
XC6118C25Ax
XC6118C25Ax
VSEN=2.75V
VSEN=2.25V
1.2
Supply Current: ISS (μA)
Supply Current: ISS (μA)
1.2
1.0
Ta=85℃
0.8
25℃
0.6
0.4
-40℃
0.2
0.0
0
1
2
3
4
5
Ta=85℃
1.0
0.8
0.6
25℃
0.4
-40℃
0.2
0.0
0
6
1
2
3
4
5
6
Input Voltage: VIN (V)
Input Voltage: VIN (V)
(4) Detect Voltage vs. Input Voltage
(3) Detect Voltage vs. Ambient Temperature
XC6118C25Ax
XC6118C25Ax
VIN=4.0V
2.55
Detect Voltage: VDF (V)
Detect Voltage: VDF (V)
2.55
2.50
2.45
85℃
2.50
-40℃
2.45
-50
-25
0
25
50
75
Ambient Temperature: Ta (℃)
14/20
Ta=25℃
100
1.0
2.0
3.0
4.0
5.0
Input Voltage: VIN (V)
6.0
XC6118
Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(5) Hysteresis Voltage vs. Ambient Temperature
(6) CD Pin Sink Current vs. Input Voltage
XC6118C25Ax
XC6118C25Ax
VSEN=0V VDS=0.5V
Cd PIN Current: ICD (mA)
Hysteresis Voltage: VHYS (V)
VIN=4.0V
0.20
0.15
0.10
0.05
-50
-25
0
25
50
75
3.0
2.5
Ta=-40℃
2.0
25℃
1.5
1.0
85℃
0.5
0.0
0
100
1
Ambient Temperature: Ta (℃)
Output Voltage: VOUT (V)
Output Voltage: VOUT (V)
6.0
VIN=6.0V
5.0
4.0
4.0V
3.0
2.0
1.0
1.0V
0.0
-1.0
3
5
6
VSEN=VIN Pull-up=VIN R=100kΩ
Ta=25℃
7.0
2
4
XC6118N25Ax
XC6118C25Ax
1
3
(8) Output Voltage vs. Input Voltage
(7) Output Voltage vs. Sense Voltage
0
2
Input Voltage : VIN (V)
4
5
4.0
3.0
Ta=85℃
2.0
25℃
1.0
-40℃
0.0
-1.0
0
6
0.5
1
1.5
2
2.5
3
Input Voltage : VIN (V)
Sense Voltage: VSEN (V)
(9) Output Current vs. Input Voltage
XC6118C25Ax
XC6118C25Ax
VDS(Pch)=0.5V
VDS(Nch)=0.5V
0.0
3.5
Output Current: Iout (mA)
Output Current: Iout (mA)
4.0
Ta=-40℃
3.0
25℃
2.5
2.0
1.5
85℃
1.0
0.5
0.0
Ta=85℃
-0.5
-1.0
25℃
-1.5
-40℃
-2.0
0
1
2
3
4
5
Input Voltage : VIN (V)
6
0
1
2
3
4
5
6
Input Voltage : VIN (V)
15/20
XC6118 Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(10) Delay Resistance vs. Ambient Temperature
(11) Release Delay Time vs. Delay Capacitance
XC6118C25Ax
Delay Resistance: Rdelay (MΩ)
VSEN=6.0V VCD=0.0V VIN=5.0V
4
3.5
3
2.5
2
1.5
1
-50
-25
0
25
50
75
Release Delay time: TDR (ms)
XC6118C25Ax
100
Ta=25℃
10000
VIN=1.0V
3.0V
6.0V
1000
100
10
1
tDR=Cd×2.0×10 6 ×0.69
0.1
0.0001
0.001
(12) Detect Delay Time vs. Delay Capacitance
XC6118N25Ax
VIN=6.0V
4.0V
3.0V
2.0V
1.0V
0.001
0.01
0.1
1
Delay Capacitor: Cd (μF)
XC6118N25Ax
Leak Current: ILEAK (μA)
VIN=VSEN=6.0V
0.25
0.20
0.15
0.10
0
1
2
3
4
5
Output Voltage: VOUT (V)
0.25
0.20
0.15
0.10
-50
-25
0
25
50
75
Ambient Temperature: Ta (℃)
(14) Leakage Current vs. Supply Voltage
16/20
VIN=VSEN=6.0V VOUT=6.0V
1000
Leak Current: ILEAK (μA)
Detect Delay time: TDF (μs)
Ta=25℃
1
0.0001
1
(13) Leakage Current vs. Ambient Temperature
XC6118C25Ax
10
0.1
Delay Capacitor: Cd (μF)
Ambient Temperature: Ta (℃)
100
0.01
6
100
XC6118
Series
●SOT-25
1.3MAX
1.1±0.1
+0.2
1.6
-0.1
2.8±0.2
●USP-4
0.2MIN
■PACKAGING INFORMATION
●USP-4 Reference Pattern Layout
1.0
0.35
0.35
4
3
1
2
0.6
0.3
1.9
0.5
0.3
●USP-4 Reference Metal Mask Design
17/20
XC6118 Series
■MARKING RULE
●SOT-25
① represents output configuration and integer number of detect voltage
CMOS Output (XC6118C Series)
MARK
VOLTAGE (V)
L
0.X
M
1.X
N
2.X
P
3.X
R
4.X
S
5.X
N-ch Open Drain Output (XC6118N Series)
MARK
T
U
V
X
Y
Z
VOLTAGE (V)
0.X
1.X
2.X
3.X
4.X
5.X
5
①
4
②
1
③
④
2
SOT-25
(TOP VIEW)
② represents decimal number of detect voltage
(ex.)
MARK
VOLTAGE (V)
PRODUCT SERIES
3
0
X.3
X.0
XC6118**3***
XC6118**0***
③ represents options
MARK
A
B
C
D
OPTIONS
Built-in delay capacitance pin with hysteresis 5% (TYP.)
(Standard)
Built-in delay capacitance pin with hysteresis less than 1%
(Standard)
No built-in delay capacitance pin with hysteresis 5% (TYP.)
(Semi-custom)
No built-in delay capacitance pin with hysteresis less than 1%
(Semi-custom)
④⑤ represents production lot number
0 to 9 A to Z, or inverted characters of 0 to 9, A to Z repeated.
(G, I, J, O, Q, and W excluded)
*No character inversion used.
18/20
PRODUCT SERIES
XC6118***A**
XC6118***B**
XC6118***C**
XC6118***D**
⑤
3
XC6118
Series
■MARKING RULE (Continued)
●USP-4
① represents output configuration and integer number of detect voltage
N-ch Open Drain Output (XC6118N Series)
VOLTAGE (V)
0.X
1.X
2.X
3.X
4.X
5.X
1
④ ⑤
MARK
T
U
V
X
Y
Z
2
① ② ③
CMOS Output (XC6118C Series)
MARK
VOLTAGE (V)
L
0.X
M
1.X
N
2.X
P
3.X
R
4.X
S
5.X
4
3
USP-4
(TOP VIEW)
② represents decimal number of detect voltage
(ex.)
MARK
3
0
VOLTAGE (V)
X.3
X.0
PRODUCT SERIES
XC6118**3***
XC6118**0***
③ represents options
MARK
OPTIONS
Built-in delay capacitance pin with hysteresis 5% (TYP.)
A
(Standard)
Built-in delay capacitance pin with hysteresis less than 1%
B
(Standard)
No built-in delay capacitance pin with hysteresis 5% (TYP.)
C
(Semi-custom)
No built-in delay capacitance pin with hysteresis less than 1%
D
(Semi-custom)
PRODUCT SERIES
XC6118***A**
XC6118***B**
XC6118***C**
XC6118***D**
④⑤ represents production lot number
0 to 9, A to Z or inverted characters of 0 to 9, A to Z repeated.
(G, I, J, O, Q, and W excluded)
*No character inversion used.
19/20
XC6118 Series
1. The products and product specifications contained herein are subject to change without
notice to improve performance characteristics.
Consult us, or our representatives
before use, to confirm that the information in this datasheet is up to date.
2. We assume no responsibility for any infringement of patents, patent rights, or other
rights arising from the use of any information and circuitry in this datasheet.
3. Please ensure suitable shipping controls (including fail-safe designs and aging
protection) are in force for equipment employing products listed in this datasheet.
4. The products in this datasheet are not developed, designed, or approved for use with
such equipment whose failure of malfunction can be reasonably expected to directly
endanger the life of, or cause significant injury to, the user.
(e.g. Atomic energy; aerospace; transport; combustion and associated safety
equipment thereof.)
5. Please use the products listed in this datasheet within the specified ranges.
Should you wish to use the products under conditions exceeding the specifications,
please consult us or our representatives.
6. We assume no responsibility for damage or loss due to abnormal use.
7. All rights reserved. No part of this datasheet may be copied or reproduced without the
prior permission of TOREX SEMICONDUCTOR LTD.
20/20