RMPA1759 Korean-PCS PowerEdge™ Power Amplifier Module General Description Features The RMPA1759 power amplifier module (PAM) is designed for Korean CDMA and CDMA2000-1X personal communications system (PCS) applications. The 2 stage PAM is internally matched to 50Ω to minimize the use of external components and features a low-power mode to reduce standby current and DC power consumption during peak phone usage. High power-added efficiency and excellent linearity are achieved using our InGaP Heterojunction Bipolar Transistor (HBT) process. • Single positive-supply operation and low power and shutdown modes • 38% CDMA efficiency at +28dBm average output power • Compact LCC package- 4.0 x 4.0 x 1.5 mm with industry standard pinout • Internally matched to 50Ω and DC blocked RF input/ output. • Meets CDMA2000-1XRTT performance requirements Device Absolute Ratings1 Symbol Vcc1, Vcc2 Vref Vmode Pin TSTG Parameter Supply Voltages Reference Voltage Power Control Voltage RF Input Power Storage Temperature Value 5.0 2.6 to 3.5 3.5 +10 -55 to +150 Units V V V dBm °C Note: 1: No permanent damage with only one parameter set at extreme limit. Other parameters set to typical values. ©2004 Fairchild Semiconductor Corporation RMPA1759 Rev. C RMPA1759 September 2004 VCC1, VCC2 (1, 10) PA MODULE COLLECTOR BIAS GND (3,6, 7, 9, 11) INTERSTAGE MATCH RF IN (2) INPUT MATCHING NETWORK INPUT STAGE MMIC INPUT STAGE BIAS OUTPUT MATCHING NETWORK OUTPUT STAGE RF OUT (8) OUTPUT STAGE BIAS VCC=3.4V (nom) VREF=2.85V (nom) 1720-1780 MHz 50Ω I/O BIAS CONTROL VREF (5) Vmode (4) Electrical Characteristics1 Symbol Parameter f Operating Frequency CDMA Operation SSg Small-Signal Gain Gp Power Gain Po Linear Output Power Min 1720 Typ Max 1780 26 27 Units MHz PAE (digital) @ +28 dBm PAE (digital) @ +16 dBm PAEd (digital) @ +16 dBm Itot High Power Total Current Low Power Total Current Adjacent Channel Power Ratio ACPR1 ±1.25 MHz Offset 38 9 20 490 120 dB dB dBm dBm % % % mA mA -50 -48 dBc dBc ACPR2 ±2.25 MHz Offset -60 -62 dBc dBc 28 16 PAEd General Characteristics VSWR Input Impedance NF Noise Figure Rx No Receive Band Noise Power 2fo-5fo Harmonic Suppression S Spurious Outputs2, 3 Ruggedness w/ Load Mismatch3 Tc Case Operating Temperature ©2004 Fairchild Semiconductor Corporation 2.0:1 4 -139 -30 -30 -60 10:1 85 Comments Po = 0 dBm Po = +28 dBm; Vmode = 0V Vmode = 0V Vmode ≥ 2.0V Vmode = 0V Vmode ≥ 2.0V Vmode ≥ 2.0V, Vcc = 1.4V Po = +28 dBm, Vmode = 0V Po = +16 dBm, Vmode = 2.0V Po = +28 dBm; Vmode = 0V, IS-95 Po = +28 dBm; Vmode = 0.0V, CDMA2000-1X Po = +28 dBm; Vmode = 0V, IS-95 Po = +28 dBm; Vmode = 0.0V, CDMA2000-1X dB dBm/Hz Po ≤ +28 dBm; 1920 to 1980 MHz dBc Po ≤ +28 dBm dBc Load VSWR ≤ 5.0:1 No permanent damage. °C RMPA1759 Rev. C RMPA1759 Module Block Diagram Min Typ Max Units 50 5 1 8 10 mA mA µA RMPA1759 Symbol Parameter DC Characteristics Iccq Quiescent Current Iref Reference Current Icc(off) Shutdown Leakage Current Comments Vmode ≥ 2.0V Po ≤ +28 dBm No applied RF signal. Notes: 1: All parameters met at Tc = +25°C, Vcc = +3.4V, f=1950 MHz and load VSWR ≤ 1.2:1. 2: All phase angles. 3: Guaranteed by design. Recommend Operating Conditions Symbol f Vcc1, Vcc2 Vref Vmode Pout Tc Parameter Operating Frequency Supply Voltage Reference Voltage (Operating) (Shutdown) Bias Control Voltage (low-power) (high-power) Linear Output Power (high-power) (low-power) Case Operating Temperature Min 1720 3.0 Typ 2.7 0 1.8 0 -30 Max 1780 4.2 Units MHz V 2.85 3.1 0.5 V V 2.0 3.0 0.5 V V +28 +16 +85 dBm dBm °C 3.4 Note: 1: RF input power for CDMA Pout = +28dBm. ©2004 Fairchild Semiconductor Corporation RMPA1759 Rev. C RMPA1759 Evaluation Board Layout Evaluation Board Schematic 1000 pF 3.3 µF SMA1 RF IN 1000 pF 10 3.3 µF Vcc2 Vcc1 2 50Ω TRL 4 Vmode 1000 pF ©2004 Fairchild Semiconductor Corporation Vref Fairchild 50Ω TRL RMPA1759 PPYYWW 3,6,7,9 5 0.1 µF 8 SMA2 RF OUT 11 (package base) RMPA1759 Rev. C RMPA1759 Package Outline I/O 1 INDICATOR TOP VIEW 10 1 FRF 2 (4.00mm +.100 –.050 ) SQUARE 3 4 5 PA1959 PPYYWW U31XX 9 8 7 6 1.60mm MAX. FRONT VIEW .25mm TYP. 3.50mm TYP. See Detail A .40mm .10mm .30mm TYP. .10mm .85mm TYP. 11 3.65mm .40mm .45mm 1.08mm .18mm 1.84mm DETAIL A. TYP. BOTTOM VIEW Package Pinout Pin # 1 2 3 4 5 6 7 8 9 10 11 Symbol Vcc1 RF In GND Vmode Vref GND GND RF Out GND Vcc2 GND Description Supply Voltage to Input Stage RF Input Signal Ground High-Power/Low-Power Mode Control Reference Voltage Ground Ground RF Output Signal Ground Supply Voltage to Output Stage Paddle Ground DC Turn-On Sequence 1) Vcc1 = Vcc2 = 3.4V (typical) 2) Vref = 2.85V (typical) 3) Vmode = 2.0V (Pout < 16dBm), 0V (Pout > 16dBm) ©2004 Fairchild Semiconductor Corporation RMPA1759 Rev. C CAUTION: THIS IS AN ESD SENSITIVE DEVICE Precautions to Avoid Permanent Device Damage: • Cleanliness: Observe proper handling procedures to ensure clean devices and PCBs. Devices should remain in their original packaging until component placement to ensure no contamination or damage to RF, DC & ground contact areas. • Device Cleaning: Standard board cleaning techniques should not present device problems provided that the boards are properly dried to remove solvents or water residues. • Static Sensitivity: Follow ESD precautions to protect against ESD damage: – A properly grounded static-dissipative surface on which to place devices. – Static-dissipative floor or mat. – A properly grounded conductive wrist strap for each person to wear while handling devices. • General Handling: Handle the package on the top with a vacuum collet or along the edges with a sharp pair of bent tweezers. Avoiding damaging the RF, DC, & ground contacts on the package bottom. Do not apply excessive pressure to the top of the lid. • Device Storage: Devices are supplied in heat-sealed, moisture-barrier bags. In this condition, devices are protected and require no special storage conditions. Once the sealed bag has been opened, devices should be stored in a dry nitrogen environment. Device Usage: Fairchild recommends the following procedures prior to assembly. • Dry-bake devices at 125°C for 24 hours minimum. Note: The shipping trays cannot withstand 125°C baking temperature. • Assemble the dry-baked devices within 7 days of removal from the oven. • During the 7-day period, the devices must be stored in an environment of less than 60% relative humidity and a maximum temperature of 30°C Solder Materials & Temperature Profile: Reflow soldering is the preferred method of SMT attachment. Hand soldering is not recommended. • Reflow Profile – Ramp-up: During this stage the solvents are evaporated from the solder paste. Care should be taken to prevent rapid oxidation (or paste slump) and solder bursts caused by violent solvent out-gassing. A typical heating rate is 1- 2°C/sec. – Pre-heat/soak: The soak temperature stage serves two purposes; the flux is activated and the board and devices achieve a uniform temperature. The recommended soak condition is: 120-150 seconds at 150°C. – Reflow Zone: If the temperature is too high, then devices may be damaged by mechanical stress due to thermal mismatch or there may be problems due to excessive solder oxidation. Excessive time at temperature can enhance the formation of intermetallic compounds at the lead/board interface and may lead to early mechanical failure of the joint. Reflow must occur prior to the flux being completely driven off. The duration of peak reflow temperature should not exceed 10 seconds. Maximum soldering temperatures should be in the range 215-220°C, with a maximum limit of 225°C. – Cooling Zone: Steep thermal gradients may give rise to excessive thermal shock. However, rapid cooling promotes a finer grain structure and a more crackresistant solder joint. The illustration below indicates the recommended soldering profile. Solder Joint Characteristics: Proper operation of this device depends on a reliable voidfree attachment of the heatsink to the PWB. The solder joint should be 95% void-free and be a consistent thickness. Rework Considerations: Rework of a device attached to a board is limited to reflow of the solder with a heat gun. The device should not be subjected to more than 225°C and reflow solder in the molten state for more than 5 seconds. No more than 2 rework operations should be performed. • If the 7-day period or the environmental conditions have been exceeded, then the dry-bake procedure must be repeated. ©2004 Fairchild Semiconductor Corporation RMPA1759 Rev. C RMPA1759 Application Information RMPA1759 240 10 SEC 220 200 183°C 180 160 140 DEG (°C) 120 100 1°C/SEC SOAK AT 150°C FOR 60 SEC 80 45 SEC (MAX) ABOVE 183°C 1°C/SEC 60 40 20 0 0 60 120 180 240 300 TIME (SEC) Figure 1. Recommended Solder Reflow Profile ©2004 Fairchild Semiconductor Corporation RMPA1759 Rev. C TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FAST ActiveArray™ FASTr™ Bottomless™ FPS™ CoolFET™ FRFET™ CROSSVOLT™ GlobalOptoisolator™ DOME™ GTO™ EcoSPARK™ HiSeC™ E2CMOS™ I2C™ EnSigna™ i-Lo™ FACT™ ImpliedDisconnect™ FACT Quiet Series™ ISOPLANAR™ LittleFET™ MICROCOUPLER™ MicroFET™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ OPTOLOGIC Across the board. Around the world.™ OPTOPLANAR™ PACMAN™ The Power Franchise POP™ Programmable Active Droop™ Power247™ PowerEdge™ PowerSaver™ PowerTrench QFET QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ µSerDes™ SILENT SWITCHER SMART START™ SPM™ Stealth™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic TINYOPTO™ TruTranslation™ UHC™ UltraFET VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I13