ATMEL T48C510

T48C510
MARC4 – 4-bit MTP Universal Microcontroller
The T48C510 is an Multi Time Programmable (MTP) microcontroller which is pin and functionally compatible to the
Atmel Wireless & Microcontrollers’ M44C510E mask programmable microcontroller. It contains EEPROM, RAM,
up to 34 digital I/O pins, up to 10 maskable external interrupt sources, 4 maskable internal interrupts, a watchdog timer,
interval timer, 2 x 8-bit multifunction timer/counter module and a versatile software configurable on-chip system clock
module.
Features / Benefits
Programmable system clock with prescaler and five
different clock sources:
– Up to 8-MHz crystal oscillator (system clock)
– 32-kHz crystal oscillator
– RC-oscillator fully integrated
– RC-oscillator with external resistor adjustment
– External clock input
I/O ports – bitwise configurable with combined interrupt handling (for serial I/O applications)
Wide supply-voltage range (2.4 V to 6.2 V)
Various power-down modes
Very low halt current
Efficient, hardware-controlled interrupt handling
4 KByte program EEPROM, 256 x 4-bit RAM
High-level programming language in qFORTH
8 hard- and software interrupt priority levels
Comprehensive library of useful routines
Up to 10 external and 4 internal interrupts, bitwise
maskable with programmable priority level
Windows 95/NT based development and programmer
tools
2 x 8-bit multifunction timer/counters
Coded reset and watchdog timer
Power-on reset and “brown out” function
Up to 34 I/O lines
TE
Config.
EEPROM
OSCIN OSCOUT AVDD VSS
SCLIN
System
clock
Test
Sleep
EEPROM
4K x 8 bit
Real time
clock
VDD TIM1
NRST
Master
reset
Timer/
counter
RAM
Watch–
dog
256 x 4 bit
Prescaler
Timer 1
Timer 0
MARC4
Melody
& buzzer
4-bit CPU core
I/O bus
I/O
I/O
4
PM
4
I/O
4
I/O
I/O
I/O
4
Port 0 Port 1 Port 5 Port 7
Interrupt
& reset
4
Port A
I/O I/O
Interrupt
I/O
Interrupt
4
4
Port B
Port C
2
Port 6
4
Port 4
16536
Figure 1. Block diagram
Rev. A2, 26-Feb-01
1 (61)
Preliminary Information
T48C510
Ordering Information
Extended Type Number
Package
Remarks
BPC2
AVDD
OSCIN
OSCOUT
NRST
BPA0
BPA1
BPA2
BPA3
30
29
28
27
26
25
24
23
15
BPC1 16
17
BPC0 18
19
20
21
22
TIM1
BP13
BP12
BP11
BP10
BPC3
31
14
BPB0
32
BP00
BPB1
BPB3
36
33
BP60
37
BPB2
BP61
38
34
SCLIN
39
35
BP73
PM
40
BP72
41
Taped and reeled
BP71
SSO44
42
T48C510 – ILQ
BP70
Stick
43
SSO44
44
T48C510 – ILS
3
4
5
6
7
8
9
10
11
12
13
BP52
BP51
BP50
VDD
BP43
BP42
BP41
BP40
BP03
BP02
BP01
TE
2
1
V SS
BP53
T48C510
Figure 2. Pin connections SSO44-package
Table 1 Pin description
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Name
Function
VDD
Power supply voltage +2.4 V to +6.2 V
AVDD
Analog power supply voltage +2.4 V to +6.2 V
VSS
Circuit ground
BP00 – BP03
4 I/O lines of Port 0 – automatic nibblewise configurable / programmer interface
BP10 – BP13
4 I/O lines of Port 1 – automatic nibblewise configurable
BP50 – BP53
4 I/O lines of high current Port 5 – bitwise configurable
BP70 – BP73
4 I/O lines of high current Port 7 – bitwise configurable
BPA0 – BPA3
4 I/O lines of Port A – bitwise configurable, as inputs to a port monitor module and optional
coded reset inputs
BPB0 – BPB3
4 I/O lines of Port B – bitwise configurable I/O and as inputs to a port monitor module
BPC0 – BPC3
4 I/O lines of Port C – bitwise configurable I/O
BP60 – BP61
2 I/O lines of Port 6 – bitwise configurable I/O or as external programmable interrupts
BP40 (T0OUT0)
I/O line BP40 of Port 4 – configurable or timer/counter I/O T0OUT0
BP41 (T0OUT1)
I/O line BP41 of Port 4 – configurable or timer/counter I/O T0OUT1
BP42 (BUZ)
BP43 (NBUZ)
High current I/O line BP42 of Port 4 – configurable or buzzer output BUZ
High current I/O line BP43 of Port 4 – configurable or buzzer output NBUZ
TIM1
Dedicated I/O for Timer 1
SCLIN
External trimming resistor or external clock input
OSCIN
32-kHz quartz crystal or 4-MHz quartz crystal input pin
OSCOUT
32-kHz quartz crystal or 4-MHz quartz crystal output pin
TE
NRST
PM
Testmode input, used to control the production test modes (internal pull-down)
Reset input (/output), a logic low on this pin resets the device. An internal watchdog or
coded reset can cause a low pulse on this pin.
MTP program mode enable pin (internal pull-down)
2 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
Table of Contents
1
2
MARC4 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Components of MARC4 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.2
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.3
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.4
ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.5
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.6
I/O Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.1
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2
Software Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.1
Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.2
Oscillator Circuits and External Clock Input Stage . . . . . . . . . . . . . . . . . . . . . . . .
RC-Oscillator 1 Fully Integrated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RC-Oscillator 2 with External Trimming Resistor . . . . . . . . . . . . . . . . . . . . . . . . .
4-MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-kHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quartz Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.3
Clock Management Register (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Configuration Register (SC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.4
Power-down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.5
Clock Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Addressing Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Bidirectional Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1
Bidirectional Port 0 and Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2
Bidirectional Port 5, Port 7 and Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3
Bidirectional Port A and Port B with Port Monitor Function . . . . . . . . . . . . . . . .
2.2.4
Bidirectional Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5
Bidirectional Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.6
TIM1 – Dedicated Timer 1 I/O Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Interval Timers / Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1
Interval Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5
Timer/Counter Module (TCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1
General Timer/Counter Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.2
Timer/Counter in 16-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.3
Timer 0 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.4
Timer 1 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. A2, 26-Feb-01
5
5
5
5
6
6
9
9
9
9
11
11
12
13
13
14
14
14
14
15
15
15
16
16
17
17
18
18
21
22
23
23
25
27
28
28
29
30
30
32
35
35
44
3 (61)
Preliminary Information
T48C510
Table of Contents (continued)
2.6
2.7
2.8
3
4
5
Buzzer Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Noise Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.1
Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.2
Electromagnetic Emission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
DC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 (61)
47
49
50
50
51
51
51
51
53
57
57
58
59
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
1
MARC4 Architecture
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
MARC4 CORE
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
X
Reset ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
Program
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
Y
RAM
PC
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
SP
memory
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
RP
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏ
Instruction
bus
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏ
Memory
bus
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
Instruction
TOS
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
decoder
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
System
CCR
ALU
clock ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
Interrupt
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
controller
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
I/O bus
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
256 x 4-bit
Reset
Clock
Sleep
On–chip peripheral modules
94 8973
Figure 3. MARC4 core
1.1
General Description
The functionality, programming and pinning of the
T48C510 is compatible with the M44C510E mask programmable microcontroller from Atmel Wireless &
Microcontrollers. All on-chip modules are addressed and
controlled with exactly the same programming code, so
that a program targeted for the M44C510E can be read
directly into the T48C510 and will operate in the same
fashion.
The MARC4 microcontroller consists of an advanced
stack based 4-bit CPU core and on-chip peripherals. The
CPU is based on the HARVARD architecture with physically separate program memory (EEPROM) and data
memory (RAM). Three independent buses, the instruction bus, the memory bus and the I/O bus are used for
parallel communication between EEPROM, RAM and
peripherals. This enhances program execution speed by
allowing both instruction prefetching, and a simultaneous
communication to the on-chip peripheral circuitry. The
extremely powerful integrated interrupt controller with
associated eight prioritized interrupt levels supports fast
and efficient processing of hardware events. The MARC4
is designed for the high-level programming language
qFORTH. The core includes an expression and a return
stack. This architecture allows high-level language programming without any loss in efficiency or code density.
1.2
Components of MARC4 Core
The core contains EEPROM, RAM, ALU, a program
counter, RAM address registers, an instruction decoder
and an interrupt controller. The following sections describe each functional block in more detail:
1.2.1
EEPROM
The program memory (EEPROM) is programmed with
the customer application program. The EEPROM is addressed by a 12-bit wide program counter, thus
predefining a maximum program bank size of 4 Kbytes.
Rev. A2, 26-Feb-01
5 (61)
Preliminary Information
T48C510
1F8 h
1F0h
1 E8h
1 E0h
FFFh
SCALL addresses
EEPROM
(4K x 8 bit)
Z ero
p age
0 20 h
01 8 h
01 0 h
00 8h
0 00 h
1FFh
Zero page
000h
1 E0 h
INT7
1 C0 h
INT6
18 0h
INT5
14 0h
INT4
1 00 h
INT3
0 C0 h
INT2
0 80 h
INT1
04 0h
INT0
00 8h
0 00 h
$RESET
$AUTOSLEEP
Figure 4. EEPROM map of T48C510
The lowest user EEPROM address segment is taken up by
a 512-byte zero page which contains predefined start
addresses for interrupt service routines and special subroutines accessible with single-byte instructions
(SCALL). The corresponding memory map is shown in
figure 4. Look-up tables of constants can also be held in
EEPROM and are accessed via the MARC4’s built-in
TABLE instruction.
1.2.2
RAM
The MARC4 contains 256 x 4-bit wide static random
access memory (RAM). It is used for the expression stack,
the return stack and data memory for variables and arrays.
The RAM is addressed by any of the four 8-bit wide RAM
address registers SP, RP, X and Y.
Return Stack
The 12-bit wide return stack is addressed by the return
stack pointer (RP). It is used for storing return addresses
of subroutines, interrupt routines and for keeping loop
index counts. The return stack can also be used as a
temporary storage area.
The MARC4 instruction set supports the exchange of data
between the top elements of the expression stack and the
return stack. The two stacks within the RAM have a userdefinable location and maximum depth.
1.2.3
Registers
The MARC4 controller has seven programmable registers and one condition code register. They are shown in
figure 6.
Expression Stack
Program Counter (PC)
The 4-bit wide expression stack is addressed with the
expression stack pointer (SP). All arithmetic, I/O and
memory reference operations take their operands from,
and return their result to the expression stack. The
MARC4 performs the operations with the top of stack
items (TOS and TOS-1). The TOS register contains the
top element of the expression stack and works in the same
way as an accumulator. This stack is also used for passing
parameters between subroutines and as a scratch pad area
for temporary storage of data.
The program counter (PC) is a 12-bit register that contains
the address of the next instruction to be fetched from the
EEPROM. Instructions currently being executed are decoded in the instruction decoder to determine the internal
micro operations. For linear code (no calls or branches)
the program counter is incremented with every instruction cycle. If a branch, call, return instruction or an
interrupt is executed, the program counter is loaded with
a new address. The program counter is also used with the
TABLE instruction to fetch 8-bit wide constants.
6 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
RAM
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(256 x 4-bit)
Autosleep
RAM address register:
FCh
3
SP
Global
variables
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TOS–1
RP
SP
4-bit
Expression
stack
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Return stack
11
Return
stack
Global
vvariables
07h
03h
04h
00h
0
TOS
TOS–1
TOS–2
FFh
X
Y
ÏÏÏ
ÏÏÏ
Expression stack
0
12-bit
RP
94 8975
Figure 5. RAM map
RAM Address Registers
The RAM is addressed with the four 8-bit wide RAM
address registers: SP, RP, X and Y. These registers allow
access to any of the 256 RAM nibbles.
Expression Stack Pointer (SP)
preincrement or postdecrement, addressing mode arrays
in the RAM can be compared, filled or moved.
Top Of Stack ( TOS )
The top of stack register is the accumulator of the
MARC4. All arithmetic/logic, memory reference and I/O
operations use this register. The TOS register receives
data from the ALU, EEPROM, RAM or I/O bus.
The stack pointer (SP) contains the address of the next-totop 4-bit item (TOS-1) of the expression stack. The
pointer is automatically preincremented if a nibble is
moved onto the stack, or postdecremented if a nibble is
removed from the stack. Every postdecrement operation
moves the item (TOS-1) to the TOS register before the SP
is decremented. After a reset the stack pointer has to be
initialized with “ >SP S0 ” to allocate the start address of
the expression stack area.
The 4-bit wide condition code register contains the
branch, the carry and the interrupt-enable flag. These bits
indicate the current state of the CPU. The CCR flags are
set or reset by ALU operations. The instructions
SET_BCF, TOG_BF, CCR! and DI allow direct
manipulation of the condition code register.
Return Stack Pointer (RP)
Carry/Borrow ( C )
The return stack pointer points to the top element of the
12-bit wide return stack. The pointer automatically preincrements if an element is moved onto the stack or it
postdecrements if an element is removed from the stack.
The return stack pointer increments and decrements in
steps of 4. This means that every time a 12-bit element is
stacked, a 4-bit RAM location is left unwritten. These
locations are used by the qFORTH compiler to allocate
4-bit variables. After a reset, the return stack pointer has
to be initialized with “>RP FCh ”.
RAM Address Register ( X and Y )
The X and Y registers are used to address any 4-bit item
in the RAM. A fetch operation moves the addressed
nibble onto the TOS. A store operation moves the TOS to
the addressed RAM location. By using either the
Condition Code Register ( CCR )
The carry/borrow flag indicates that borrow or carry out
of arithmetic logic unit ( ALU ) occurred during the last
arithmetic operation. During shift and rotate operations,
this bit is used as a fifth bit. Boolean operations have no
affect on the C flag.
Branch ( B )
The branch flag controls the conditional program branching. Should the branch flag have been set by a previous
instruction, a conditional branch will cause a jump. This
flag is affected by arithmetical, logical, shift, and rotate
operations.
Interrupt Enable ( I )
The interrupt-enable flag globally enables or disables the
triggering of all interrupt routines with the exception of
the non-maskable reset. After a reset, or on executing the
Rev. A2, 26-Feb-01
7 (61)
Preliminary Information
T48C510
DI instruction, the interrupt-enable flag is reset, thus disabling all interrupts. The core will not accept any further
interrupt requests until the interrupt-enable flag has been
set again either by executing an EI, RTI or SLEEP instruction.
11
0
PC
Program counter
0
7
0
RP
0
Return stack pointer
0
7
SP
Expression stack pointer
0
7
X
RAM address register (X)
7
0
Y
RAM address register (Y)
3
0
Top of stack register
TOS
3
CCR
C
0
–– B
I
Condition code register
Interrupt enable
Branch
Reserved
Carry / borrow
Figure 6. Programming model
8 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
1.2.4
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ALU
RAM
SP
TOS–1
TOS–2
TOS–3
TOS–4
TOS
ALU
CCR
94 8977
Figure 7. ALU zero-address operations
The 4-bit ALU performs all the arithmetical, logical, shift
and rotate operations with the top two elements of the expression stack (TOS and TOS-1) and returns the result to
the TOS. The ALU operations affect the carry/borrow and
branch flag in the condition code register (CCR).
1.2.5
Instruction Set
The MARC4 instruction set is optimized for the highlevel programming language qFORTH. Many MARC4
instructions are qFORTH words. This enables the compiler to generate a fast and compact program code. The
CPU has an instruction pipeline which allows the controller to prefetch an instruction from EEPROM at the same
time as the present instruction is being executed. The
MARC4 is a zero-address machine. The instructions contain only the operation to be performed and no source or
destination address fields. The operations are implicitly
performed on the data placed on the stack. There are one
and two byte instructions which are executed within 1 to
4 machine cycles. A MARC4 machine cycle is made up
of two system clock (SYSCL) cycles. Most of the instructions are only one byte long and are executed in a single
machine cycle.
1.2.6
I/O Bus
The I/O ports and the registers of the peripheral modules
(Timer 0, Timer 1, Interval timer, Watchdog etc.) are I/O
mapped. All communication between the core and the onchip peripherals takes place via the I/O bus and the
associated I/O control. With the MARC4 IN and OUT
instructions, the I/O bus enables a direct read or write
access to one of the 16 primary I/O addresses. More about
the I/O access to the on-chip peripherals is described in
the “Peripheral Modules”. The I/O bus is internal and is
not accessible by the customer on the final microcontroller device, but is used as the interface for the
MARC4 emulation.
1.3
Interrupt Structure
The MARC4 can handle interrupts with eight different
priority levels. They can be generated from the internal
and external interrupt sources or by a software interrupt
from the CPU itself. Each interrupt level has a hard-wired
priority and an associated vector for the service routine in
the EEPROM (see table 2, page 11). The programmer can
postpone the processing of interrupts by resetting the interrupt enable flag (I) in the CCR. An interrupt occurrence
will still be registered but the interrupt routine is only
started after the I flag is set. All interrupts can be masked,
and the priority individually software configured by programming the appropriate control register of the
interrupting module (see section “Peripheral Modules”).
Rev. A2, 26-Feb-01
9 (61)
Preliminary Information
T48C510
INT7
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁ ÁÁÁ
7
INT7 active
6
Priority level
RTI
INT5
5
INT5 active
RTI
INT3
4
ÁÁÁ
ÁÁÁ
3
INT3 active
2
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ÁÁÁÁÁ
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ÁÁÁÁ
INT2
RTI
INT2 pending
1
INT2 active
RTI
SWI0
0
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INT0 pending
INT0 active
RTI
Main /
Autosleep
Main /
Autosleep
Time
94 8978
Figure 8. Interrupt handling
Interrupt Processing
For processing the eight interrupt levels, the MARC4 includes an interrupt controller with two 8-bit wide
“interrupt pending” and “interrupt active” registers. The
interrupt controller samples all interrupt requests during
every non-I/O instruction cycle and latches these in the
interrupt pending register. Whenever an interrupt request
is detected, the CPU interrupts the program currently
being executed, on condition that no higher priority
interrupt is present in the interrupt active register. If the
interrupt-enable bit is set, the processor enters an interrupt acknowledge cycle. During this cycle a short call
(SCALL) instruction is executed to the service routine
and the current PC is saved on the return stack. An interrupt service routine is finished with the RTI instruction.
This instruction sets the interrupt-enable flag, resets the
corresponding bits in the interrupt pending/active register
and fetches the return address from the return stack to the
program counter. When the interrupt-enable flag is reset
(triggering of interrupt routines is disabled), the
execution of new interrupt service routines is inhibited,
but not the logging of the interrupt requests in the interrupt pending register. The execution of the interrupt is
then delayed until the interrupt-enable flag is set again.
Note that interrupts are only lost if an interrupt request occurs while the corresponding bit in the pending register is
still set (i.e., the interrupt service routine is not yet finished).
After a master reset (power-on, external or watchdog reset), the interrupt-enable flag and the interrupt pending
and interrupt active registers are all reset.
Interrupt Latency
The interrupt latency is the time from the occurrence of
the interrupt to the interrupt service routine being activated. In the MARC4, this is extremely short and takes
between 3 to 5 machine cycles depending on the state of
the core.
10 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
Table 2 Interrupt priority table
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Interrupt
Priority
EEPROM Address
Maskable
INT0
lowest
040h
Yes
C8h (SCALL 040h)
INT1
|
080h
Yes
D0h (SCALL 080h)
INT2
|
0C0h
Yes
D8h (SCALL 0C0h)
INT3
|
100h
Yes
E8h (SCALL 100h)
INT4
|
140h
Yes
E8h (SCALL 140h)
INT5
|
180h
Yes
F0h (SCALL 180h)
INT6
↓
1C0h
Yes
F8h (SCALL 1C0h)
INT7
highest
1E0h
Yes
FCh (SCALL 1E0h)
1.3.1
Interrupt Opcode
Hardware Interrupts
Table 3 Hardware interrupts
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Interrupt
Source
Possible Interrupt Priorities
0
1
2
3
4
5
6
RST
7
Interrupt Mask
Register
Bit
Function
NRST external
X
–
–
low level active
Watchdog
#
–
–
1/2 – 2 sec. time out
Port A coded reset
#
–
–
level any inputs
3
any edge, any input
any edge, any input
Port A monitor
*
*
*
*
PAIPR
Port B monitor
*
*
*
*
PBIPR
3
Port 60 external
*
*
*
*
P6CR
1,0
any edge
P6CR
3,2
any edge
ITIPR
0
1 of 8 frequencies
(1 – 128 Hz)
ITIPR
1
1 of 8 frequencies
(8 – 8192 Hz)
T0CR
0
overflow/compare/
end measurement
T1CR
0
compare
Port 61 external
*
Interval timer INTA
*
*
*
Interval timer INTB
*
*
Timer 0
*
*
Timer 1
*
*
*
*
*
*
*
*
X = hardwired (neither optional or software configurable)
# = configurable option (see “Hardware Options”)
* = software configurable (see “Peripheral Modules” section for further details)
In the T48C510, there are eleven hardware interrupt
sources which can be programmed to occupy a variety of
priority levels. With the exception of the reset sources
(RST), each source can be individually masked by mask
bits in the corresponding control registers. An overview
of the possible hardware configurations is shown in
table 3.
1.3.2
The software triggered interrupt operates in exactly the
same way as any hardware triggered interrupt.
The SWI instruction takes the top two elements from the
expression stack and writes the corresponding bits via the
I/O bus to the interrupt pending register. Thus, by using
the SWI instruction, interrupts can be re-prioritized or
lower priority processes scheduled for later execution.
Software Interrupts
The program can generate interrupts using the software
interrupt instruction (SWI) which is supported in
qFORTH by predefined macros named SWI0...SWI7.
Rev. A2, 26-Feb-01
11 (61)
Preliminary Information
T48C510
1.4
activate an external reset, the pin should be low for a
minimum of 4 s.
Hardware Reset
The master reset forces the CPU into a well-defined
condition, is unmaskable and is activated independent of
the current program state. It can be triggered by either
initial supply power-up, a short collapse of the power supply, a watchdog time out, activation of the NRST input or
the occurrence of a coded reset on Port A (see figure 9).
A master reset activation will reset the interrupt enable
flag, the interrupt pending registers, the interrupt active
registers and initialize all on-chip peripherals. In this state
all ports take on a high resistance input status with deactivated pullup and pulldown transistors (see figure 10).
When the reset condition disappears, the hardware
configuration
previously
programmed
in
the
configuration EEPROM (see MTP Programming section)
is loaded into the peripherals so that all port
characteristics and pullup/ downs reflect the programmed
configuration. This configuration period is immediately
followed by a further reset delay time (approx. 80 ms),
after which a short call instruction (opcode C1h) to the
EEPROM address 008h is performed. This activates the
initialization routine $RESET which in turn initializes all
necessary RAM variables, stack pointers and internal
peripheral configuration registers.
Power-on Reset
The fully integrated power-on reset circuit ensures that
the core is held in a reset state until the minimum operating supply voltage has been reached. A reset condition is
also generated should the supply voltage drop
momentarily below the minimum operating supply.
External Reset (NRST)
An external reset can be triggered with the NRST pin. To
Coded Reset (Port A)
The coded reset circuit is connected directly to the Port A
terminals. By using the appropriate configuration, the
user can define a hardwired code combination (e.g., all
pins low) which, if occurring on the Port A, will generate
a reset in the same way as the NRST pin.
Table 4 Multiple key reset options
NO_RST
Not used (default)
RST2
BPA0 & BPA1 = low
RST3
BPA0 & BPA1 & BPA2 = low
RST4
BPA0 & BPA1 & BPA2 & BPA3 = low
RST5
BPA0 & BPA1 = high
RST6
BPA0 & BPA1 & BPA2 = high
RST7
BPA0 & BPA1 & BPA2 & BPA3 = high
Note, that if this option is used, the reset is not maskable
and will also trigger if the predefined code is written on
to the Port A by the CPU itself. Care should also be taken
not to generate an unwanted reset by inadvertently passing through the reset code on input transitions. This
applies especially if the pins have a high capacitive load.
Watchdog Reset
The watchdog’s function can be enabled via a configuration option and triggers a reset with every watchdog
counter overflow. To suppress the watchdog reset, the
counter must be regularly reset by reading the watchdog
timer register address (CWD).
The CPU reacts in exactly the same manner as a reset
stimulus from any of the above sources.
VDD
* = Configuration
Pull-up
NRST
Reset delay
timer
Power-on
reset
reset code
CODE *
time out
Port A
CPU reset
VSS
V DD
Watchdog *
rst
Port A
I/O
WD reset
CPU
Figure 9. Reset configuration/ start-up sequence
12 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
NRST
Device
status
Reset
Configuration period
Power-on reset delay
250 sec
Port
status
Pullup/
pulldown
configuration
Program defined
Input mode
Old config.
No pullup/ -down
Input mode
No pullup/ pulldown
Application program
execution
80 msec
Input mode
New configuration
Program defined
New configuration
16539
Figure 10. Normal mode start-up
1.5
1.5.1
Clock Generation
Clock Module
The clock module generates two clocks. The system
clock (SYSCL) supplies the CPU and the peripherals
while the lower frequency periphery sub-clock (SUBCL)
supplies only the peripherals. The modes for clock
sources are programmable with the OS1-bit and OS0-bit
in the SC-register and the CCS-bit in the CM-register.
The clock module includes 4 different internal oscillator
types: two RC-oscillators, one 4-MHz crystal oscillator
and one 32-kHz crystal oscillator. The pins OSC1 and
OSC2 provide the interface to connect a crystal either for
the 4-MHz, or the 32-kHz crystal oscillator. SCLIN can
be used as an input for an external clock or for connecting
an external trimming resistor for the RC-oscillator 2. All
necessary components with the exception of the crystal
and the trimming resistor are integrated on-chip. Any one
of these clock sources can be selected to generate the
system clock (SYSCL).
In applications that do not require exact timing, it is
possible to use the fully integrated RC-oscillator 1
without any external components. The RC-oscillator 2 is
more stable but the oscillator frequency must be trimmed
with an external resistor attached between SCLIN and
VDD. In this configuration, for system clock frequencies
below 2 MHz, the RC-oscillator 2 frequency can be
maintained to within a tolerance of ± 10% over the full
operating temperature and voltage range.
The clock module is programmable via software using the
clock management register (CM) and the system
configuration register (SC). The required oscillator
configuration is selected with the OS[1:0]-bits in the
SC-register. A programmable 4-bit divider stage allows
the adjustment of the system clock speed. A
synchronization stage avoids any clock glitches which
could be caused by clock source switching.
The CPU always requires SYSCL clocks to execute
instructions, process interrupts and enter or leave the
SLEEP state. Internal oscillators are, depending on the
condition of the NSTOP-bit automatically stopped and
started where necessary. Special care must however be
taken when using an external clock source which is gated
by a one of the microcontroller port signals. This configuration can hang up if the external oscillator is switched off
while the external clock source is still selected. It is therefore advisable in such a case to switch first to the internal
RC-oscillator 1 source using CSS-bit. The external source
can then be reselected later when the external oscillator
has again been restarted.
Rev. A2, 26-Feb-01
13 (61)
Preliminary Information
T48C510
SCLIN
SYSCLmax
SYSCL
ExOut
Stop
ExIn
RCOut1
Stop Control
RC oscillator2
OSCIN
SC:
RC[1:0]
RC
oscillator 1
Ext. clock
RCOut2
Stop
RTrim
IN1
/2
/2
/2
IN2
4–MHz oscillator
Oscin
Oscout
/2
to CPU
and
Timer/
counter
Divider chain
4Out
Stop
/8
32–kHz oscillator
Oscin
Oscout
OSCOUT
32Out
Sleep
SYSCLmax/64
Stop
SUBCL
CM: NSTOP
CCS
CSS1
CSS0
32 kHz
SC:
OS1
OS0
Figure 11. Clock module
Table 5 Clock modes
Mode
Clock Source for SYSCL
Clock Source for SUBCL
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OS1
OS0
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1
1
RC-oscillator 1 (intern)
2
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1
3
1
4
0
1.5.2
CCS = 1
CCS = 0
CCS = 1
CCS = 0
External input clock
SYSCL max/64
SCLIN / 128
RC-oscillator 1 (intern)
RC-oscillator 2 with
external trimming resistor
SYSCL max/64
SYSCL max/64
0
RC-oscillator 1 (intern)
4-MHz oscillator
SYSCL max/64
fxtal / 128
0
RC-oscillator 1 (intern)
32-kHz oscillator
Oscillator Circuits and External
Clock Input Stage
RC-Oscillator 1 Fully Integrated
For timing insensitive applications, it is possible to use
the fully integrated RC oscillator 1. This operates without
any external components and thus saves on component
costs. The RC-oscillator 1 frequency tolerance is better
than ±50% over the full temperature and voltage range.
A reduction in the application operating supply voltage
and temperature ranges will result in an improved frequency tolerance. For more detailed information see
figures 55 – 57. The basic center frequency of the RC-oscillator 1 is programmable with the RC1 and the RC0-bits
in the SC register.
Control
RC1
Stop
External Input Clock
The SCLIN pin can be driven by an external clock source
provided it meets the specified input levels, duty cycle,
rise and fall times. The maximum system clock frequency
fSYSCLmax that the core can operate is fSCLIN/2 (see
figure 13).
Ext. input clock
Ext.
Clock
SCLIN
ExOut
ExOut
ExIn
Osc–Stop
Stop
Figure 13. External input clock
RC-Oscillator 2 with External Trimming
Resistor
RC
oscillator 1
RcOut1
RcOut1
RC0
32 kHz
Osc–Stop
Figure 12. RC-oscillator 1
The RC-oscillator 2 is a high stability oscillator whereby
the oscillator frequency can be trimmed with an external
resistor connected between SCLIN and VDD. In this
configuration, as long as the system clock frequency does
not exceed 2 MHz, the RC-oscillator 2 frequency can be
14 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
maintained stable to within a tolerance of ± 10% over the
full operating temperature and voltage range.
32-kHz Oscillator
For example: A SYSCLmax frequency of 2 MHz, can be
obtained by connecting a resistor Rext = 150 k (see
figures 14, 52, 53 and 54).
Some applications require accurate long-term time
keeping without putting excessive demands on the CPU
or alternatively low resolution computing power. In this
case, the on-chip ultra low power 32-kHz crystal
oscillator can be used to generate both the SUBCL and/or
the SYSCL. In this mode, power consumption can be significantly reduced. The 32-kHz crystal oscillator will
remain operating (not stopped) during any CPU powerdown/SLEEP mode.
VDD
RC
oscillator 2
Rext
RcOut2
RcOut2
SCLIN
RTrim
Stop
Osc–Stop
OSCIN
Oscin
13377
XTAL
32 kHz
Figure 14. RC-oscillator 2
4-MHz Oscillator
XTAL
OSCIN
Cer.
Res
32Out
Oscout
The integrated system clock oscillator requires an external crystal or ceramic resonator connected between the
OSCIN and OSCOUT pins to establish oscillation. All the
necessary oscillator circuitry, with the exception of the
actual crystal, resonator and the optional C3 and C4 are
integrated on-chip.
C3
32Out
32–kHz
oscillator
Oscin
4Out
4–MHz
oscillator
Oscout
Stop
C4 OSCOUT
Figure 15. System clock oscillator
4Out
Osc–Stop
OSCOUT
Figure 16. 32-kHz crystal oscillator
Quartz Oscillator Configuration
If the customer’s application necessitates the use of a
quartz crystal clock source and this requires capacitive
trimming, the trimming capacitors are not integrated into
the MTP unlike the M44C510E and should therefore be
connected externally as descrete components between the
respective Quartz Crystal terminals (OSCIN, OSCOUT)
and VSS.
Rev. A2, 26-Feb-01
15 (61)
Preliminary Information
T48C510
1.5.3
Clock Management Register (CM)
The clock management register (CM) controls the system clock divider chain, as well as the peripheral clock in the
power-down modes.
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Auxiliary register address: ’E’hex
Bit 3
NSTOP
CM:
NSTOP
Bit 2
CCS
Bit 1
CSS1
Bit 0
CSS0
Reset value: 1111b
CCS
Not STOP peripheral clock
NSTOP = 0, stops the peripheral clock (SUBCL) when the core is in SLEEP mode.
The 32-kHz crystal oscillator SUBCL clock cannot be stopped.
NSTOP = 1, enables the peripheral clock (SUBCL) when the core in SLEEP mode
Core Clock Select
CCS = 1, the internal RC-oscillator 1 generates SYSCL
CCS = 0, the 4-MHz crystal oscillator, the 32-kHz crystal oscillator, an external clock source or the
RC-oscillator 2 (with the external resistor) will generate SYSCL dependent on the setting of
OS0 and OS1 in the system configuration register
CSS[1:0]
Core Speed Select
These two bits control the system clock divider chain
Auxiliary register address: ’E’hex
CSS1
0
0
1
1
CSS0
0
1
0
1
Divider
16
8
4
2
Note
SYSCLmax/8
SYSCLmax/4
SYSCLmax/2
Reset value = SYSCLmax
System Configuration Register (SC)
Primary register address: ’E’hex
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SC: write
Bit 3
Bit 2
Bit 1
Bit 0
RC1
RC0
OS1
OS0
Reset value: 1111b
RC1, RC0 Internal RC oscillator 1 frequency select (SYSCLmax)
RC1
0
0
1
1
RC0
0
1
0
1
SYSCLmax @ 25°C, VDD = 5 V
Note
7.0 MHz (fiRC0)
3.0 MHz (fiRC1)
2.0 MHz (fiRC2)
0.8 MHz (fiRC3)
Reset value
OS1, OS0 Oscillator selection bits (in conjunction with the CCS-bit)
CCS
0
0
0
0
1
OS1
1
0
1
0
x
OS0
1
1
0
0
x
SUBCL
SYSCLmax/64
32 kHz
SYSCLmax/64 or 32 kHz
System Oscillator Selection
External input clock at SCLIN
RC-oscillator 2 with Rext
4-MHz crystal oscillator
32-kHz crystal oscillator
RC-oscillator 1
If CCS = 0 in the CM-register, the RC-oscillator 1 is stopped.
16 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
1.5.4
Power-down Modes
The T48C510 encorporates several modes which enable
the power consumption to be tailored to a minimum without sacrificing computational power. When the controller
exits the lowest priority interrupt task, it reverts to a
SLEEP state. This is a CPU shutdown condition which is
used to reduce average system power consumption where
the CPU itself is only partially utilized. In SLEEP, the
CPU clocking system is deactivated whereby the peripherals and associated clock sources may remain active
(Standby Mode) or they can also be halted (Halt Mode).
In Standby Mode, the peripherals are able to continue operation and if required also generate interrupts which can,
along with a reset reactivate the CPU to bring it out of the
sleep state.
SLEEP can only be maintained when none of the interrupt
pending or active register bits are set. The application of
the $AUTOSLEEP routine ensures the correct function of
the sleep mode.
In both Standby and Active modes the current consumption is largely dependent on the frequency of the CPU
system clock (SYSCL) and the supply voltage (VDD).
(see figures 50 and 51) while the Halt Mode current is
merely controller static leakage current.
Selection of Standby or Halt mode is performed by the
NSTOP bit in the clock managent register (CM). It should
be noted that the low power 32-kHz crystal oscillator, if
enabled will always remain active in both Standby and
Halt modes.
Table 6 Power-down modes
Mode
CPU Core
State
NSTOP
RC-Oscillator 1
RC-Oscillator 2
4-MHz Oscillator
32-kHz Oscillator
Active
RUN
Standby
Halt
External Input
Clock at SCLIN
1
RUN
RUN
Enabled
SLEEP
1
RUN
RUN
Enabled
SLEEP
0
STOP
RUN
Disabled
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1.5.5
Clock Monitor Mode
NRST
TE
SYSCL clocks
BP11
SUBCL clocks
BP10
13387
Oscillator supervisory mode
Normal operation
Figure 17. Clock monitoring
For trimming purposes, the T48C510 can be put into a
clock monitor mode. By forcing the test input (TE) high,
the SYSCL clock will appear on BP11 (Port 1, bit 1) and
SUBCL clock on Port BP10 (Port 1, bit 0). On releasing
the TE pin, the BP10 and BP11 will resume their normal
function (see figure 17).
Rev. A2, 26-Feb-01
17 (61)
Preliminary Information
T48C510
2
Peripheral Modules
2.1
Addressing Peripherals
Accessing the peripheral modules takes place via the I/O
bus (see figure 18). The IN or OUT instructions allow
direct addressing of up to 16 I/O modules. A dual register
addressing scheme has been adopted which addresses the
“primary register” directly. To address the “auxiliary register”, the access must be switched with an “auxiliary
switching module”. Thus, a single IN (or OUT) to the
module address will read (or write) into the module primary register. Accessing the auxiliary register is
performed with the same instruction preceded by writing
the module address into the auxiliary switching module.
Byte-wide registers are accessed by multiple IN (or OUT)
instructions. Extended addressing is used for more complex peripheral modules, with a larger number of
registers. In this case, a bank of up to 16 subport registers
are indirectly addressed with the subport address being
initially written into the auxiliary register. Please refer to
the ’HARDC510.SCR’ hardware interface file as a programming guideline.
18 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
Module ASW
Module M1
Module M2
Module M3
(Address Pointer)
Aux. Reg.
Aux. Reg.
Bank of
Primary Regs.
Subport Fh
2
6
Subport Eh
Auxiliary Switch
Module
Subport 1
Primary Reg.
Primary Reg.
Primary Reg.
Subport 0
3
4
7
1
5
I/O bus
to other modules
Indirect Subport
Access
Dual Register
Access
(Subport Register Write)
Addr.(M1)
2
Addr.(SPort) Addr.(M1)
OUT
3
SPort_Data
OUT
Addr.(ASW) OUT
(Subport Register Read)
Example of
qFORTH
Program
Code
1
Addr.(M1)
2
Addr.(SPort) Addr.(M1)
3
Addr.(M 1)
(Prima ry Register Write)
(Primary Register Write)
1
Addr.(M1)
Single Register
Access
4
Prim._Data
5
Address(M2) Address(ASW) OUT
6
Aux._Data
Address(M2) OU T
Prim._Data Address(M3) O UT
( Auxiliary Register Write )
Address(M2) OUT
Addr.(ASW) OUT
OUT
IN
7
(Prima ry Register Read)
7
Address(M3) IN
(Primary Register Rea d)
4
Address(M 2)
IN
(Subport Register Write Byte)
(Auxiliary Register Rea d)
1
Addr.(M1)
2
Addr.(SPort) Addr.(M1)
3
SPort_Data(lo) Addr.(M1) OUT
3
SPort_Data(hi) Addr.(M1) OUT
Addr.(ASW) OUT
OUT
(Subport Register Rea d Byte)
1
Addr.(M1)
Addr.(ASW) OUT
5
6
Address(M2) Address(ASW) OUT
Address(M 2) IN
(Auxiliary Register Write Byte)
5
Address(M2) Address(ASW) OUT
6
Aux._Data(lo) Address(M2) OUT
6
Aux._Data(hi) Address(M2) OUT
2
Addr.(SPort) Addr.(M1)
3
Addr.(M 1)
IN
Addr.(ASW) = Auxiliary Switch Module Address
3
Addr.(M 1)
IN
Addr.(Mx) = Module Mx Addr ess
OUT
Addr.(SPort) = Subport Address
(Auxiliary Register Rea d)
1
2
Address(M1) Address(ASW) OUT
Address(M1) IN
Prim._D ata = da ta to be written into Primary Register.
Aux._D ata = data to be written into Auxilia ry Register
Aux._Data (lo)= data to be written into Auxilia ry Register (low nibble)
Aux._Data (hi) = da ta to be written into Auxiliary Register(high nibble)
SPort_Data(lo) = data to be written into SubP ort (low nibble)
SPort_Data(hi) = data to be written into Subport (high nibble)
96 11522
Figure 18. Example of I/O addressing
Rev. A2, 26-Feb-01
19 (61)
Preliminary Information
T48C510
Table 7 T48C510 Peripheral addresses
Port Address
Name
Write
/Read
P0DAT
W/R
P1DAT
W/R
PAIPR
W
Aux. PAICR
W
CWD
R
PBIPR
W
Aux. PBICR
W
P4DAT
W/R
Aux. P4DDR
W
P5DAT
W/R
Aux. P5DDR
W
P6DAT
W/R
Aux P6CR
W
P7DAT
W/R
Aux. P7DDR
W
ASW
W
TCM
W/R
Aux. T0SR
R
TCSUB
W
Subport address
0 T0MO
W
1 T0CR
W
2 T1MO
W
3 T1CR
W
4 TCMO
W
5 TCIOR
W
6 TCCR
W
7 TCIP
W
8 T1CP
W
T1CA
R
9 T0CP
W
T0CA
R
A BZCR
W
B-F
PADAT
W/R
Aux. PADDR
W
PBDAT
W/R
Aux. PBDDR
W
PCDAT
W/R
Aux. PCDDR
W
–––
–––
SC
W
Aux. CM
W/R
ITFSR
W
Aux. ITIPR
W
Reset Value
Register Function
Module
Type
M3
M3
M2
See
Page
21
21
22
22
29
22
22
20
21
20
21
25
25
20
21
18
18
35
30/31
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0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
1111b
1111b
1111b
1111b
––––
1111b
1111b
1111b
1111b
1111b
1111b
0011b
1111 1111b
1111b
1111b
1111b
1111b
0000b
1111b
Port 0 – data register/input data
Port 1 – data register/input data
Port A – interrupt priority register
Port A – interrupt control register
Watchdog timer reset
Port B – interrupt priority register
Port B – interrupt control register
Port 4 – data register/pin data
Port 4 – data direction register
Port 5 – data register/pin data
Port 5 – data direction register
Port 6 – data register/pin data
Port 6 – control register (byte)
Port 7 – data register/pin data
Port 7 – data direction register
Auxiliary switch register
1111b
1111b
1111b
1111b
1111b
1111b
1111b
1111b
xxxx xxxxb
xxxx xxxxb
xxxx xxxxb
xxxx xxxxb
1111b
––––
1111b
1111b
1111b
1111b
1111b
1111b
––––
1111b
1111b
1111b
1111b
Timer 0 mode register
Timer 0 control register
Timer 1 mode register
Timer 1 control register
Timer/counter mode register
Timer/counter I/O control register
Timer/counter control register
Timer/counter interrupt priority
Timer 1 compare register (byte)
Timer 1 capture register (byte)
Timer 0 compare register (byte)
Timer 0 capture register (byte)
Buzzer control register
Reserved
Port A – data register/pin data
Port A – data direction register
Port B – data register/pin data
Port B – data direction register
Port C – data register/pin data
Port C – data direction register
Reserved
System configuration register
Clock management register
Interval timer frequency select register
Interval timer interrupt priority register
Data to/from subport addressed by TCSUB
Timer 0 interrupt status register
Timer/counter subport address pointer
20 (61)
M3
M2
M2
M2
M2
M2
ASW
M1
M1
M1
M1
M1
M1
M1
M1
M1
M1
M1
M1
M1
M1
M1
M1
35
36
43
43/44
33
32
31
32
44
M2
20
21
20
21
20
21
M2
M2
M2
M2
37
47
16
15
28
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
2.2
Bidirectional Ports
Table 8 Overview of Port Features
0
1
4
5
6
7
A
B
C
Number of bits
Port Address
4
4
4
4
2
4
4
4
4
Bitwise programmable
direction
no
no
yes
yes
yes
yes
yes
yes
yes
Output drivers
configurable 1)
no 2)
yes
yes
yes
yes
yes
yes
yes
yes
Dynamic pullup/ down
typ. (Ohm) 3)
500k
500k
500k
500k
500k
500k
500k
500k
500k
Static pullup/ down
typ. (Ohm) 4)
none
none
30k
30k
4k
30k
30k
30k
30k
yes
yes
yes
no
yes
no
yes
yes
no
Port
monitor/
coded
reset
Port
monitor
Schmitt trigger inputs
Timer 0
Additional functions
1)
2)
3)
4)
External
interrupt
Either ”open drain down”, ”open drain up” or CMOS output configuration.
This output must always be CMOS.
The Dynamic pullup/down transistors are configurable and if selected, are only activated when the associated complementry driver transistor
is off. ie. A dynamic pull up transistor is only active when the port is either in input mode (both drivers off) or when a logical 1 is written to
the port pad (low driver off) in output mode. (figure 20)
The Static Pullup/down transitors are configurable and if selected, are always active independant of the port direction or driven state.
(figure 20)
For further data see section 3.2 .
All Ports (0, 1, 4, 5, 7, A, B and C with the exception of
Port 6) are 4 bits wide. Port 6 has a data width of 2 bits (bit
0 and bit 1) only. The ports may be used for data input or
output. All ports that can either directly or indirectly generate an interrupt are equipped with Schmitt-trigger
inputs. A variety configurable options are available such
as open drain, open source and full complementary outputs as well as different types of pull-up and pull-down
transistors. All Port Data Registers (PxDAT) are I/O
mapped to the primary address register of the respective
port address, and the Port Data Direction Register
(PxDDR) to the corresponding auxiliary register.
All bidirectional ports except Port 0 and Port 1, include
a bitwise- programmable Data Direction Register
(PxDDR) which allows the individual programming of
each port bit as input or output. It is also possible to read
the pin condition when in output mode. This is a useful
feature for self testing and for collision detection on
wired-OR bus systems.
There are five different types of bidirectional ports:
Ports 0 and 1 – 4-bit wide, bidirectional ports with automatic full bus width direction switching.
Port 4 – 4-bit wide, bitwise programmable bidirectional port also provides the I/O interface to Timer 0
and the Buzzer.
Ports 5, 7 and C – 4-bit wide, bitwise programmable
high drive I/O port.
Port 6 – 2-bit wide, bitwise programmable bidirectional ports with optional static (4 k) pull-up/-down
and programmable interrupt logic.
Ports A and B – 4-bit wide, bitwise programmable
bidirectional ports with optional port monitor function.
Port Data Register (PxDAT)
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
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ÁÁÁÁ
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ÁÁÁÁ
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Primary register address: ’Port address’hex
PxDAT
Bit 3
Bit 2
Bit 1
Bit 0
PxDAT3
PxDAT2
PxDAT1
PxDAT0
Reset value: 1111b
Bit 3 → MSB, bit 0 → LSB, x → Port address
Rev. A2, 26-Feb-01
21 (61)
Preliminary Information
T48C510
Port Data Direction Register (PxDDR)
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ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Auxiliary register address: ’Port address’hex
PxDDR
Bit 3
Bit 2
Bit 1
Bit 0
PxDDR3
PxDDR2
PxDDR1
PxDDR0
Reset value: 1111b
Table 9 Port Data Direction Register (PxDDR)
Code: 3 2 1 0
Function
xxx1
BPx0 in input mode
xxx0
BPx0 in output mode
xx1x
BPx1 in input mode
xx0x
BPx1 in output mode
x1xx
BPx2 in input mode
x0xx
BPx2 in output mode
1xxx
BPx3 in input mode
0xxx
BPx3 in output mode
2.2.1
Bidirectional Port 0 and Port 1
In this port type, the data direction register is not independently software programmable because the direction of
the complete port is switched automatically when an I/O
instruction occurs (see figure 19). The port can be
switched to output mode with an OUT instruction and to
input with an IN instruction. The data written to a port will
be stored in the output data latches and appears immediately at the port pin following the OUT instruction. After
RESET, all output latches are set to ’1’ and the ports are
switched to input mode. An IN instruction reads the
condition of the associated pins.
Note: Care must be taken when switching these bidirectional ports from output to input. The capacitive pin
loading at this port, in conjunction with the high resistance pull-ups, may cause the CPU to read the contents of
the output data register rather than the external input state.
This can be avoided by using either of the following programming techniques:
Use two IN instructions and DROP the first data
nibble. The first IN switches the port from output to
input and the DROP removes the first invalid nibble.
The second IN reads the valid pin state.
Use an OUT instruction followed by an IN instruction.
With the OUT instruction, the capacitive load is
charged or discharged depending on the optional
pull-up /pull-down configuration. Write a “1” for pins
with pull-up resistors, and a “0” for pins with pulldown resistors.
VDD
I/O Bus
*
VDD
(Data out)
D
*
Q
BPxy
PxDATy
R
*
Reset
(Direction)
OUT
IN
Master reset
Pull-up
S
Q
R
NQ
*
*) Configurable option
Port 1 only
Pull-down
Figure 19. Bidirectional Ports 0 and 1
22 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
2.2.2
Bidirectional Port 5, Port 7 and Port C
All bidirectional ports except Port 0 and Port 1, include
a bitwise-programmable Data Direction Register
(PxDDR) which allows the individual programming of
each port bit as input or output. It also enables the reading
of the pin condition in output mode.
The bidirectional Ports 5, 7 and C as well as Port A and
Port B are equipped with the same standard I/O logic.
However, Port 5, Port 7 and Port C include standard
CMOS input stages, whereas Port A, Port B and all other
digital signal pins have Schmitt-trigger inputs. Port 5 and
Port 7 have high current output drive capability for up to
20 mA @ 5 V. Whereby the instantaneous sum of the output currents should not exceed 100 mA.
Port A and Port B with Schmitt-trigger
V
DD
Static
Pull-up
* 30 k @ 5 V
I/O Bus
Pull-up
*
(Data out)
*
I/O Bus
D
Q
PxDATy
S
BPxy
*
Master reset
I/O Bus
V
DD
Static
* Pull-down
*
D S Q
PxDDRy
Pull-down
* Configurable option
(Direction)
Figure 20. Bidirectional Ports 5, 7, A, B and C
2.2.3
Bidirectional Port A and Port B with Port Monitor Function
PRx1 PRx2
Connected to Ports A and B (x = A or B)
PxICR ENx3
ENx2
ENx1
ENx0
IMAx
ITRx
PRx1
BPx3
PRx2
PxIPR
0
0
1
1
0
1
0
1
INT7
INT5
INT3
INT1
Decoder
2:4
BPx2
INT7
INT5
INT3
INT1
BPx1
BPx0
16507
Figure 21. Port monitor module of Port A and Port B
In addition to the standard I/O functions described in section 2.2.2, both Port A (BPA3 – BPA0) and Port B (BPB3
– BPB0) are equipped with Schmitt-trigger inputs and a
port monitor module. This module is connected across all
four port pins (see figure 21) and is intended for monitoring those pins selected by control bits Enx3 – Enx0 and
generating an interrupt when the first pin leaves a preselected logical default idle state. This state is defined by
control bit ITRx . Transitions on other pins will only cause
an interrupt if the other pins have first returned to the idle
state. This, for example is useful for interrupt initiated
port scanning without the power consuming task of continuously polling for port activity.
Using the Port Interrupt Control Register (PxICR), pins
can be individually selected. A non-selected pin cannot
generate an interrupt. The Port Interrupt Priority Register
(PxIPR) allows masking of each interrupt, definition of
Rev. A2, 26-Feb-01
23 (61)
Preliminary Information
T48C510
the interrupt edge and programming of the interrupt
priority levels. When programming or reprogramming either of the port monitor control registers, any previously
generated interrupt on that port which has not yet been acknowledged by the CPU or an interrupt generated by the
reprogramming itself is automatically cleared. Port A can
also be used for a configurable coded reset. For more information see section 1.4 ’Hardware Reset’.
Port Monitor Interrupt Priority Register (PxIPR)
The Port Interrupt Priority Registers PAIPR and PBIPR
are I/O mapped to the the primary address registers of the
Port Monitor Module addresses ’2’h and ’3’h respectively. The Port Interrupt Control Registers PAICR and
PBICR are mapped to the corresponding auxiliary
registers.
x = ’A’ (Port A) or ’B’ (Port B)
(Port A) Primary register address: ’2’hex
(Port B) Primary register address: ’3’hex
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
PxIPR
IMx
ITRx
PRx2..1
Bit 3
Bit 2
Bit 1
Bit 0
IMx
ITRx
PRx2
PRx1
Reset value: 1111b
– Interrupt Mask
– Interrupt Transition
– Interrupt Priority code
Table 10 Port Monitor Interrupt Priority Register (PxIPR)
Code
3210
Function
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁ
ÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
xx00
Port monitor interrupt priority 7
xx01
Port monitor interrupt priority 5
xx10
Port monitor interrupt priority 3
xx11
Port monitor interrupt priority 1
x0xx
Port monitor interrupt on falling edge
x1xx
Port monitor interrupt on rising edge
0xxx
Port monitor interrupt enabled
1xxx
Port monitor interrupt disabled
Port Monitor Interrupt Control Register (PxICR)
x = ’A’ (Port A) or ’B’ (Port B)
PxICR
Bit 3
ENx3
(Port A) Auxiliary register address: ’2’hex
(Port B) Auxiliary register address: ’3’hex
Bit 2
ENx2
Bit 1
ENx1
Bit 0
ENx0
Reset value: 1111b
ENx3 ... 0 port monitor input ENable code
Table 11 Port Monitor Interrupt Control Register (PxICR)
Code
3210
xxx0
xxx1
xx0x
xx1x
x0xx
x1xx
0xxx
1xxx
Function
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Bit 0 can generate an interrupt
Bit 0 cannot generate an interrupt
Bit 1 can generate an interrupt
Bit 1 cannot generate an interrupt
Bit 2 can generate an interrupt
Bit 2 cannot generate an interrupt
Bit 3 can generate an interrupt
Bit 3 cannot generate an interrupt
24 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
2.2.4
Bidirectional Port 6
V
I/O Bus
V
DD
Pull-up
*
DD
Strong
Static
Pull-up
* 4k @ 5 V
VDD
(Data out)
*
I/O Bus
Q
D
P6DATy
BP6y
S
*
V
Master reset
y = 0 or 1
DD
*
IN enable
* Configurable
*
Strong
Static
Pull-down
4k @ 5 V
Pull-down
Figure 22. Bidirectional Port 6
This 2-bit bidirectional port can be used as bitwise-programmable I/O. The data is LSB aligned so that the two
MSB’s will not appear on the port pins when written. The
port pins can also be used as external interrupt inputs (see
figures 22 and 23). Both interrupts can be masked or independently configured to trigger on either edge. The
interrupt priority levels are also configurable. The
interrupt configuration and port direction is controlled by
the Port 6 Control Register (P6CR). An additional low
resistance pull-up transistor (configurable option) provides an internal bus pull-up for serial bus applications.
In output mode (PxDDR bit = 0), the respective Port Data
Register (PxDAT) bit appears on the port pin, driven by
an output port driver stage which can be configurable as
open drain, or full complementary CMOS. With an IN
instruction the actual pin state can be read back into the
controller at any time without changing the port directional mode. If the output port is configured as an open
drain driver, the controller is able to receive the external
data on this pin without switching into input mode as long
as the output transistor is switched off.
In input mode (PxDDR bit = 1), the output driver stage is
deactivated, so that an IN instruction will directly read the
pin state which can be driven from an external source. In
this case, the state of the Port Data Register (PxDAT),
although not appearing at the pin itself, remains
unchanged. High resistance configurable pull-up or pulldown transistors are automatically switched onto the port
pin in input mode. The Port Data Register is written to the
respective port address with an OUT instruction.
The Port 6 Data Register (P6DAT) is I/O mapped to the
primary address register of address ’6’hex and the Port 6
Control Register (P6CR) to the corresponding auxiliary
register. The P6CR is a byte wide register and is written
by writing the low nibble first and then the high nibble
(see section 2.1 “Addressing peripherals”).
Rev. A2, 26-Feb-01
25 (61)
Preliminary Information
T48C510
Port 6 Data Register (P6DAT)
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Primary register address: ’6’hex
P6DAT
Bit 3
Bit 2
Bit 1
Bit 0
not used
not used
P6DAT1
P6DAT0
Reset value: xx11b
The unused bits 2 and 3 are ’0’, if read.
Port 6 Control Register (P6CR)
ÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
Auxiliary register address: ’6’hex
P6CR
First write cycle
Second write cycle
Bit 3
Bit 2
Bit 1
Bit 0
P61IM2
P61IM1
P60IM2
P60IM1
Bit 7
Bit 6
Bit 5
Bit 4
P61PR2
P61PR1
P60PR2
P60PR1
Reset value: 1111b
Reset value: 1111b
P6xIM2, P6xIM1 – Port 6x Interrupt mode/direction code
P6xPR2, P6xPR1 – BP6x Interrupt priority code
Table 12 Port 6 control register (P6CR)
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
Auxiliary Address: ’6’hex
First Write Cycle
Second Write Cycle
Code
3210
xx11
Function
Code
3210
Function
BP60 in input mode – interrupt disabled
xx11
BP60 set to priority 1
xx01
BP60 in input mode – rising edge interrupt
xx10
BP60 set to priority 3
xx10
BP60 in input mode – falling edge interrupt
xx01
BP60 set to priority 5
xx00
BP60 in output mode – interrupt disabled
xx00
BP60 set to priority 7
11xx
BP61 in input mode – interrupt disabled
11xx
BP61 set to priority 0
01xx
BP61 in input mode – rising edge interrupt
10xx
BP61 set to priority 2
10xx
BP61 in input mode – falling edge interrupt
01xx
BP61 set to priority 4
00xx
BP61 in output mode – interrupt disabled
00xx
BP61 set to priority 6
26 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
INT6
Edge
Mask
INT4
Data in
INT2
Bidir. Port
Dir.
INT0
BP61
IN_Enable
INT7
Edge
Mask
INT5
BP60
Data in
INT3
Bidir. Port
Dir.
INT1
IN_Enable
decode
decode
decode
decode
I/O bus
P6CR:
CR7
CR6
CR7 CR6
0
0
1
1
0
1
0
1
INT6
INT4
INT2
INT0
CR5 CR4
CR3
CR5
CR4
0
0
1
1
0
1
0
1
CR2 CR1 CR0
INT7
INT5
INT3
INT1
CR1
CR0
CR3
CR2
0
0
1
1
0
1
0
1
Dir.
out
in
in
in
INT
INT
edge
disabled
–
yes
no
no
yes
–
96 11526
Figure 23. Port 6 external interrupts
2.2.5
Bidirectional Port 4
The bidirectional Port 4 is both a bitwise configurable I/O
port and provides the external pins for both the Timer 0
and the internal buzzer generator. As an I/O port, it performs in exactly the same way as bidirectional Port 5, 7,
A, B and C (see figure 20). Two additional multiplexers
allow data and port direction control to be passed over to
other internal modules (Timer 0 or Buzzer). Each of the
four Port 4 pins can be individually switched by the
Timer/Counter I/O Register (TCIO). Figure 24 shows the
internal interfaces to Port 4.
V
I/O Bus
V
DD
DD
Pull-up
T0In
*
*
TCIOy
T0Out
VDD
Static
Pull-up
30 k @ 5 V
*
I/O Bus
D
Q
BP4y
P4DATy
S
(Data out)
*
V
Master reset
DD
(Direction)
I/O Bus
D
S
*
*
Q
Static
Pull-down
P4DDRy
Pull-down
TDir
* Configurable option
Figure 24. Bidirectional Port 4
Rev. A2, 26-Feb-01
27 (61)
Preliminary Information
T48C510
2.2.6
TIM1 – Dedicated Timer 1 I/O Pin
V
T1IN (Timer 1 input)
DD
Pull-up
*
VDD
*
TIM1
T1OUT (Timer 1 output)
*
T1Dir (direction control)
*
* Configurable options
Pull-down
Figure 25. Bidirectional pin TIM1
TIM1 is a dedicated bidirectional I/O stage for signal
communication to and from the Timer 1 in the timer/
counter module (see figure 25). It has no I/O bus interface
and is not directly accessible from the CPU. The direction
control is performed from the timer/counter configuration registers.
Interval Timers / Prescaler
ure 11 ) and consists of a 15-stage binary divider and two
programmable multiplexers for selecting the appropriate
interrupt frequencies for each interrupt source (see figure 26). Each multiplexer is completely independent and
is controlled by the common Interval Timer Frequency
Select Register (ITFSR). Buffer registers store the respective frequency select codes and ensure complete
programming independence of each interrupt channel.
The interval timers are based on a frequency divider for
generating two independent time base interrupts. It is
driven by SUBCL generated by the clock module (see fig-
Interrupt masking and programming of the interrupt
priority levels is performed with the aid of the Interval
Timer Interrupt Priority Register (ITIPR).
2.3
ITIPR
PRB
PRA
MIB
MIA
ITFSR
FS2
FS3
FS1
FS0
INT5
INT1
Buffer
Buffer
Fh
Eh
Dh
INTB Ch
8:1 Bh
Mux Ah
9h
8h
INT6
INT2
8092Hz
2048Hz
4096Hz
R
SUBCL
CK
(e.g. SUBCL = 32 kHz)
7h
6h
5h
INTA 4h
8:1
3h
Mux 2h
1h
0h
8192Hz
4096Hz
2048Hz
1024Hz
256Hz
64Hz
16Hz
8Hz
32Hz
128Hz
1024Hz 256Hz
64Hz
2 2 2 3 2 4 2 5 2 6 27 2 8 2
9
128Hz
64Hz
32Hz
16Hz
8Hz
4Hz
2Hz
1Hz
8Hz
16Hz
2Hz
4Hz
1Hz
210 2 11 212 213 214 215
15-stage binary counter
96 11530
Figure 26. Interval timers / prescaler
28 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
2.3.1
Interval Timer Registers
The Interval Timer Frequency Select Register (ITFSR) is
I/O mapped to the primary address register of the prescaler/ interval timer address (’F’hex) and the Interval
Timer Interrupt Priority Register (ITIPR) to the correInterval Timer Interrupt Priority Register (ITIPR)
sponding auxiliary register. The interrupt masks MIA and
MIB enable interrupt masking of INTA and INTB respectively. Each interrupt source can be programmed with
PRA and PRB to one of two interrupt priority levels. Disabling both interrupts resets the interval timer.
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁ
ÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
ITIPR
Bit 3
Bit 2
Bit 1
Auxiliary register address (write only): ’F’hex
Bit 0
PRB
PRA
MIB
MIA
Reset value: 1111b
PRB – Priority select Interval Timer Interrupt INTB
PRA – Priority select Interval Timer Interrupt INTA
MIB – Mask Interval Timer Interrupt INTB
MIA – Mask Interval Timer Interrupt INTA
Table 13 Interval Timer Interrupt Priority Register (ITIPR)
Code
3210
Function
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
xx11
Reset prescaler and halt
xxx1
Interrupt A disabled
xxx0
Interrupt A enabled
xx1x
Interrupt B disabled
xx0x
Interrupt B enabled
x1xx
Interrupt A => priority 1
x0xx
Interrupt A => priority 5
1xxx
Interrupt B => priority 2
0xxx
Interrupt B => priority 6
Interval Timer Frequency Select Register (ITFSR)
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Primary register address (write only): ’F’hex
ITFSR
Bit 3
Bit 2
Bit 1
Bit 0
FS3
FS2
FS1
FS0
Reset value: 1111b
FS3 ... 0 – Frequency select code
Table 14 Interval Timer Frequency Select Register (ITFSR)
Code
3210
0000
Function
SUBCL
divide by
Code
3210
Function
SUBCL
divide by
215
SUBCL
= 32 kHz
Select 1 Hz
INTA
SUBCL
= 32 kHz
1000
INTB
212
Select 8 Hz
0001
214
Select 2 Hz
1001
211
Select 16 Hz
0010
213
1010
29
Select 64 Hz
0011
212
1011
27
Select 256 Hz
0100
211
1100
25
Select 1024 Hz
0101
210
Select 32 Hz
1101
24
Select 2048 Hz
0110
29
Select 64 Hz
1110
23
Select 4096 Hz
0111
28
1111
22
Select 8192 Hz
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
Á ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
Á ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁ
Select 4 Hz
Select 8 Hz
Select 16 Hz
Select 128 Hz
The control bit FS3 determines whether the INTA or the INTB buffer register is loaded with the select code (FS2–FS0).
This allows independent programming of interval times for INTA and INTB.
Rev. A2, 26-Feb-01
29 (61)
Preliminary Information
T48C510
2.4
Watchdog Timer
NRST
2
14
*
SUBCL
216
15
2
*
*
17-stage binary counter
CK
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Read
WDRES
Master
Reset
*
Watchdog enable
* Configurable option
VDD
Figure 27. Watchdog timer
The watchdog timer is a 17-stage binary divider clocked
by SUBCL generated within the clock module (see figures 11 and 27). It can only be enabled as a configurable
option whereby it must be periodically reset from the application program. The program cannot disable the
watchdog. If the CPU find itself for an extended length of
time in SLEEP mode or in a section of program that includes no watchdog reset, then the watchdog will
overflow, thus forcing the NRST pin low. This initiates a
master reset. The timeout period can be set to 0.5, 1 or 2
seconds (if SUBCL = 32 kHz) by using a configurable option.
To reset the watchdog, the program must perform an INinstruction on the address CWD (’3’hex). No relevant
data is received. The operation is therefore normally followed by a DROP to flush the data from the stack.
2.5
Timer/Counter Module (TCM)
The TCM consists of two timer/counter blocks (Timer 0
and Timer 1) which can be used separately, or together as
a single 16-bit counter/timer (see figures 28 and 30). Each
timer can be supplied by various internal or external clock
sources. These can be selected and divided under program
control using the Timer/Counter Control Register
(TCCR), the Timer 0 Control Register (T0CR) and the
Timer 1 Control Register (T1CR). Capture and compare
registers (T0CA,T1CA,T0CP and T1CP) not only allow
event counting, but also the generation of various timed
output waveforms including programmable frequencies,
modulated melody tones, Pulse Width Modulated (PWM)
and Pulse Density Modulated (PDM) output signals.
When in one of these signal generation modes, the capture
register acts as timer shadow register, the current timer
state is freezed whenever read by the CPU. The Timer 0
is further equipped for performing a variety of time measurement operations. In this mode the capture register is
used together with the gating logic for performing
asynchronous, externally triggered snapshot measurements. These measurements include single input pulse
width and period measurements and also dual input phase
and positional measurement. The mode configuration is
set in the Timer 0 and Timer 1 Mode Registers (T0MO
and T1MO).
Each timer represents a single maskable interrupt source
(T0INT and T1INT), the priority of which can be configured under program control. A Timer 0 interrupt can be
caused by any of three conditions (overflow, compare or
end-of-measurement). The associated status register
(T0SR) differentiates between these. A status register is
not necessary in the Timer 1 as an interrupt is caused only
on a compare condition.
30 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
Timer 0
T0IN1
Capture
register
T0IN0
SYSCL
ck
Prescaler
rst
MUX
4:1
SUBCL
Gating
control
Status
register
T0CA
T0SR
up/down
MUX
8:1
Clock
control
up/down
counter
overflow
end–of–
measu–
rement
reset
Reload
control
Compare
T0CR
Compare
register
T0MO
T0OUT1
Output
control
T0CP
T0OUT0
Int
T0INT
Int. enable
T1OUT
TCCR
TCMO
T0OUT0
T1CR
16–bit mode
Int. enable
T1MO
Compare
register
T1INT
Int
Output
control
T1CP
T1OUT
carry
Reload
control
Compare
reset
MUX
8:1
SUBCL
MUX
4:1
SYSCL
MUX
2:1
rst
Prescaler
ck
Clock
control
up/down
counter
overflow
T1CA
Capture
register
T1IN
Timer 1
13909
< = CPU Read/write registers
Figure 28. Timer/counter module
Rev. A2, 26-Feb-01
31 (61)
Preliminary Information
T48C510
2.5.1
General Timer/Counter Control Registers
With the exception of the Timer 0 Interrupt Status Register (T0SR), all the timer/counter registers are indirectly
addressed using extended addressing as described in the
section “Addressing peripherals”. An overview of all register and subport addresses is shown in table 7. The
Timer/Counter auxiliary register (TCSUB) holds the subport address of the particular register about to be
accessed.
Care has to be taken to ensure that this subport access sequence is not interrupted. Please refer to the
’HARDC510.SCR’ hardware interface file as a programming guideline.
Timer/Counter Clock Control Register (TCCR)
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Subport address (indirect write access): ’6‘hex of Port address ’9‘hex
TCCR
Bit 3
Bit 2
Bit 1
Bit 0
T1CL2
T1CL1
T0CL2
T0CL1
T0CL2, T0CL1 – Timer 0 Clock source select
Reset value: 1111b
T1CL2, T1CL1 – Timer 1 Clock source select
Table 15 Timer/Counter Clock Control Register (TCCR)
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
Code
3210
*
Function
Direction (TDir)
BP40*
TIM1
xx00
Timer 0 clock = SUBCL
out
x
xx01
Timer 0 clock = SYSCL
out
x
xx10
Timer 0 clock = Timer1 output (T1OUT connected internally)
out
x
xx11
Timer 0 clock = T0IN0 ( BP40*)
in
x
00xx
Timer 1 clock = SUBCL
x
out
01xx
Timer 1 clock = SYSCL
x
out
10xx
Timer 1 clock = Timer 0 output (T0OUT0 connected internally)
x
out
11xx
Timer 1 clock = TIM1
x
in
if TCIO0 = low (connects Timer 0 to Port 4)
The Timer/Counter Clock Control Register (TCCR) controls the clock source to both Timer 0 and Timer 1 prescalers.
If an external clock source (on BP40 or TIM1) is selected, then the corresponding port direction is automatically
switched to input mode (see figure 27).
Note: The TCIO0 bit must be set low for the BP40 external timer/counter access.
32 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
Timer/Counter Interrupt Priority Register (TCIP)
The Timer/Counter Interrupt Priority register (TCIP) is used to configure the Timer 0 and Timer 1 interrupt priority
levels.
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁ
Á
ÁÁÁ
ÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Bit 3
T1IP2
TCIP
Bit 2
T1IP11
Subport address (indirect write access): ’7’hex of Port address ’9‘hex
Bit 1
Bit 0
T0IP2
T0IP1
Reset value: 1111b
T0IP2, T0IP1 – Timer 0 Interrupt Priority code
T1IP2, T1IP1 – Timer 1 Interrupt Priority code
Table 16 Timer/Counter Interrupt Priority Register (TCIP)
Code
3210
Function
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
xx11
Timer 0 interrupt priority 1
xx10
Timer 0 interrupt priority 3
xx01
Timer 0 interrupt priority 5
xx00
Timer 0 interrupt priority 7
11xx
Timer 1 interrupt priority 0
10xx
Timer 1 interrupt priority 2
01xx
Timer 1 interrupt priority 4
00xx
Timer 1 interrupt priority 6
Timer/Counter I/O Control Register (TCIOR)
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Subport address (indirect write access): ’5’hex of Port adddress ’9‘hex
Bit 3
TCIO3
TCIOR
Bit 2
TCIO2
Bit 1
TCIO1
Bit 0
TCIO0
Reset value: 1111b
TCIO3...0 – Timer / Counter I/0 mode select
Table 17 Timer/Counter I/O Control Register (TCIOR)
Code
3210
xxx1
xxx0
xx1x
xx0x
x1xx
x0xx
1xxx
Function
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
BP40 – standard port mode
BP40 – Timer 0 clock input (T0IN0) or Timer 0 output (T0OUT0)
BP41 – standard port mode
BP41 – Timer 0 gate input (T0IN1) or Timer 0 output (T0OUT1)
BP42 – standard port mode
BP42 – Buzzer output (BUZ)
BP43 – standard port mode
0xxx
BP43 – Buzzer output (NBUZ)
By using the Timer/Counter I/O Control Register
(TCIOR) the program can configure the respective Port 4
pins as either standard data I/O ports or as external signal
ports for the Timer 0 and Buzzer. The Timer 1 uses a dedicated I/O pin TIM1, whose direction is controlled solely
by the TCCR (see figure 29). It should be noted that if a
TCIOR bit is set low, then the corresponding port data
direction register (P4DDR) bit no longer influences the
port direction. In the case of BP40 and BP41, the port
direction is then controlled entirely by the timer/counter
configuration registers (TCCR,T0MO), while pins BP42
and BP43 become unidirectional buzzer outputs.
Rev. A2, 26-Feb-01
33 (61)
Preliminary Information
T48C510
TIMER 0
T0IN0
P4DAT0
BP40
T0OUT0
TCIO0
P4DDR0
TCCR
to CPU
Select Ext. Clock
T0IN1
P4DAT1
BP41
T0OUT1
TCIO1
T0MO
PWM,PDM
P4DDR1
to CPU
Melody,Counter
P4DAT2
BUZZER
BUZ
BP42
TCIO2
P4DDR2
to CPU
’0’
P4DAT3
BP43
NBUZ
TCIO3
P4DDR3
TIMER 1
to CPU
’0’
T1IN
TIM1
T1OUT
TCCR
Select Ext. Clock
96 11533
Figure 29. Timer/counter and buzzer external interface
Timer/Counter Mode Register (TCMO)
ÁÁÁÁÁÁ
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ÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Subport address (indirect write access): ’4’hex of Port address ’9‘hex
TCMO
Bit 3
T0NINV
Bit 2
TC8
Bit 1
T1RST
Bit 0
T0RST
T0NINV
– Timer 0 output (BP41) appears non-inverted at BP40
TC8
– Timer/Counter in 8-/16-bit mode
T1STP
– Timer 1 Stop/Run
T0STP
– Timer 0 Stop/Run
Reset value: 1111b
Table 18 Timer/Counter Mode Register (TCMO)
Code
3210
Function
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
xxx0
Timer 0 running
xxx1
Timer 0 halted
xx0x
Timer 1 running
xx1x
Timer 1 halted
x0xx
Timer/counter in 16-bit mode
x1xx
Timer/counter in 8-bit mode
0xxx
Inverted output BP41 appears on BP40 (BP40 = NOT BP41)
1xxx
Non-inverted output BP41 appears on BP40 (BP40 = BP41)
34 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
2.5.2
Timer/Counter in 16-bit Mode
Timer 0
Compare
Register
Comparator
Compare
Register
Timer 1
Carry
Comparator
Compare
Interrupt
Counter
to TIM1
8bit/16bit
Prescaler
Counter
Prescaler
MUX
Overflow/compare
96 11549
Figure 30. 16-bit mode
In 16-bit mode, Timer 0 and Timer 1 are cascaded thus
forming a 16-bit counter (see figure 30) whereby, irrespective of the state of Timer 0 interrupt mask bit (T0IM),
the Timer 1 counts both Timer 0 overflow and compares
interrupt events. These are generated according to the
state of the Timer 0 Mode Register as described in the
T0MO table. The comparators are also cascaded so that
when both Timer 0 and Timer 1 match their respective
compare registers, the Timer 1 generates both an output
signal and a compare interrupt (if unmasked).
In measurement modes, only Timer 0 capture register is
loaded with Timer 0’s contents on an end-of-measurement event. Timer 1 capture register operates solely as a
shadow register. There is no 16-bit capture operation, so
the user program must check if Timer 1 has incremented
between reading the lower and higher byte. Likewise,
there is no automatic suppression of spurious interrupts
which could conceivably be generated between writing
Timer 0 and Timer 1 compare registers.
2.5.3
Timer 0 Modes
The Timer 0 mode configuration is defined in the Timer 0
Mode Register (T0MO). The available modes and the
effect on the Timer 0 interrupt and interrupt flags is shown
below. In all modes except the position measurement
mode, Timer 0 acts as an up-counter, the related clock frequency being defined by the selected clock source and the
prescaler division factor. The counter can be reset and
halted at any time by the T0RST bit of the TCMO register
which also resets all the interrupt status flags and capture
registers. Whenever Port 4 BP40 and BP41 pins are required for Timer 0 I/O, then the appropriate TCIOR
enable bit must be set low. In this case, the port direction
switching is handled automatically by the hardware. In
modes where the BP40 is not used as a timer clock input
or as a melody envelope output, the BP40 outputs the
same signal as that appearing on BP41. With the help of
the T0NINV bit of the Timer/Counter Mode Register
(TCMO), the BP41 output can be inverted so that BP40
and BP41 form a differential output stage which can be
used for directly driving piezo buzzers or small stepper
motors.
Rev. A2, 26-Feb-01
35 (61)
Preliminary Information
T48C510
Timer 0 Mode Register (T0MO)
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁ
Subport address (indirect write access): ’0’hex of Port adress ’9’hex
Bit 3
T0MO3
T0MO
Bit 2
T0MO2
Bit 1
T0MO1
Bit 0
T0MO0
Reset value: 1111b
T0MO3 ... 0 – Timer 0 Mode Code
Table 19 Timer 0 Mode Register (T0MO)
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁ
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ÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁ
Code
3210
Function
Assuming TCIOR1=TCIOR0=low
BP40 (*3)
BP41
Interrupt set /
T0SR affected
cmp
ofl
eom
0000
reserved
–
–
–
0001
reserved
–
–
–
0010
Modulated melody mode
Envelope (out)
Tone (out)
y/y
y/y
n/n
0011
Melody mode
Tone (out)
Tone (out)
y/y
y/y
n/n
0100
Counter-auto reload (50% duty cycle)
Toggle (out) /Clock (in)
Toggle (out)
y/y
y/y
n/n
0101
Counter-free running (50% duty cycle)
Toggle (out) /Clock (in)
Toggle (out)
n/y
y/y
n/n
0110
Pulse density modulation
PDM (out) /Clock (in) PDM (out)
n/y
y/y
n/n
0111
Pulse width modulation
PWM (out) /Clock (in)
PWM (out)
n/y
y/y
n/n
1000
Phase measurement
Signal 1 (in)
Signal 2 (in)
n/n
y/y
y/y
1001
Position measurement
Signal 1 (in)
Signal 2 (in)
(*1)
(*2)
n/n
1010
Low pulse width measurement
Clock (in)
Signal (in)
n/y
y/y
y/y
1011
High pulse width measurement
Clock (in)
Signal (in)
n/y
y/y
y/y
1100
Counter- auto reload (strobe)
Strobe (out) /Clock (in)
Strobe (out)
y/y
y/y
n/y
1101
Counter-free running (strobe)
Strobe (out) /Clock (in)
Strobe (out)
n/y
y/y
n/y
1110
Period measurement (rising edge)
Clock (in)
Signal (in)
n/y
y/y
y/y
1111
Period measurement (falling edge)
Clock (in)
Signal (in)
n/y
y/y
y/y
*1 Note:
The compare interrupt/status flag can only be set when counting up.
*2 Note:
The overflow interrupt/status flag is set on both an overflow or an underflow.
*3 Note:
The BP40 signals can be inverted if T0NINV=0 (TCMO register)
Timer 0 Interrupt Status Register (T0SR)
ÁÁÁÁÁÁ
ÁÁÁÁÁ
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ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Auxiliary register address (read access): ’9’hex
T0SR
Note:
Bit 3
Bit 2
Bit 1
Bit 0
not used
T0EOM
T0OFL
T0CMP
Reset value: x000b
The status register is reset automatically when read and also when Timer 0 is reset.
T0EOM– Timer 0 End Of Measurement status flag
T0OFL – Timer 0 OverFLow status flag
T0CMP – Timer 0 CoMPare status flag
36 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
Table 20 Timer 0 Interrupt Status Register (T0SR)
Code
3210
Function
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
xxx1
Timer 0 compare has occurred (Timer 0 = T0CP)
xx1x
Timer 0 overflow or underflow has occurred
x1xx
Timer 0 measurement completed
The interrupt flags will be set whenever the associated condition occurs irrespective of whether the corresponding interrupt is triggered. Therefore, the status flags are still set if the interrupt condition occurs when the interrupt is masked.
To see exactly when the flags are set, see T0MO control code table 18.
Reading from the timer/counter auxiliary register will access the Timer 0 Interrupt Status Register (T0SR).
Timer 0 Control Register (T0CR)
The T0CR is responsible for the predivision of the selected Timer 0 input clock (see TCCR). It can be divided or used
directly as clock for the up/down counter. Bit 0 is the mask bit for the Timer 0 interrupt.
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
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ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Subport address (indirect write access): ’1’hex of Port address ’9‘hex
Bit 3
T0FS3
T0CR
Bit 2
T0FS2
Bit 1
T0FS1
Bit 0
T0IM
Reset value: 1111b
T0FS3 ... 1 – Timer 0 prescaler division factor code
T0IM – Timer 0 Interrupt Mask
Table 21 Timer 0 Control Register (T0CR)
Code
3210
Function
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
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xxx1
Timer 0 interrupt disabled
xxx0
Timer 0 interrupt enabled
000x
Timer 0 prescaler divide by 256
001x
Timer 0 prescaler divide by 128
010x
Timer 0 prescaler divide by 64
011x
Timer 0 prescaler divide by 32
100x
Timer 0 prescaler divide by 16
101x
Timer 0 prescaler divide by 8
110x
Timer 0 prescaler divide by 4
111x
Timer 0 prescaler bypassed
Rev. A2, 26-Feb-01
37 (61)
Preliminary Information
T48C510
Timer 0 Compare Register (T0CP) – Byte Write
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Subport address (indirect write access): ’9’hex of Port address ’9‘hex
T0CP
First write cycle
Second write cycle
Bit 3
Bit 2
Bit 1
Bit 0
T0CP3
T0CP2
T0CP1
T0CP0
Bit 7
Bit 6
Bit 5
Bit 4
T0CP7
T0CP6
T0CP5
T0CP4
Reset value: xxxxb
Reset value: xxxxb
T0CP3 ... T0CP0 – Timer 0 Compare Register Data (low nibble) – first write cycle
T0CP7 ... T0CP4 – Timer 0 Compare Register Data (high nibble) – second write cycle
The compare register T0CP is 8-bit wide and must be accessed as byte wide subport (see section ”Addressing Peripherals). First of all, the data is written low nibble and is then followed by the high nibble. Any timer interrupts are
automatically suppressed until the complete compare value has been transferred.
Timer 0 Capture Register (T0CA) – Byte Read
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Subport address (indirect read access): ’9’hex of Port address ’9‘hex
T0CA
First read cycle
Second read cycle
Bit 7
Bit 6
Bit 5
Bit 4
T0CA7
T0CA6
T0CA5
T0CA4
Bit 3
Bit 2
Bit 1
Bit 0
T0CA3
T0CA2
T0CA1
T0CA0
Reset value: xxxxb
Reset value: xxxxb
T0CA7. .. T0CA4 – Timer 0 Capture Register Data (high nibble) – first read cycle
T0CA3 ... T0CA0 – Timer 0 Capture Register Data (low nibble) – second read cycle
Note:
If the timer is read (in PDM mode only) the bit order will appear reversed, so that T0CA0 =MSB,
T0CA1=MSB-1 .... T0CA6=LSB+1, T0CA7 = LSB.
The 8-bit capture register T0CA is read as byte wide subport. Note, however, unlike the writing to the compare register,
the high nibble is read first followed by the low nibble. The 8-bit timer state is captured on reading the first nibble and
held until the complete byte has been read. During this transfer, the timer is free to continue counting.
38 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
Timer 0 Free Running Counter Modes (Strobe and 50% Duty Cycle)
In the free running counter mode, Timer 0 can be used as an event counter for summing external event pulses on BP40,
or as a timer with an internal time-based clock. When enabled, the counter will count up generating an output signal
on BP41 whenever the counter contents match the compare register (see figure 31). This signal can appear either as
a strobe pulse or as a simple toggling of the output state (50% duty cycle) depending on the timer mode. Interrupts (if
not masked) are generated every 256 clocks on the overflow condition. The current counter state can be read at any
time by reading the capture register,. The compare register has no effect on the counter cycle time and will not influence
interrupts.
Timer
State
255
Overflow
Interrupt
0
1
2
ÏÏ
3
4
5 6
255
0
1
2
3
Ï
4
5 6
255
0
1
2
Ï
3
4
5 6
strobe
T0OUT1
(BP41)
50% duty
cycle
Timer
Clock
Timer resets
on overflow
Timer = compare register (= 4)
96 11534
Figure 31. Timer 0 free running counter mode
Timer 0 Counter Reload Modes (Strobe and 50% Duty Cycle)
As in the free running mode, the counter can also be clocked from either an external signal on BP40 or from an internal
clock source. In this mode, the counter repetition period is completely defined by the contents of the compare register
(T0CP) (see figure 32). The counter counts up with the selected clock frequency. When it reaches the value held in
the compare register, the counter then returns to the zero state. At the same time, depending on the selected timer mode,
the BP41 either toggles or generates a strobe pulse. If the Timer 0 interrupt is unmasked, a compare interrupt is also
generated.
The resultant output frequency fOUT = fIN/2*(n+1) where
n = compare value (n = 1 – 255).
ÏÏ
ÏÏ
ÏÏ ÏÏ
Timer
State
Ï
Ï
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0
Compare
Interrupt
strobe
T0OUT1
(BP41)
50% duty
cycle
Timer
Clock
Timer = compare register (= 7)
Resets timer
96 11535
Figure 32. Timer 0 counter reload mode
Rev. A2, 26-Feb-01
39 (61)
Preliminary Information
T48C510
Melody Mode (with/without Modulation)
The non-modulated melody mode is identical to the auto- reload counter (50% duty cycle) mode. The melody tone
frequency appearing on BP41 and/or BP40 is determined in exactly the same way as the value written into the
comparator register. In the modulated melody mode, the T48C510 generates two output signals, a melody tone and
an envelope pulse (see figure 33). The tone frequency output on BP41 is generated in exactly the same way as in the
simple melody mode. While the envelope pulse on BP40 is a single pulse, of a clock period in duration which appears
shortly after loading the compare value into the compare register. In this mode, an analog switch is activated between
the BP40 and BP41 outputs (see figure 34). With the external capacitor connected, the resultant signal on BP41 exhibits
a melody chime effect with an exponential decay.
01 2 3 4 5 6
0 2 4 6 0 2 4 6 0 2 4 6
0 2 4 6
7 1 3 5 7 1 3 5 7 1 3 5 7 1 3 5 7
Timer
State
Compare
Interrupt
T0OUT1
(BP41)
T0OUT0
(BP40)
Timer
Clock
Timer = compare register
resets timer
New value (=7) loaded
into compare register
96 11538
Figure 33. Modulated melody mode
V DD
T0OUT0
(melody output)
V
DD
BP40
Modulated
melody mode
Analog switch
T0OUT1
(envelope)
R
(optional)
10...47uF
BP41
Piezo
buzzer
VSS
V SS
T0OUT1
T0OUT0
BP41
BP40
96 11539
Figure 34. Modulated melody output circuit
40 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
Timer 0 Pulse Width Modulation Mode
A pulse width modulated (PWM) signal exhibits a fixed repetition frequency and a variable mark space ratio. It is often
used as a simple method for D/A conversion, where the high period is proportional to the digital value to be converted.
Therefore by connecting a simple low-pass RC network to the PWM signal, the analog value can be retrieved.
Timer 0 generates the PWM signal by comparing the state of the free running up counter with the contents of the
compare register (see figure 35). If the result is less than the compare register value, then the BP41 output is high. If
the result is greater or equal to the compare register value, then the BP41 output is set low. Thus, the high phase of
the PWM signal is directly proportional to the compare register contents. A total of 256 possible discrete mark space
ratios can be generated ranging from a continuous low signal over a variable pulse width signal to a continuous high
signal. The PWM signal has a repetition period of 256 clocks, an interrupt (if unmasked) being generated on every
overflow event. Care should be taken if the SYSCL clock is used as the PWM clock source because it may stop if the
CPU goes into SLEEP mode (see Section 1.5.4 Power-Down Modes).
Timer
State
255
0
1
2
ÏÏ
3
4
255
0
1
ÏÏ
3
4
255
0
1
Ï
3
4
Overflow
Interrupt
t_hi
t_low
T0OUT1
(BP41)
Timer
Clock
Timer = compare register (= 4)
t_hi = (comparator value)*clock period
t_low = (255–comparator value)*clock period
96 11540
Figure 35. Timer 0 pulse width modulation
Pulse Density Modulation Mode
Pulse density modulation (PDM) is also used for simple D/A conversion. Unlike the PWM signal,where the high and
low signal phases are always continuous during a single repetition cycle, the PDM distributes these evenly as a series
of pulses (see figure 36). This has the advantage that, if used together with an RC smoothing filter for D/A conversion,
either the ripple is less than the PWM, or, for a corresponding ripple error, the filter components can be smaller or the
clock frequency lower. To generate the PDM output on BP41, the pulse density is controlled by the contents of the
compare register in the same way as the PWM generation. Each of the pulses has a width equal to the counter clock
period.
Repetition period
PWM=0.25
PWM=0.75
PDM=0.25
PDM=0.75
96 11541
Figure 36. An example 4-bit PWM/PDM comparison
Rev. A2, 26-Feb-01
41 (61)
Preliminary Information
T48C510
Period Measurement Modes (Rising and Falling Edge)
During the period measurement mode, the counter counts the number of either internal or external clocks in one period
of the BP41 input signal (see figure 37). Dependent on the mode chosen, this will be from rising edge to the next rising
edge or conversely, falling edge to the following falling edge. On the trigger edge, the counter state is loaded into the
capture register and subsequently reset. The measured value remains in the capture register until overwritten by the
following measured value. Interrupts can be generated by either an overflow condition or an end-of-measurement
(eom) event. An ’eom’ event signals the CPU that a new measured value is present in the capture register and can be
read, if required.
Captures and resets timer
”eom”
Interrupt
t_period
t_period
T0IN1
(BP41)
Falling edge triggered
Rising edge triggered
96 11542
Figure 37. Period measurement
Pulse Width Measurement Modes (High and Low)
In this mode, the selected clock source is gated to the counter for the duration of each input pulse received on BP41
(see figure 38). Whether the measurement takes place during the high or low phase depends on the selected mode. At
the end of each pulse, the counter state is loaded into the capture register and subsequently reset. Interrupts can be generated by either an overflow condition or an end-of-measurement (eom) event. An ’eom’ event signals the CPU that
a new measured value is present in the capture register can be read, if required.
Captures and resets timer
”eom”
Interrupt
t_low
t_high
T0IN1
(BP41)
96 11543
Figure 38. Pulse width measurement
42 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
Phase Measurement Mode
This mode allows the Timer 0 to measure the phase misalignment between two 1:1 mark space ratio input signals connected to the BP40 and BP41 pins (see figure 39). The counter clock is gated with the phase misalignment period (tp),
during which time the counter increments with the selected clock frequency. This misalignment period is defined as
the period during which BP40 is high and BP41 is low. Capturing and resetting of the counter always takes place on
the rising edge of BP41. The measured value remains in the capture register until overwritten by the next measurement.
Interrupts can be generated by either an overflow condition or an end-of-measurement (’eom’) event. An ’eom’ event
signals the CPU that a new measured value is present in the capture register and can be read, if required.
Captures & resets timer
”eom”
Interrupt
tp
tp
tp
T0IN0
(BP40)
T0IN1
(BP41)
96 11544
Figure 39. Phase measurement
Position Measurement Mode
This mode is intended for the evaluation of positional sensors with biphase output signals. Figure 40 illustrates a typical
positional sensor system which delivers both incremental positional stepping signals and also directional information.
The direction can be deduced from the relative phase of the two signals. Therefore if BP40 is high on the rising edge
of BP41, the moving mask travels to the left and if it is low then it travels to the right. The direction (left/right) information is used to set the direction of the up/down counter which enables the BP40 pulses to be counted. Assuming that
the system has been reset on a reference position, the counter will always hold the absolute current position of the moving mask. This can be read by the CPU if necessary. This mode is the only one in which the counter is allowed to
decrement. Therefore, in this case it is possible for both an underflow or an overflow to occur. The overflow interrupt
(if unmasked) will trigger on either of these conditions while the compare interrupt on the other hand will only trigger
if the counter is counting upwards. To differentiate between an overflow or underflow, the compare value can be set
to ’0’ hex, for example. An overflow would then set both the overflow and compare status flags while an underflow
sets the overflow status flag only.
T0IN0
Typical sensor
T0IN1
ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ
Moving mask
Static mask
light
Timer
N
left movement
N+1
N+2
light
N+3
N
right movement
N–1
N–2
N–3
T0IN0
(BP40)
T0IN1
(BP41)
96 11545
Figure 40. Position measurement mode
Rev. A2, 26-Feb-01
43 (61)
Preliminary Information
T48C510
2.5.4
Timer 1 Modes
The Timer 1 is aimed at performing event counting and
timing functions (see figure 28). It has, unlike the
Timer 0, no gated clock or externally triggered capture
modes. The counter counts up with an internal or external
clock, depending on the state of the Timer 1 Control Register (T1CR) and the Timer/Counter Clock Control
Register (TCCR) and generates a compare interrupt
whenever the counter matches the Timer 1 compare register. This is the only Timer 1 interrupt source. Masking can
be performed using the mask bit in the Timer 1 Control
Register (T1CR) and priority can be defined in the Timer/
Counter Interrupt Priority Register (TCIP). The TIM1 pin
is used by the Timer 1 either as clock/event input or timer
output. I/O control of the Timer 1 pin TIM1 is controlled
entirely by the hardware, therefore if the TIM1 is selected
as an external clock or event source (in the TCCR), there
can be no Timer 1 signal output. In this case, the timer
would be used solely to generate interrupts.
In autostop operation, the Timer 1 will halt both itself and
Timer 0 whenever the Timer 1 compare value is reached.
This feature can be used for example to generate an exact
burst of pulses. Both timers will remain stopped until
restarted. Restarting is performed in the normal way by
setting the appropriate control bits in the Timer/Counter
Mode Register (TCM0).
Timer 1 Mode Register (T1MO)
ÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁ
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Subport address (indirect write address): ’2’hex of Port address ’9‘hex
T1MO
Bit 3
T1MO3
Bit 2
T1MO2
Bit 1
T1MO1
Bit 0
T1MO0
Reset value: 1111b
T1MO3 ... 0 – Timer 1 Mode Control
Table 22 Timer 1 Mode Register (T1MO)
Code
3210
Function
Compare
Interrupt
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
xx00
Counter free running (50% duty cycle)
yes
xx01
Counter auto reload (50% duty cycle)
yes
xx10
Pulse width modulation
yes
xx11
Counter auto-reload (strobe output)
yes
x0xx
Increment on falling edge of clock
–
x1xx
Increment on rising edge of clock
–
1xxx
Normal operation (no autostop)
yes
0xxx
Autostop operation (Timer 1 stops Timer 2)
yes
Timer 1 Control Register (T1CR)
The T1CR is responsible for the predivision of the selected Timer 1 input clock (see TCCR). It can be divided or used
directly as clock for the up counter. Bit 0 is the mask bit for the Timer 1 interrupt.
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
Subport address (indirect write access): ’3’hex of Port adress ’9‘hex
T1CR
T1FS3 ... 1
T1IM
Bit 3
T1FS3
Bit 2
T1FS2
Bit 1
T1FS1
Bit 0
T1IM
Reset value: 1111b
– Timer 1 Prescaler Division Factor Code
– Timer 1 Interrupt Mask
44 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
Table 23 Timer 1 Control Register (T1CR)
Code
3210
Function
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
xxx1
Timer 1 interrupt disabled
xxx0
Timer 1 interrupt enabled
000x
Timer 1 prescaler divide by 256
001x
Timer 1 prescaler divide by 128
010x
Timer 1 prescaler divide by 64
011x
Timer 1 prescaler divide by 32
100x
Timer 1 prescaler divide by 16
101x
Timer 1 prescaler divide by 8
110x
Timer 1 prescaler divide by 4
111x
Timer 1 prescaler bypassed
Timer 1 Compare Register (T1CP) – Byte Write
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Subport address (indirect write access): ’8’hex of Port address ’9‘hex
T1CP
First write cycle
Second write cycle
Bit 3
Bit 2
Bit 1
T1CP3
T1CP2
T1CP1
Bit 7
Bit 6
Bit 5
T1CP7
T1CP6
T1CP5
Bit 0
T1CP0
Reset value: xxxxb
Bit 4
T1CP4
Reset value: xxxxb
T1CP3 ... T1CP0 – Timer 1 Compare Register Data (low nibble) – first write cycle
T1CP7. .. T1CP4 – Timer 1 Compare Register Data (high nibble) – second write cycle
The compare register T1CP is 8 bits wide and must be accessed as byte wide subport (see section “Addressing Peripherals”). The data is written low nibble first, followed by high nibble. Any timer interrupts are automatically suppressed
until the complete compare value has been transferred.
Timer 1 Capture Register (T1CA) – Byte Read
Subport address (indirect read access): ’8’hex of Port address ’9‘hex
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T1CA
First read cycle
Second read cycle
Bit 7
Bit 6
Bit 5
Bit 4
T1CA7
T1CA6
T1CA5
T1CA4
Bit 3
Bit 2
Bit 1
Bit 0
T1CA3
T1CA2
T1CA1
T1CA0
Reset value: xxxxb
Reset value: xxxxb
T1CA7 ... T1CA4 – Timer 1 Capture Register Data (high nibble) – first read cycle
T1CA3 ... T1CA0 – Timer 1 Capture Register Data (low nibble) – second read cycle
The 8-bit capture register T1CA is read as byte-wide subport. Note, however, unlike the writing to the compare register,
the high nibble is read first followed by low nibble. The 8-bit timer state is captured on reading the first nibble and held
until the complete byte has been read. During this transfer, the timer is free to continue counting. The previous capture
value will be held until the timer is restarted again.
Rev. A2, 26-Feb-01
45 (61)
Preliminary Information
T48C510
Timer 1 Counter Free Running (50% Duty Cycle)
In the free running counter mode, the counter counts up with either an internal or external clock and cycles through
all 256 timer states. On the clock following a match between the compare register (T1CR) and the counter, a compare
interrupt (if unmasked) is generated and the TIM1 pin is toggled (see figure 40).
Timer
State
255
Compare
Interrupt
T1OUT
(TIM1)
0
1
2
3
Ï
4
5 6
255
0
1
2
ÏÏ
3
4
5 6
255
0
1
2
ÏÏ
3
4
5 6
50% duty
cycle
Timer
Clock
(clock set to rising edge)
Timer = compare register (= 4)
96 11546
Figure 41. Timer 1 counter free running (50% duty cycle)
Timer 1 Counter Auto Reload (Strobe and 50% Duty Cycle)
In the auto-reload mode, the counter counts up with either an internal or external clock. On the clock cycle following
a match between the compare register (T1CR) and the counter, a compare interrupt (if unmasked) is generated. The
TIM1 output is either strobed or toggled and the counter reset (see figure 42). Therefore, the counter cycle period is
defined by the contents of the compare register. In 50% duty cycle mode the frequency of TIM1 is:
fTIM1 = fin/2(n+1)
where the compare value (n) =1 ... 255.
Ï
Timer
State
ÏÏ
Ï
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0
Compare
Interrupt
strobe
T1OUT
(TIM1)
50% duty
cycle
Timer
Clock
(clock set to neg. edge)
Timer = compare register (= 7)
Resets timer
96 11547
Figure 42. Timer 1 counter auto reload
46 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
Timer 1 Pulse Width Modulation
The Timer 1 generates the PWM signal by comparing the state of the free running up counter with the contents of the
compare register (see figure 43). If the result is less or equal to the compare register value, then the TIM1 output is
high. If the result is greater than the compare register value, then the TIM1 output is set low. Thus, the high phase of
the PWM signal is directly proportional to the compare register contents. A total of 256 possible discrete mark space
ratios can be generated ranging from a continuous low signal over a variable pulse width signal. The PWM signal has
a repetition period of 256 clock periods, an interrupt (if unmasked) being generated on every compare event.
Care should be taken if SYSCL is used as the PWM clock source. The PWM output may stop if the CPU goes into
SLEEP depending on the programming of the NSTOP bit in the CM-register. Using this mode of operation recommends
to set the bit NSTOP =1.
Timer
State
255
0
1
2
Ï
3
4
255
0
1
2
ÏÏ
3
4
255
0
1
ÏÏ
2
3
4
Compare
Interrupt
t_hi
t_low
T1OUT
(TIM1)
Timer
Clock
t_hi = (comparator value)*clock period
t_low = (256-comparator value)* clock period
Timer = compare register (=4)
96 11548
Figure 43. Timer 1 pulse width modulation
2.6
Buzzer Module
The buzzer is a 4 stage frequency divider which divides the SUBCL and depending on the state of the Buzzer Control
Register (BZCR) can output one of four frequencies. An external piezo or buzzer can be driven by the complementary
buzzer outputs (BUZ and NBUZ) which are directed to Port 4 (BP42 and BP43) under control of the Timer/Counter
I/O Register (TCIOR) as shown in figure 28. When the buzzer is switched off, both of the buzzer outputs take up the
same logical state. This is controlled by the BZOP bit of the BZCR.
BZCR
BZFS2 BZFS1 BZOP BZOF
NBUZ
SUBCL (32 kHz)
SUBCL / 4 (8 kHz)
SUBCL / 8 (4 kHz)
BUZ
4 :1
MUX
SUBCL / 16 (2 kHz)
SUBCL
CK
R
4 stage divider
R
R
R
96 11550
Figure 44. Buzzer module
Rev. A2, 26-Feb-01
47 (61)
Preliminary Information
T48C510
Buzzer Control Register (BZCR)
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Subport address (indirect write access): ’A‘hex of Port adress ’9‘hex
BZCR
Bit 3
BZFS2
Bit 2
BZFS1
Bit 1
BZOP
BZFS2, BZFS2
– Buzzer Frequency Select code
BZOP
– Buzzer Output Stop State
BZOF
– Buzzer off/on
Bit 0
BZOF
Reset value: 1111b
Table 24 Buzzer Control Register (BZCR)
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Code
3210
Function
xxx0
Buzzer on
xxx1
Buzzer off
xx0x
Buzzer output stop state: BP42 = BP43 = low
xx1x
Buzzer output stop state: BP42 = BP43 = high
00xx
Buzzer frequency: 32 kHz (= SUBCL)
01xx
Buzzer frequency: 8 kHz (= SUBCL / 4)
10xx
Buzzer frequency: 4 kHz (= SUBCL / 8)
11xx
Buzzer frequency: 2 kHz (= SUBCL / 16)
BUZ
BZOP=1
NBUZ
BUZZER Off
BUZ
BZOP=0
NBUZ
96 11551
Figure 45. Buzzer waveform
48 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
2.7
MTP Programming
The state of the T48C510 PM pin defines the MTP operational mode ie. PM = high (Program Mode), PM = low
(Normal operation Mode) while the 3 TPI data lines are
used to serially load or read the customer’s data into or out
of the T48C510.
Application Program
In Circuit Programmer (ICP)
Target Programmer Interface (TPI)
16541
Figure 46. Programmer System
To accomodate the application program and the associated hardware option configuration, the T48C510 is
equipped with 2 on-chip EEPROM memory blocks.
These are written via a 6-signal Target Programmer Interface (TPI), comprising of 2 power lines (VDD and VSS),
a Programm Mode signal (PM) and 3 data lines which are
multiplexed onto 3 of the T48C510 functional pins –
BP00, BP01 and BP02 (see figure 47). For setting up the
required hardware options and downloading these along
with the application program into the T48C510, the customer can be supplied with a dedicated PC based
programmer software operating under Windows95/98 or
NT and an In Circuit Programmer unit (ICP). The ICP is
connected to the PC via a standard PC serial interface port
and to the target device or application board (for in system programming) via the TPI flat band cable.
Table 25 Target programmer interface signals
TPI
Connector
Pin
Pin Name
1
PM
2
T48C510 Function
The Programmer software requires only the customer’s
binary *.hex file which is generated by the MARC4 program compiler and also provides the primary data base for
emulation. This is displayed on the screen as an editable
hexadecimal memory map. Contents of an already programmed device can be read back and displayed an the
same hex. form provided that the device’s “Read Lock”
has not been set. A “Read Lock” Protected device, if read
will appear to be full of F hex .
Hardware Configuration
All hardware configurations are set up within the software’s intuitive user interface by selecting the required
options from the masks provided. The available configurable hardware options are similar to those of the
M44C510E (see “Hardware Options” section). These effect primarily port configurations, watchdog and coded
reset settings. The port driver strengths, although mask
programmable in the M44C510E are not configurable in
the MTP – all output drivers being internally “hardwired”
to the default “standard drive” strength.
Read Lock Protection
The programmer software encorporates a so called “Read
Lock” which can be set by the user. This is provided for
customer security purposes and inhibits the reading of the
customer ’s Application Program by unauthorized persons. If set, the “Read Lock” sets a hardware key in the
MTP EEPROM which disables reading of the Program/
Configuration data. It should be noted that this is a “Read
Lock” and not a “Write Lock”, so even if the lock is set,
it is still possible to overwrite the customer data with new
program code.
Programming Mode Input
In-System Programming
VDD
+5 volt Supply
3
BP02
Port02 (Clock) Input
4
BP01
Port01 (Data ) Input
5
BP00
Port00 (Data ) Output
6
VSS
Ground Supply
7
n/c
not connected
8
n/c
not connected
9
n/c
not connected
10
n/c
not connected
For “in-system programming”, the application circuit
board must be fitted with a 10-pin male connector to accomodate the TPI connector. To ensure conflict-free access
to the target T48C510 TPI related Pins (BP00, BP01,
BP02 and PM) it is recommended that these are equipped
with jumpers (J5, J4, J3 and J1) to avoid signal contention
with other on board drivers sources. ( see figure 47). However, if these can be overdriven, or if the Port 0 is not used
in the application, then the jumpers can be omitted or replaced by isolating resistors. Prior to connecting the TPI,
all other application power supply sources should be disconnected from the application circuit board. Should
Rev. A2, 26-Feb-01
49 (61)
Preliminary Information
T48C510
other on board components either present an excessive
power supply load or be unable to withstand the ICP
5-Volt supply voltage, then the VDD power line should
also be jumpered (J2).
During the programming operation all ports are set into
input mode, with the previously programmed pullup/pulldowns transitors deactivated.
In normal operational mode, the PM pin is strapped to
ground and the Port 0 reverts to a port function as described in section 2.2.1.
1
2
3
4
5
9
10
VSS
n.c.
n.c.
n.c.
1
VSS
2
BP53
3
5
BP52
BP51
BP50
6
VDD
7
BP43
8
10
BP42
BP41
BP40
11
BP03
n.c.
Programmer interface
4
J2
*
9
Application: BP00
BP01
BP02 VDD
J3
J4
J5
*
*
*
BP70
BP71
BP72
43
BP73
PM
SCLIN
40
44
42
41
BP61
BP60
38
BPB3
36
BPB2
BPB1
34
35
33
32
AVDD
OSCIN
30
OSCOUT
28
NRST
BPA0
27
BP13
20
BP12
BPA1
25
21
BP11
BPA2
24
22
BP10
BPA3
23
BP01
14
BP00
15
17
TIM1
BPC1
TE
18
BPC0
19
VSS
37
BPB0
BP02
J1
*
39
BPC3
BPC2
12
13
16
*Optional jumpers
T48C510
6
7
8
31
29
26
Figure 47. In-system programming
2.8
Noise Considerations
When designing the microcontroller based application,
several factors should be taken into consideration to
increase noise immunity and reduce electromagnetic
emission (EME). Many such potential problems can be
avoided by careful layout of the printed circuit board
(PCB). The PCB contains many parasitic components
which at first sight are not apparent. PCB tracks can act
as antennas or as coupling capacitors. Long stretches of
parallel tracks and long high frequency signal lines
should thus be avoided wherever possible to minimise the
chance of picking up or transmitting unwanted signals.
2.8.1
Noise Immunity
The following guidelines will increase system noise immunity:
Unconnected inputs should not be left open. If port
pins are not required then it is recommended to set
pullup or pulldown option on these pins.
Special care should be taken when laying out the PCB
that interrupt, reset and clock signal lines are kept
short and are carefully shielded or have sufficient
spacing from other on board noise generating sources.
A quartz crystal should always be directly located
immediately next to the microcontroller crystal
oscillator terminals (OSCIN and OSCOUT), the
connections being always very short. This avoids not
only signal coupling onto the clock source but can also
reduces EME.
50 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
PCB’s should where economically possible be
equipped with adequate ground planes.
The microcontroller power supply should be
decoupled with an electrolytic capacitance (approx.
10 F) in parallel with a ceramic capacitance
(approx.100 nF) situated as close to the microcontroller device as possible.
2.8.2
Electromagnetic Emission
Electromagnetic emmision is caused by rapidly changing
electrical current (dI/dt) in long antenna like connection
lines and cables. This can result in electrical interference
on other telecommunication devices. These current
spikes are more often than not present in the system power
supply lines and driver signal lines.
The following guide will help to reduce EME:
3
3.1
Keep the length of PCB current switching signal
tracks to a minimum..
Adopt a PCB star power routing system connected at
one point.
Many of the microcontroller port outputs can be configured with several drive strengths. This means that
a high drive output will switch a signal faster than for
example standard drive output. The resulting change
in current in the signal and power lines will also increase, causing an increase in EME. So wherever
speed and drive current is not necessary the ports
should be configured with the lowest drive possible.
If possible, write the application program to avoid
multiple outputs switching at any instant.
Cables can be equipped with ferrite rings to slow current spikes or the system can be encased in a grounded
conducting casing.
Electrical Characteristics
Absolute Maximum Ratings
Voltages are given relative to VSS .
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Parameters
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to + 7.0
V
Input voltage (on any pin)
VIN
VSS –0.3 VIN VDD +0.3
V
Output short circuit duration
tshort
indefinite
s
Operating temperature range
Tamb
–40 to +85
°C
Storage temperature range
Tstg
–65 to +150
°C
RthJA
110
K/W
Tsld
260
°C
Thermal resistance (SSO44)
Soldering temperature (t ≤ 10 s)
Stresses greater than those listed under absolute
maximum ratings may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at any condition above those
indicated in the operational section of these specification
is not implied. Exposure to absolute maximum rating
condition for an extended period may affect device
3.2
reliability. All inputs and outputs are protected against
high electrostatic voltages (4kV, HBM) or electric fields.
However, precautions to minimize the build-up of
electrostatic charges during handling are recommended.
Reliability of operation is enhanced if unused inputs are
connected to an appropriate logic voltage level (e.g.
VDD).
DC Operating Characteristics
Supply voltage VDD = 5 V, VSS = 0 V, Tamb = –40 to 85°C unless otherwise specified.
Typical values relate to VDD = 5 V, Tamb = 25°C and are for reference only.
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Parameters
Test Conditions / Pins
Symbol
Min.
VDD
2.2
Typ.
Max.
Unit
6.2
V
500
A
Power supply
Supply voltage
Active current
CPU running TestROM
@SYSCL_iRC3
IDD
Rev. A2, 26-Feb-01
200
51 (61)
Preliminary Information
T48C510
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Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Quotient IDD/SYSCL_iR3
CPU running TestROM
@SYSCL_iRC3
IDDQ
0.25
0.5
µA/kHz
Halt current
CPU in sleep mode,
NSTOP = 0
IHalt
0.1
0.5
A
1.0
1.5
V
Power-on reset threshold voltage
POR threshold voltage
VPOR
0.8
Schmitt-trigger input voltage: (all inputs except Port 5, 7 and C)
Negative-going threshold
voltage
VDD = 2.4 to 6.2 V
VT–
VSS
0.4×VDD
V
Positive-going threshold
voltage
VDD = 2.4 to 6.2 V
VT+
0.55×
VDD
VDD
V
Hysteresis (VT+ – VT–)
VDD = 2.4 to 6.2 V
VH
0.1×VDD
Input Pins: NRST and TE
Input voltage LOW
VDD = 2.4 to 6.2 V
VIL
VSS
0.2 VDD
V
Input voltage HIGH
VDD = 2.4 to 6.2 V
VIH
0.8 VDD
VDD
V
IIL
–1.0
–5
–1.5
–10
–3.0
–18
µA
µA
IIH
1
1.4
2
mA
Input NRST with pull-up resistor
Input LOW current
VDD = 2.4 V, VIL= VSS
VDD = 5.0 V
Input TE with pull-down resistor
Input HIGH current
VDD = 5.0 V
All Bidirectional Ports and TIM1
Input voltage LOW
VDD = 2.4 to 6.2 V
VIL
VSS
0.2 VDD
V
Input voltage HIGH
VDD = 2.4 to 6.2 V
VIH
0.8 VDD
VDD
V
Dynamic input LOW current (pull-up)
VDD = 2.4 V, VIL= VSS
VDD = 5.0 V
IIL
–1.0
–5
–1.5
–10
–3.0
–18
µA
µA
Dynamic input HIGH current (pull-down)
VDD = 2.4 V, VIH = VDD
VDD = 5.0 V
IIH
1.0
5
1.5
10
2.5
18
µA
µA
Output LOW current
VDD = 2.4 V
VOL = 0.2*VDD
VDD = 5.0 V
IOL
1
2
4
mA
6
9
13
mA
VDD = 2.4 V
VOH = 0.8*VDD
VDD = 5.0 V
IOH
–1
–2
–4
mA
–6
–8
–13
mA
Output HIGH current
Bidirectional Port BP4, BP5, BP7, BPA, BPB and BPC
Input LOW current
Static pull-up (30 k)
VDD = 2.4 V
VDD = 5.0 V
IIL
IIL
–15
–100
–25
–150
–45
–220
µA
µA
Input HIGH current
static pull-down (30 k)
VDD = 2.4 V
VDD = 5.0 V
IIH
IIH
15
100
25
150
45
220
µA
µA
Bidirectional Port BP60 and BR61
Input LOW current
static pull-up (4 k)
VDD = 2.4 V
VDD = 5.0 V
IIL
IIL
–0.2
–1
–0.3
–1.35
–0.5
–2
mA
mA
Input HIGH current
static pull-down (4 k)
VDD = 2.4 V, VIL = VSS
VDD = 5.0 V
IIH
IIH
0.15
1
0.25
1.4
0.5
2
mA
mA
Note: The total sum of all port static output currents must not exceed 100 mA.
The sum of all port currents switched at any instant (dI/ dt) must not exceed 30 mA.
52 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
3.3
AC Characteristics
Supply voltage VDD = 2.4 to 6.2 V, VSS = 0 V, Tamb = –40 to 85°C unless otherwise specified.
Typical values relate to VDD = 5 V, Tamb = 25°C and are for reference only.
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ÁÁÁÁ
ÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
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ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Reset timing
Power-on reset delay
VDD u VPOR
tPOR
80
ms
tNRST
4
µs
Int. request LOW time
tIRL
50
ns
Int. request HIGH time
tIRH
50
ns
NRST input LOW time
Interrupt request input timing
Internal RC oscillator (for additional characteristics see figures 55 to 57)
Standby current of iRC0
CPU in SLEEP mode,
SC = 0011b, CM = 1100b
IiRC0
SYSCL_iRC0
CPU active,
SC = 0011b, CM = 1100b
fSYSCL
Standby current of iRC1
CPU in SLEEP mode,
SC = 0111b, CM = 1101b
IiRC1
SYSCL_iRC1
CPU active,
SC = 0111b, CM = 1101b
fSYSCL
Standby current of iRC2
CPU in SLEEP mode,
SC = 1011b, CM = 1110b
IiRC2
SYSCL_iRC2
CPU active,
SC = 1011b, CM = 1110b
fSYSCL
Standby current of iRC3
CPU in SLEEP mode,
SC = 1111b, CM = 1111b
IiRC3
SYSCL_iRC3
CPU active,
SC = 1111b, CM = 1111b
fSYSCL
Stability
VDD = 5 V " 20 %
3.5
1.9
1.4
0.60
300
500
A
7.0
10.5
MHz
150
250
A
3.0
4.5
MHz
100
150
A
2.0
3.0
MHz
40
70
A
0.80
1.3
MHz
”5
%
125
A
df/f0
System clock crystal/ceramic oscillator (for additional characteristics see figures 49)
Standby current
CPU in SLEEP mode,
4-MHz crystal active
Ixtal
Start-up time
VDD = 2.4 V
tstartup
8
10
ms
Stability
VDD = 3 V to 5.5 V
df/f0
0.3
0.5
ppm
125
A
2.2
MHz
”10
%
RC oscillator – external resistor (for additional characteristics see figures 52 to 54)
Standby current
CPU in SLEEP mode,
Rext = 150 k (" Frequency
CPU active, Rext = 150 k
Stability
VDD = 2.4 V to 5.5 V
IxRC
fSYSCL
1.8
df/f0
Rev. A2, 26-Feb-01
2.0
53 (61)
Preliminary Information
T48C510
AC Characteristics (continued)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁ
ÁÁÁÁ
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ÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Parameters
Test Conditions / Pins
32-kHz crystal oscillator
Active current
CPU active/running
HALT current
CPU in SLEEP mode
Start-up time
VDD = 2.4 V
Stability
AVDD = 100 mV
External clock input at SCLIN, TIM1 and T0IN
SCLIN input clock
CPU active, VDD > 2.4 V
fSCLIN = 2 fSYSCL
rise/fall time < 50 ns,
see figure 47
TIM1, T0IN input frequ.
rise/fall time < 30 ns
EEPROM program/ configuration memory
Number of programming
cycles
Symbol
Min.
Typ.
IDD32k
IHALTx
tstartup
df/f0
Max.
Unit
0.1
10
1.5
1.5
0.3
A
A
s
ppm
4
8
MHz
10
MHz
1.0
fSYSCL
fIN
n
1000
Cycles
Crystal Characteristics
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁ
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ÁÁÁÁ
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ÁÁÁÁÁÁÁÁ
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ÁÁÁÁ
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ÁÁÁÁ
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ÁÁÁÁ
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ÁÁÁÁ
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Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
32-kHz crystal
Crystal frequency
fX
32.768
kHz
Series resistance
RS
30
Static capacitance
C0
1.5
pF
Dynamic capacitance
C1
3
fF
Load capacitance
CL
8
10
12.5
pF
Crystal frequency
fX
1.5
4
8
MHz
Series resistance
RS
30
50
Static capacitance
C0
2
4.5
pF
C1
3
15
fF
50
k
System clock crystal
Dynamic capacitance
100.0000
10.0000
OSCIN
L
C1
fSYSCL ( MHz )
Equivalent
circuit
fSYSCLmax
OSCOUT
RS
1.0000
0.1000
fSYSCLmin
0.0100
C0
0.0010
0
1
2
3
4
5
6
VDD ( V )
Figure 48. Crystal equivalent circuit
Figure 49. Worst case minimum/ maximum system frequency
(using external RC or crystal oscillator)
54 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
10000.00
DD
100.00
VDD = 5 V
Tamb =
25°C
100% active
fSYSCL ( kHz )
1000.00
10000
VDD = 3
V
Tamb =
25°C
Standby
10.00
1.00
1000
Halt
0.10
0.01
10
100
1000
fSYSCL ( kHz )
100
10
10000
Figure 50. IDD = f (fSYSCL)
6000
VDD = 5 V
Tamb =
25°C
Rext = 47 k
5000
100% active
100.0
fSYSCL ( kHz )
DD
1000
Figure 53. fSYSCL = f (Rext)
10000.0
1000.0
100
Rext ( k )
Standby
10.0
1.0
Tamb =
25°C
4000
3000
Rext = 150 k
2000
1000
Halt
Rext = 477 k
0.1
10
0
100
1000
fSYSCL ( kHz )
10000
1.5
Figure 51. IDD = f (fSYSCL)
2.5
3.5
4.5
VDD ( V )
7000
Rext = 150 k
fiRC0
6000
2150
Tamb =
25°C
5000
2100
fSYSCL ( kHz )
fSYSCL ( kHz )
VDD = 5 V
VDD = 3 V
2000
4000
fiRC1
3000
fiRC2
2000
1950
1900
–40
6.5
Figure 54. fSYSCL = f (VDD, Rext)
2200
2050
5.5
fiRC3
1000
0
–20
16512
0
20
40
60
Tamb ( C )
80
Figure 52. fSYSCL = f (Tamb); external RC
100
1.5
2.5
3.5
4.5
VDD ( V )
5.5
6.5
Figure 55. fSYSCL = f (VDD); internal RC
Rev. A2, 26-Feb-01
55 (61)
Preliminary Information
T48C510
9000
14
VDD = 3 V
8000
VDD = 3 V
12
10
fiRC3
6000
IOL ( mA)
fSYSCL ( kHz )
7000
5000
4000
fiRC2
3000
fiRC1
2000
6
4
fiRC0
2
1000
0
–40
8
0
–20
0
16514
20
40
60
Tamb ( °C )
80
100
0.0
1.5
2.0
VOL ( V )
2.5
3.0
Figure 59. Typical low output driver
35
VDD = 5 V
9000
1.0
16516
Figure 56. fSYSCL = f (Tamb)
10000
0.5
VDD = 5 V
30
25
7000
fiRC3
6000
IOL ( mA)
fSYSCL ( kHz )
8000
5000
4000
20
15
fiRC2
3000
fiRC1
10
2000
fiRC0
1000
0
–40
5
0
–20
16515
0
20
40
60
Tamb ( °C )
80
100
0
1
16517
Figure 57. fSYSCL = f (Tamb)
0
4
5
VDD = 5 V
VDD = 3 V
–5
–2
–10
IOH ( mA )
–4
IOH ( mA )
3
VOL ( V )
Figure 60. Typical low output driver
0
–6
–8
–15
–20
–25
–10
–30
–12
–35
0.0
16518
2
0.5
1.0
1.5
2.0
VDD–VOH ( V )
2.5
Figure 58. Typical high output driver
3.0
0
1
16519
2
3
VDD–VOH ( V )
4
5
Figure 61. Typical high output driver
56 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
4
Device Information
4.1
Pad Layout
NRST BPA1
BPA3
OSCOUT BPA0
BPA2
12
OSCIN
AVDD
11
BPC2
9
BPC3
8
BPB0
7
BPB1
6
BPB2
5
BPB3
4
BP60
3
BP61
SCLIN
2
13 14
15
16
BP13
TE
BP1
BP10 1
BP12
BPC0
17
18
19
20
21
22
10
Die size: 2.99 x 4.30 mm
23
24
BPC1
25
TIM1
26
BP00
BP01
27
T48C510
28
29
30
BP02
BP03
BP40
31
BP41
32
BP42
33
BP43
34
VDD
Standard pad size:
96 x 96 m
Pad size (VSS):
246 x 96 m
Thickness:
480 ± 25 m
( 19 ± 1 mil )
Mask/chip ID
1
44
43
42
40
41
BP72
PM
BP73
39
BP70
BP71
VSS
38
37
36
35
BP51
BP53
BP50
BP52
Figure 62. Pad layout
Table 26 Pad coordinates
Pad No.
Name
X-Coord.
Y-Coord
Pad No.
Name
X-Coord.
Y-Coord.
1
2
SCLIN
BP61
113.80
113.80
353.95
503.95
23
TE
3861.80
2678.70
24
BPC1
3939.70
2374.60
3
BP60
113.80
744.40
25
TIM1
3939.70
2134.15
4
BPB3
113.80
984.85
26
BP00
3939.70
1744.20
5
BPB2
113.80
1225.30
27
BP01
3939.70
1594.20
6
BPB1
113.80
1465.75
28
BP02
3939.70
1444.20
7
BPB0
113.80
1706.20
29
BP03
3939.70
1294.20
8
BPC3
113.80
1946.65
30
BP40
3939.70
1144.20
9
BPC2
113.80
2187.10
31
BP41
3939.70
903.75
10
AVDD
113.80
2426.65
32
BP42
3939.70
663.30
11
OSCIN
113.80
2576.65
33
BP43
3939.70
422.85
12
OSCOUT
421.80
2678.70
34
VDD
3939.70
147.90
13
NRST
571.80
2678.70
35
BP50
3590.95
146.45
14
BPA0
721.80
2678.70
36
BP51
3350.50
146.45
15
BPA1
962.25
2678.70
37
BP52
3110.05
146.45
16
BPA2
1202.70
2678.70
38
BP53
2869.60
146.45
17
BPA3
1443.15
2678.70
39
VSS
2474.15
146.45
18
BP10
2659.55
2678.70
40
BP70
1431.05
146.45
19
BP11
2900.00
2678.70
41
BP71
1190.60
146.45
20
BP12
3140.45
2678.70
42
BP72
950.15
146.45
21
BP13
3380.90
2678.70
43
BP73
709.70
146.45
22
BPC0
3621.35
2678.70
44
VSS
469.25
146.45
Rev. A2, 26-Feb-01
57 (61)
Preliminary Information
BP70
BP53
2
43
BP71
BP52
3
42
BP72
BP51
4
41
BP73
BP50
5
40
VSS
VDD
6
39
BP43
7
38
SCLIN
BP61 [INTy]
BP42
8
37
BP60 [INTx]
BP41
9
36
BPB3
BP40
10
35
BPB2
BP03
11
34
BPB1
BP02
12
33
BPB0
BP01
13
32
BPC3
BP00
technical drawings
according to DIN
specifications
9.15
8.65
7.50
7.30
0.25
13040
Rev. A2, 26-Feb-01
10.50
10.20
14
31
BPC2
TIM1 15
30
AVDD
BPC1 16
17
TE
29
OscIn
28
OscOut
BPC0
18
27
NRST
BP13
19
26
BPA0
BP12
20
25
BPA1
BP11
21
24
BPA2
BP10
22
23
BPA3
Packaging
44
T48C510
2.35
0.25
0.10
Figure 63. Pin connections SSO44-package
18.05
17.80
16.8
23
22
1
T48C510
4.2
Package SSO44
Dimensions in mm
0.3
0.8
44
1
58 (61)
Preliminary Information
VSS
T48C510
5
Hardware Options
The following list shows all the T48C510 hardware options that can be programmed into the configuration EEPROM.
SPD –> strong static pull-down, SPU –> strong static pull-up
Port 0 Output
Standard drive
BP00 CMOS
Pull-up
BP01 CMOS
Pull-up
BP02 CMOS
Pull-up
BP03 CMOS
Pull-up
Port 1 Output
BP10 Standard drive
CMOS
Open drain [N] Open drain [P]
Pull-up
Pull-down
BP11 CMOS
Open drain [N] Open drain [P]
Pull-up
Pull-down
BP12 CMOS
Open drain [N] Open drain [P]
Pull-up
Pull-down
BP13 CMOS
Open drain [N] Open drain [P]
Pull-up
Pull-down
Port 4 Output
BP40 Standard drive
CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
BP41 CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
BP42 CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
BP43 CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
Port 5 Output
BP50 Standard drive
CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
BP51 CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
BP52 CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
BP53 CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
Port 7 Output
BP70 Standard drive
CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
BP71 CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
BP72 CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
BP73 CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
Port 6 Output
BP60 Standard drive
CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (4 k)
SPD (4 k)
BP61 CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (4 k)
SPD (4 k)
Rev. A2, 26-Feb-01
59 (61)
Preliminary Information
T48C510
Port A Output
Standard
BPA0 CMOS
Open drain [N]
Open drain [P]
Drive
Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
Port C Output
Standard
BPC0 CMOS
Open drain [N]
Open drain [P]
Drive
Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
BPA1 CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
BPC1 CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
BPA2 CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
BPC2 CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
BPA3 CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
BPC3 CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
Port B Output Standard
BPB0 CMOS
Open drain [N]
Open drain [P]
BPB1 Drive
Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
BPB2 CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
BPB3 CMOS
Open drain [N] Open drain [P] Pull-up
Pull-down
SPU (30 k)
SPD (30 k)
BPA-Reset
Watchdog
No
BPA0 & BPA1 = low
BPA0 & BPA1 & BPA2 = low
BPA0 & BPA1 & BPA2 & BPA3 = low
BPA0 & BPA1 = high
BPA0 & BPA1 & BPA2 = high
BPA0 & BPA1 & BPA2 & BPA3 = high
1/
2
s
Disabled
1s
2s
OSCIN
No integrated capacitance
OSCOUT
No intergrated capacitance
TIM1 Output Standard
Drive
CMOS
Open drain [N] Pull-up
Open drain [P] Pull-down
60 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
Ozone Depleting Substances Policy Statement
It is the policy of Atmel Germany GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems
with respect to their impact on the health and safety of our employees and the public, as well as their impact on
the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as
ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid
their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these
substances.
Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed
in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.
Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances
and do not contain such substances.
10.
We reserve the right to make changes to improve technical design and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer
application by the customer. Should the buyer use Atmel Wireless & Microcontrollers products for any unintended
or unauthorized application, the buyer shall indemnify Atmel Wireless & Microcontrollers against all claims,
costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death
associated with such unintended or unauthorized use.
Data sheets can also be retrieved from the Internet:
http://www.atmel–wm.com
Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
Rev. A2, 26-Feb-01
61 (61)
Preliminary Information