ONSEMI NTGS4141NT1G

NTGS4141N
Power MOSFET
30 V, 7.0 A, Single N−Channel, TSOP−6
Features
• Low RDS(on)
• Low Gate Charge
• Pb−Free Package is Available
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Applications
V(BR)DSS
• Load Switch
• Notebook PC
• Desktop PC
ID MAX
RDS(on) TYP
21.5 mW @ 10 V
7.0 A
30 V
30 mW @ 4.5 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current (Note 1)
Power Dissipation
(Note 1)
Value
Unit
VDSS
30
V
VGS
±20
V
ID
5.0
A
Steady
State
TA = 25°C
TA = 85°C
3.6
t ≤ 10 s
TA = 25°C
7.0
Steady
State
TA = 25°C
PD
Steady
State
Power Dissipation
(Note 2)
Gate 3
W
1.0
2.0
TA = 25°C
ID
TA = 85°C
TA = 25°C
Pulsed Drain Current
Drain 1 2 5 6
Source 4
t ≤ 10 s
Continuous Drain
Current (Note 2)
N−Channel
Symbol
tp = 10 ms
PD
0.5
W
21
A
TJ,
TSTG
−55 to
150
°C
IS
2.0
A
EAS
54
mJ
TL
260
°C
Rating
Symbol
Max
Unit
Junction−to−Ambient – Steady State (Note 1)
RθJA
125
°C/W
Junction−to−Ambient – t ≤ 10 s (Note 1)
RθJA
62.5
Junction−to−Ambient – Steady State (Note 2)
RθJA
248
Source Current (Body Diode)
Single Pulse Drain−to−Source Avalanche Energy
(VDD = 30 V, IL = 10.4 A, VGS = 10 V,
L = 1.0 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TSOP−6
CASE 318G
STYLE 1
2.5
IDM
Operating Junction and Storage Temperature
MARKING
DIAGRAM
A
3.5
1
S4 MG
G
S4
= Device Code
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN ASSIGNMENT
Drain Drain Source
6 5 4
THERMAL RESISTANCE RATINGS
1
2 3
Drain Drain Gate
ORDERING INFORMATION
1. Surface−mounted on FR4 board using 1 inch sq pad size
(Cu area = 1.127 in sq [1 oz] including traces).
2. Surface−mounted on FR4 board using the minimum recommended pad size
(Cu area = 0.0773 in sq).
Device
NTGS4141NT1
NTGS4141NT1G
Package
Shipping †
TSOP−6
3000/Tape & Reel
TSOP−6
(Pb−Free)
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2006
February, 2006 − Rev. 1
1
Publication Order Number:
NTGS4141N/D
NTGS4141N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Characteristic
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
18.4
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25°C
1.0
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
±100
mA
nA
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
Forward Transconductance
RDS(on)
gFS
1.0
3.0
5.7
V
mV/°C
VGS = 10 V, ID = 7.0 A
21.5
25
mW
VGS = 4.5 V, ID = 6.0 A
30
35
VDS = 10 V, ID = 7.0 A
30
S
560
pF
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
75
Total Gate Charge
QG(TOT)
12
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
VGS = 0 V, f = 1.0 MHz,
VDS = 24 V
VGS = 10 V, VDS = 15 V,
ID = 7.0 A
115
nC
0.85
1.9
QGD
3.0
Total Gate Charge
QG(TOT)
6.0
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
3.0
RG
2.8
W
td(ON)
6.0
ns
Gate Resistance
VGS = 4.5 V, VDS = 15 V,
ID = 7.0 A
nC
0.8
1.85
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
tr
td(OFF)
VGS = 10 V, VDS = 24 V,
ID = 7.0 A, RG = 3.0 W
tf
15
18
4.0
DRAIN − SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
Reverse Recovery Time
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 2.0 A
TJ = 25°C
0.78
TJ = 125°C
0.63
15
VGS = 0 V
dIS/dt = 100 A/ms, IS = 2.0 A
QRR
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2
V
ns
9.0
6.0
8.0
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
1.0
nC
NTGS4141N
TYPICAL PERFORMANCE CURVES
10 V
6V
15
TJ = 25°C
VDS ≥ 10 V
3.5 V
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
15
4.5 V
10
3V
5
10
5
125°C
25°C
2.6 V
0
TJ = −55°C
0
0
4
2
6
10
8
1
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.05
TJ = 25°C
ID = 7 A
0.04
0.03
0.02
0.01
0
2
4
6
8
10
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.05
TJ = 25°C
0.04
0.03
VGS = 4.5 V
0.02
VGS = 10 V
0.01
0
0
5
10
15
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
10000
2.0
VGS = 0 V
ID = 7 A
VGS = 10 V
IDSS, LEAKAGE CURRENT (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
5
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
Figure 1. On−Region Characteristics
2
3
4
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
1.5
1.0
0.5
0
−50
1000
TJ = 150°C
100
TJ = 125°C
10
−25
0
25
50
75
100
125
150
0
TJ, JUNCTION TEMPERATURE (°C)
5
10
15
20
25
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
30
NTGS4141N
1200
C, CAPACITANCE (pF)
VDS = 0 V
1000
VGS, GATE−TO−SOURCE VOLTAGE (V)
TYPICAL PERFORMANCE CURVES
TJ = 25°C
VGS = 0 V
Ciss
800
Ciss
600
400 Crss
200
0
10
Coss
Crss
5
0
VGS
5
10
15
20
10
QT
8
VGS
6
4
QGS
ID = 7 A
VDD = 15 V
TJ = 25°C
2
0
0
25
2
VDS
Figure 7. Capacitance Variation
1000
12
IS, SOURCE CURRENT (AMPS)
7
VDD = 24 V
ID = 7 A
VGS = 10 V
td(off)
100
tf
tr
10
td(on)
VGS = 0 V
TJ = 25°C
6
5
4
3
2
1
0
1
10
RG, GATE RESISTANCE (OHMS)
100
0
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
t, TIME (ns)
4
6
8
10
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and
Drain−To−Source Voltage vs. Total Charge
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1
QGD
0.1 0.2
0.3 0.4
0.5 0.6 0.7 0.8
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage vs. Current
60
ID = 10.4 A
40
20
0
25
0.9
50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Avalanche Energy vs.
Starting Junction Temperature
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4
150
NTGS4141N
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE P
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
D
6
HE
1
5
4
2
3
E
b
DIM
A
A1
b
c
D
E
e
L
HE
q
e
q
c
A
0.05 (0.002)
L
A1
MIN
0.90
0.01
0.25
0.10
2.90
1.30
0.85
0.20
2.50
0°
MILLIMETERS
NOM
MAX
1.00
1.10
0.06
0.10
0.38
0.50
0.18
0.26
3.00
3.10
1.50
1.70
0.95
1.05
0.40
0.60
2.75
3.00
10°
−
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
SOLDERING FOOTPRINT*
2.4
0.094
1.9
0.075
MIN
0.035
0.001
0.010
0.004
0.114
0.051
0.034
0.008
0.099
0°
INCHES
NOM
0.039
0.002
0.014
0.007
0.118
0.059
0.037
0.016
0.108
−
MAX
0.043
0.004
0.020
0.010
0.122
0.067
0.041
0.024
0.118
10°
DRAIN
DRAIN
GATE
SOURCE
DRAIN
DRAIN
0.95
0.037
0.95
0.037
0.7
0.028
1.0
0.039
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTGS4141N/D