ONSEMI MC33680FTB

MC33680
Dual DC-DC Regulator for
Electronic Organizer
The MC33680 is a dual DC–DC regulator designed for electronic
organizer
applications.
Both
regulators
apply
Pulse–Frequency–Modulation (PFM). The main step–up regulator
output can be externally adjusted from 2.7V to 5V. An internal
synchronous rectifier is used to ensure high efficiency (achieve 87%).
The auxiliary regulator with a built–in power transistor can be
configured to produce a wide range of positive voltage (can be used
for LCD contrast voltage). This voltage can be adjusted from +5V to
+25V by an external potentiometer.
The MC33680 has been designed for battery powered hand–held
products. With the low start–up voltage from 1V and the low quiescent
current (typical 35 µA); the MC33680 is best suited to operate from 1
to 2 AA/ AAA cell. Moreover, supervisory functions such as low
battery detection, CPU Power–Good signal, and back–up battery
control, for lithium battery or supercap are also included in the chip.
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32
32–LEAD LQFP
FTB SUFFIX
CASE 873A
PIN CONNECTIONS &
DEVICE MARKING
NC
VAUXBASE
VAUXCHG
VAUXBDV
VAUXFBN
NC
VAUXFBP
VAUXEN
FEATURES:
• Low Input Voltage, 1V up
• Low Quiescent Current in Standby Mode: 35µA typical
• PFM and Synchronous Rectification to ensure high efficiency
(87% @60mA Load)
VAUXSW
VAUXEMR
LIBATIN
LIBATOUT
NC
VMAINGND
VMAINSW
VMAIN
• Adjustable Main Output: +2.7V to +5V
•
•
•
•
•
NC
DGND
LIBATCL
LIBATON
LOWBATB
PORB
DGND
LOWBATSEN
MC33680
FTB
AWLYYWW
VMAINFB
VBAT
VBAT
VDD
PDELAY
VREF
AGND
IREF
•
nominal 3.3V @ 100mA max, with 1.8V input
Auxiliary Output Voltage: +5V to +25V
+5V @ 25mA max, with 1.8V input
+25V @ 15mA max, with 1.8V input
Current Limit Protection
Power–Good Signal with Programmable Delay
Battery Low Detection
Lithium Battery or Supercap Back–up
32–Pin LQFP Package
1
(Top View)
APPLICATIONS:
• Digital Organizer and Dictionary
• Dual Output Power Supply (For MPU, Logic, Memory, LCD)
• Handheld Battery Powered Device (1–2 AA/AAA cell)
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2000
May, 2000 – Rev. 3
1
Package
Shipping
MC33680FTB
LQFP
1250 Tray / Drypack
MC33680FTBR2
LQFP
1800 / Tape & Reel
Publication Order Number:
MC33680/D
MC33680
Figure 1. Detailed Application Block Diagram
VBAT
CMAINb
100 pF
VBAT
+
CPOR
80 nF
RIref
480 kW
8
IREF 7
AGND
6
VREF
+
CVDD
20 mF
5
L1
33 mH
MBRA130LT1
RMAINb
PDELAY
4
VDD
VBAT 2
3
VBAT
1
VMAINFB
1000 kW
5
VBAT
300 kW
RLBa
ZLC
31
COMP3
LOBAT–
SEN
VMAINSW
9
32 VMAIN
900 kW
RLBb
+ve Edge Delay
senseFET
VDD
M2
for Max. ON Time
DGND
R
Q
S
Qb
CMAIN
100 mF
M1
+
10
PORB
Power–On
Reset
11
VMAINGND
DGND
30
VDD
1–SHOT
x2
28
LIBATIN
for Min. OFF Time
R
S
Q
DGND
ILIM
1.22 V
COMP1
L2
33 mH
VCOMP
AGND
Main Regulator
with Synchronous Rectifier
MBRA140T3
0.5 V
25
VAUXSW
+ve Edge Delay
LOWBATB
12
AGND
LIBATCL
for Max. ON Time
0.85 V,
1.1 V
LIBATON
13
27
VBAT
COMP2
Voltage
Reference
LIBATOUT
R
Q
S
Qb
senseBJT
CAUX
30 mF
Q1
VCOMP
Lithium
Battery
Backup
COMP1
VAUXEMR
ILIM
COMP2
14
26
1–SHOT
DGND
15
for Min. OFF Time
Voltage Reference
Current Bias
& Supervisory
17
VAUXEN
18
VAUXFBP
AGND
Auxiliary Regulator
20
VAUXFBN
2200 kW
RAUXb
21
VAUXBDV
200 kW
RAUXa
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2
VBAT
22
VAUXCHG
23
VAUXBASE
+
MC33680
TIMING DIAGRAMS
VBAT
VMAINreg
VMAINreg – 0.15 V
T
VMAIN
POR
+
ǒ Ǔ
1.22
0.5
C por
RIref
tPORC
PORB
VAUXEN
Figure 2. Startup Timing
VBAT
LOWBAT Threshold
LOWBATB
VMAIN
VMAINreg – 0.5 V
PORB
Figure 3. Power Down Timing
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3
MC33680
PIN FUNCTION DESCRIPTION
Pin
No.
Function
Type/Direction
1
VMAINFB
Analog / Input
2
VBAT
Power
Main battery supply
3
VBAT
Power
Main battery supply
4
VDD
Analog / Output
Connect to decoupling capacitor for internal logic supply
5
PDELAY
Analog / Input
Capacitor connection for defining Power–On signal delay
6
VREF
Analog / Output
7
AGND
Analog Ground
8
IREF
Analog / Input
Resistor connection for defining internal current bias and PDELAY current
9
LOWBATSEN
Analog / Input
Resistive network connection for defining low battery detect threshold
10
DGND
Digital Ground
11
PORB
CMOS / Output
Active LOW Power–On reset signal
12
LOWBATB
CMOS / Output
Active LOW low battery detect output
13
LIBATON
CMOS / Input
microprocessor control signal for Lithium battery backup switch, the switch is
ON when LIBATON=HIGH and LIBATCL=HIGH
14
LIBATCL
CMOS / Input
microprocessor control signal for Lithium battery backup switch, if it is HIGH,
the switch is controlled by LIBATON, otherwise, controlled by internal logic
15
DGND
Digital Ground
16
NC
17
VAUXEN
CMOS / Input
VAUX enable, Active high
18
VAUXFBP
Analog / Input
Feedback pin for VAUX
19
NC
20
VAUXFBN
Analog / Input
21
VAUXBDV
Power
22
VAUXCHG
Analog / Output
test pin
23
VAUXBASE
Analog / Output
test pin
24
NC
25
VAUXSW
Analog / Output
Collector output of the VAUX power BJT
26
VAUXEMR
Analog / Output
Emitter output of the VAUX power BJT
27
LIBATIN
Analog / Input
28
LIBATOUT
Analog / Output
29
NC
30
VMAINGND
Power Ground
Ground for VMAIN low side switch
31
VMAINSW
Analog / Input
VMAIN inductor connection
32
VMAIN
Analog / Output
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Description
Feedback pin for VMAIN
Bandgap Reference output voltage. Nominal voltage is 1.25V
no connection
no connection
Feedback pin for VAUX
VAUX BJT base drive circuit power supply
no connection
Lithium battery input for backup purposes
Lithium battery output
no connection
VMAIN output
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4
MC33680
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
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Parameter
Power Supply Voltage
Digital Pin Voltage
General Analog Pin Voltage
Pin VAUXSW to Pin VAUXEMR Voltage (Continuous)
Pin VMAINSW to Pin VMAIN Voltage (Continuous)
Operating Junction Temperature
Ambient Operating Temperature
Storage Temperature
Symbol
Min
Max
Unit
VBAT
Vdigital
Vanalog
VAUXCE
–0.3
–0.3
–0.3
–0.3
7.0
7.0
7.0
30
Vdc
Vdc
Vdc
Vdc
Vsyn
0.3
Vdc
Tj (max)
150
°C
Ta
0
70
°C
Tstg
– 50
150
°C
STATIC ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, VP = 1.8V, Iload = 0 mA, TA = 0 to 70°C unless
otherwise noted.)
Rating
Symbol
Min
Operating Supply Voltage1
VBAT
1.0
VMAIN output voltage
Vmain
3.1
Vmain_range
2.7
VMAIN output voltage range2
VMAIN output current3
VMAIN maximum switching frequency4
VMAIN peak coil static current limit
Typ
Max
3.3
3.5
V
5.0
V
I3.3_1.8
200
mA
Freqmax_VM
100
kHz
1.15
A
25
V
120
kHz
ILIM_VM
0.85
VAUX output voltage range
VAUX_range
5.0
VAUX maximum switching frequency
Freqmax_VL
VAUX peak coil static current limit
Quiescent Supply Current at Standby Mode5
Unit
V
1.0
ILIM_VL
1.0
A
Iqstandby
35
60
µA
Reference Voltage @ no load
Vrefno_load
1.16
1.22
1.28
V
Battery Low Detect lower hysteresis threshold6
VLOBAT_L
0.8
0.85
0.9
V
Battery Low Detect upper hysteresis threshold
VLOBAT_H
1.05
1.1
1.15
V
PDELAY Pin output charging current
IchgPDELAY
0.8
1.0
1.2
µA
PDELAY Pin voltage threshold
VthPDELAY
1.16
1.22
1.28
V
NOTE: 1. Output current capability is reduced with supply voltage due to decreased energy transfer. The supply voltage must not be higher than
VMAIN+0.6V to ensure boost operation. Max Start–up loading is typically 1V at 400 µA, 1.8V at 4.4 mA, and 2.2V at 88 mA.
NOTE: 2. Output voltage can be adjusted by external resistor to the VMAINFB pin.
NOTE: 3. At VBAT = 1.8V, output current capability increases with VBAT.
NOTE: 4. Only when current limit is not reached.
NOTE: 5. This is average current consumed by the IC from VDD, which is low–pass filtered from VMAIN, when only VMAIN is enabled and at no loading.
NOTE: 6. This is the minimum of ”LOWBATB” threshold for battery voltage, the threshold can be increased by external resistor divider from ”VBAT” to
”LOWBATSEN”.
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MC33680
DYNAMIC ELECTRICAL CHARACTERISTICS (Refer to TIMING DIAGRAMS, TA = 0 to 70°C unless otherwise noted.)
Rating
Symbol
Minimum PORB to Control delay
Unit
500
nS
90%
85%
80%
Vin = 3V
Vin = 1.8V
Vin = 1.5V
Vin = 1V
70%
85%
80%
Iout = 10mA
Iout = 60mA
Iout = 100mA
75%
70%
0
10
20
30
40
60
50
70
80
90
1
100
1.5
2
2.5
3
IOUT_MAIN, MAIN OUTPUT CURRENT (mA)
VIN, INPUT VOLTAGE (V)
Figure 6. Efficiency of VAUX versus Output
Current (VAUX = 25 V, L2 = 33 uH, Various VIN)
Figure 7. Efficiency of VAUX versus Input
Voltage (VAUX = 25 V, L2 = 33 uH, Various IOUT)
80%
Eff VAUX , EFFICIENCY OF VAUX (%)
80%
Eff VAUX , EFFICIENCY OF VAUX (%)
Max
Figure 5. Efficiency of VMAIN versus Input
Voltage (VMAIN = 3.3 V, L1 = 33 uH, Various IOUT)
Figure 4. Efficiency of VMAIN versus Output
Current (VMAIN = 3.3 V, L = 33 uH, Various VIN)
75%
Typ
tPORC
Eff VMAIN , EFFICIENCY OF VMAIN (%)
Eff VMAIN , EFFICIENCY OF VMAIN (%)
90%
Min
75%
70%
65%
60%
Vin = 3V
Vin = 1.8V
Vin = 1.5V
Vin = 1V
55%
75%
70%
65%
60%
Iout = 1mA
Iout = 5mA
Iout = 10mA
Iout = 15mA
55%
50%
50%
1
3
5
7
9
11
13
1
15
IOUT_AUX, AUX OUTPUT CURRENT (mA)
1.5
2
VIN, INPUT VOLTAGE (V)
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2.5
3
MC33680
Figure 8. Efficiency of VAUX versus Output
Current (VAUX = 20 V, L2 = 33 uH, Various VIN)
Figure 9. Efficiency of VAUX versus Input
Voltage (VAUX = 20 V, L2 = 33 uH, Various IOUT)
80%
Eff VAUX, EFFICIENCY OF VAUX (%)
Eff VAUX, EFFICIENCY OF VAUX (%)
80%
75%
70%
65%
Vin = 3V
Vin = 1.8V
Vin = 1.5V
Vin = 1V
60%
55%
50%
70%
65%
60%
Iout = 1mA
Iout = 5mA
Iout = 10mA
Iout = 15mA
55%
50%
1
3
5
7
9
11
13
1
15
1.5
2
2.5
3
IOUT_AUX, AUX OUTPUT CURRENT (mA)
VIN, INPUT VOLTAGE (V)
Figure 10. Efficiency of VAUX versus Output
Current (VAUX = 5 V, L2 = 82 uH, Various VIN)
Figure 11. Efficiency of VAUX versus Input
Voltage (VAUX = 5 V, L2 = 82 uH, Various IOUT)
85%
Eff VAUX, EFFICIENCY OF VAUX (%)
85%
Eff VAUX, EFFICIENCY OF VAUX (%)
75%
80%
75%
70%
65%
60%
Vin = 3V
Vin = 2.4V
Vin = 1.8V
Vin = 1.5V
Vin = 1V
55%
50%
45%
40%
80%
75%
Iout = 1V
Iout = 5V
Iout = 10V
Iout = 15V
Iout = 25V
70%
65%
50%
1
5
10
15
20
25
30
35
1
IOUT_AUX, AUX OUTPUT CURRENT (mA)
1.5
2
VIN, INPUT VOLTAGE (V)
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2.5
3
MC33680
Figure 12. VMAIN Output Ripple (Medium Load)
Figure 13. VMAIN Output Ripple (Heavy Load)
20 uS / div
10 uS / div
1: VMAIN = 3.3 V (50 mV/div, AC COUPLED)
2: Voltage at VMAINSW (1 V/div)
1: VMAIN = 3.3 V (50 mV/div, AC COUPLED)
2: Voltage at VMAINSW (1 V/div)
Figure 14. VAUX Output Ripple (Medium Load)
Figure 15. VAUX Output Ripple (Heavy Load)
20 uS / div
10 uS / div
1: VAUX = 20 V (50 mV/div, AC COUPLED)
2: Voltage at VAUXSW (10 V/div)
1: VAUX = 20 V (50 mV/div, AC COUPLED)
2: Voltage at VAUXSW (10 V/div)
Figure 16. VMAIN Startup and Power–Good Signal
Figure 17. VAUX Startup
50 mS / div
5 mS / div
1: VMAIN from 1 V to 3.3 V (1 V/div)
2: Voltage of PORB (2 V/div)
3: Voltage of ENABLE (2 V/div)
1: VAUX from 1.8 V to 20 V (5 V/div)
2: VAUXEN (2 V/div)
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8
MC33680
DETAILED OPERATING DESCRIPTION
General
Iref
The MC33680 is a dual DC–DC regulator designed for
electronic organizer applications. Both regulators apply
Pulse–Frequency–Modulation (PFM). The main boost
regulator output can be externally adjusted from 2.7V to 5V.
An internal synchronous rectifier is used to ensure high
efficiency (achieve 87%). The auxiliary regulator with a
built–in power transistor can be configured to produce a
wide range of positive voltage (can be used for LCD contrast
voltage). This voltage can be adjusted from +5V to +25V by
an external potentiometer.
The MC33680 has been designed for battery powered
hand–held products. With the low start–up voltage from 1V
and the low quiescent current (typical 35 µA), the MC33680
is best suited to operate from 1 to 2 AA/ AAA cell.
Moreover, supervisory functions such as low battery
detection, CPU Power–Good signal, and back–up battery
control, are also included in the chip. It makes the MC33680
the best one–chip power management solution for
applications such as electronic organizers and PDAs.
0.5
+ RIref
(A)
This bias current is used for all internal current bias as well
as setting VMAIN value. For the latter application, Iref is
doubled and fed as current sink at Pin 1. With external
resistor RMAINb tied from Pin1 to Pin32, a constant voltage
level shift is generated in between the two pins. In
close–loop operation, voltage at Pin 1 (i.e. Output feedback
voltage) is needed to be regulated at the internal reference
voltage level, 1.22V. Therefore, the delta voltage across Pin
1 and Pin 32 which can be adjusted by RMAINb determines
the Main Output voltage. If the feedback voltage drops
below 1.22V, internal comparator sets switching cycle to
start. So, VMAIN can be calculated as follows.
VMAIN
+ 1.22 ) RMAINb
RIref
(V)
From the above equation, although VMAIN can be
adjusted by RMAINb and RIref ratio, for setting VMAIN, it
is suggested, by changing RMAINb value with RIref kept at
480K. Since changing RIref will alter internal bias current
which will affect timing functions of Max ON time (TON1 )
and Min OFF time (TOFF1 ). Their relationships are as
follows;
Pulse Frequency Modulation (PFM)
Both regulators apply PFM. With this switching scheme,
every cycle is started as the feedback voltage is lower than
the internal reference. This is normally performed by
internal comparator. As cycle starts, Low–Side switch (i.e.
M1 in Figure 1) is turned ON for a fixed ON time duration
(namely, Ton) unless current limit comparator senses coil
current has reached its preset limit. In the latter case, M1 is
OFF instantly. So Ton is defined as the maximum ON time
of M1. When M1 is ON, coil current ramps up, so energy is
being stored inside the coil. At the moment just after M1 is
OFF, the Synchronous Rectifier (i.e. M2 in Figure 1) or any
rectification device (such as Schottky Diode of Auxiliary
Regulator) is turned ON to direct coil current to charge up
the output bulk capacitor. Provided that coil current limit is
not reached, every switching cycle delivers fixed amount of
energy to the bulk capacitor. For higher loading, a larger
amount of energy (Charge) is withdrawn from the bulk
capacitor, and a larger amount of Charge is then supplied to
the bulk capacitor to regulate output voltage. This implies
switching frequency is increased; and vice–versa.
+ 1.7
+ 6.4
T
OFF 1
T
ON 1
10 –11
10 –12
RIref (S)
RIref (S)
Continuous Conduction Mode and Discontinuous
Conduction Mode
In Figure 19, regulator is operating at Continuous
Conduction Mode. A switching cycle is started as the output
feedback voltage drops below internal voltage reference
VREF. At that instant, the coil current is not yet zero, and it
starts to ramp up for the next cycle. As the coil current ramps
up, loading makes the output voltage to decrease as the
energy supply path to the output bulk capacitor is
disconnected. After Ton elapses, M1 is OFF, M2 is ON,
energy is pumped to the bulk capacitor. Output voltage is
increased as excessive charge is pumped in, then it is
decreased after the coil current drops below the loading.
Notice the abrupt spike of output voltage is due to ESR of the
bulk capacitor. Feedback voltage can be resistor–divided
down or level–shift down from the output voltage. As this
feedback voltage drops below VREF, next switching cycle
starts.
Main Regulator
Figure 18 shows the simplified block diagram of Main
Regulator. Notice that precise bias current Iref is generated
by a VI converter and external resistor RIref, where
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9
MC33680
DETAILED OPERATING DESCRIPTION (Cont’d)
VBAT
CMAINb
100 pF
2 x Iref
1
L1
33uH
RMAINb
1000 kOhm
31
VMAINFB
VMAINSW
ZLC
COMP3
M2
VMAIN
x2
32
+ve Edge Delay
0.5 V
senseFET
VDD
for Max. ON Time
CMAIN
100 uF
Iref
IREF
R
Q
S
Qb
+
M1
8
RIref
480 kOhm
VCOMP
Voltage
Reference
1.22 V
VMAINGND
DGND
30
COMP1
VDD
1–SHOT
for Min. OFF Time
R
Q
S
DGND
ILIM
COMP2
AGND
Voltage Reference
& Current Bias
Main Regulator
with Synchronous Rectifier
AGND
Figure 18. Simplified Block Diagram of Main Regulator
In Figure 20, regulator is operating at Discontinuous
Conduction Mode, waveforms are similar to those of Figure
19. However, coil current drops to zero before next
switching cycle starts.
T
SW
Ipk
To estimate conduction mode, below equation can be
used.
Iroom
+ h2
TON
L
Vin 2
Vout
+
+
*
I
1
* ILOAD
1
ǒ Ǔ
T
ON
h Vin
Vout
ǒǓ
LOAD
*
T
ON
T
SW
(S);
) Vin2
T
ON
L
(A)
For Discontinuous Conduction mode, provided that
current limit is not reached,
where, η is efficiency, refer to Figure 4
T
SW
if Iroom > 0, the regulator is at Discontinuous Conduction
mode
if Iroom = 0, the regulator is at Critical Conduction mode
where coil current just drops to zero and next cycle starts.
if Iroom < 0, the regulator is at Continuous Conduction
mode
Ipk
For Continuous Conduction mode, provided that current
limit is not reached,
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10
+
@
ǒ
2
Vin T ON
Vout
2 L I
LOAD
h Vin
@ @
+ VinL @ TON
@ @ *1
(A)
Ǔ
(S);
MC33680
Cycle Starts
VREF
Feedback Voltage
tdl
M1 ON
M1 OFF
M1 ON
M1 OFF
M1 ON
M1 OFF
M2 ON
M2 OFF
M2 ON
M2 OFF
M2 ON
tdh
M2 OFF
Ipk
TON
Loading Current, ILOAD
TSW
Coil Current
VMAIN + 1 V
VMAIN
V@SW
0V
VMAIN Zoom–In
Figure 19. Waveforms of Continuous Conduction Mode
Cycle Starts
Feedback Voltage
VREF
tdl
M1 ON
M1 OFF
M1 ON
M1 OFF
M1 ON
tdh
M2 OFF
M2 OFF
Ipk
M2 OFF
TON
Loading Current, ILOAD
Coil Current
TSW
VMAIN + 1 V
VMAIN
VIN
V@SW
0V
VMAIN Zoom–In
Figure 20. Waveforms of Discontinuous Conduction Mode
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11
M1 OFF
MC33680
DETAILED OPERATING DESCRIPTION (Cont’d)
Synchronous Rectification
Therefore, determination on the offset voltage is essential
for optimum performance.
A Synchronous Rectifier is used in the main regulator to
enhance efficiency. Synchronous rectifier is normally
realized by powerFET with gate control circuitry which,
however, involved relative complicated timing concerns. In
Figure 19, as main switch M1 is being turned OFF, if the
synchronous switch M2 is just turned ON with M1 not being
completely turned OFF, current will be shunted from the
output bulk capacitor through M2 and M1 to ground. This
power loss lowers overall efficiency. So a certain amount of
dead time is introduced to make sure M1 is completely OFF
before M2 is being turned ON, this timing is indicated as tdh
in Figure 20.
When the main regulator is operating in continuous mode,
as M2 is being turned OFF, and M1 is just turned ON with
M2 not being completed OFF, the above mentioned situation
will occur. So dead time is introduced to make sure M2 is
completed OFF before M1 is being turned ON, this is
indicated as tdl in Figure 20.
When the main regulator is operating in discontinuous
mode, as coil current is dropped to zero, M2 is supposed to
be OFF. Fail to do so, reverse current will flow from the
output bulk capacitor through M2 and then the inductor to
the battery input. It causes damage to the battery. So
M2–voltage–drop sensing comparator (COMP3 of Figure
18) comes with fixed offset voltage to switch M2 OFF
before any reverse current builds up. However, if M2 is
switch OFF too early, large residue coil current flows
through the body diode of M2 and increases conduction loss.
Auxiliary Regulator
The Auxiliary Regulator is a boost regulator, applies PFM
scheme to enhance high efficiency and reduce quiescent
current. An internal voltage comparator (COMP1 of Figure
21) detects when the voltage of Pin VAUXFBN drops below
that of Pin VAUXFBP. The internal power BJT is then
switched ON for a fixed–ON–time (or until the internal
current limit is reached), and coil current is allowed to build
up. As the BJT is switched OFF, coil current will flow
through the external Schottky diode to charge up the bulk
capacitor. After a fixed–mimimum–OFF time elapses, next
switching cycle will start if the output of the voltage
comparator is HIGH. Refer to Figure 21, the VAUX
regulation level is determined by the equation as follows,
VAUX
+
VAUXFBP
ǒ Ǔ
@ 1 ) RRAUXb
(V)
AUXa
Where Max ON Time, TON2, and Min OFF Time, TOFF2
can be determined by the following equations.
+ 1.7
+ 2.1
T
ON 2
T
OFF 2
10 –11 RIref (S)
10 –12 RIref (S)
As the Auxiliary Regulator control scheme is the same as
the Main Regulator, equations for conduction mode, Tsw
and Ipk can also be applied, However, h to be used for
calculation is referred to Figures 6, 8, or 10.
VBAT
RAUXa
200 kOhm
VREF
L2
33uH
RAUXb
2200 kOhm
VBAT
VAUXFBP
18
VAUXFBN
20
VAUXBDV
VAUXSW
25
21
+ve Edge Delay
senseBJT
for Max. ON Time
R
Q
S
Qb
+
CAUX
33 uF
Q1
VAUXEMR
VCOMP
26
COMP1
1–SHOT
for Min. OFF Time
ILIM
COMP2
Auxiliary Regulator
AGND
Figure 21. Simplified Block Diagram of Auxiliary Regulator
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12
MC33680
DETAILED OPERATING DESCRIPTION (Cont’d)
Current Limit for Both regulators
V
LOBAThigh
From Figure 18 and Figure 21, sense devices (senseFET
or senseBJT) are applied to sample coil current as the
low–side switch is ON. With that sample current flowing
through a sense resistor, sense–voltage is developed.
Threshold detector (COMP2 in both Figures) detects
whether the sense–voltage is higher than preset level. If it
happens, detector output reset the flip–flop to switch OFF
low–side switch, and the switch can only be ON as next
cycle starts.
V
LOBATlow
ǒ Ǔ
1.22
0.5
C por
1
) RRLBa
(V)
) RRLBa
(V)
LBb
1
LBb
The backup conduction path which is provided by an
internal power switch (typ. 13 Ohm) can be controlled by
internal logic or microprocessor.
If LIBATCL is LOW, the switch, which is then controlled
by internal logic, is ON when the battery is removed and
VMAIN is dropped below LIBATIN by more than 100mV,
and returns OFF when the battery is plugged back in.
If LIBATCL is HIGH, the switch is controlled by
microprocessor through LIBATON. The truth table is shown
in Figure 22.
During the startup period (see Figure 2), the internal
startup circuitry is enabled to pump up VMAIN to a certain
voltage level, which is the user–defined VMAIN output
level minus an offset of 0.15V. The internal Power–Good
signal is then enabled to activate the main regulator and
conditionally the auxiliary regulator. Meanwhile, the startup
circuitry will be shut down. The Power–Good signal block
also starts to charge up the external capacitor tied from Pin
PDELAY to ground with precise constant current. As the Pin
PDELAY’s voltage reaches an internal set threshold, Pin
PORB will go HIGH to awake the microprocessor. This
delay is stated as follows;
+
+ 0.85
ǒ Ǔ
ǒ Ǔ
Lithium–Battery backup
Power–Good Signal
T
POR
+ 1.1
Efficiency and Output Ripple
For both regulators, when large values are used for
feedback resistors (> 50kOhm), stray capacitance of pin 1
(VMAINFB) and pin 20 (VAUXFBN) can add ”lag” to the
feedback response, destabilizing the regulator and creating
a larger ripple at the output. From Figure 1, ripple of Main
and AUX regulator can be reduced by capacitors in parallel
with RMAINb, RAUXa and RAUXb ranging from 100pF to
100nF respectively. Reducing the ripple is also with
improving efficiency, system designers are recommended to
do experiments on capacitance values based on the PCB
design.
RIref (S)
From Figure 3, if, by any chance, VMAIN is dropped
below the user–defined VMAIN output level minus 0.5V,
PORB will go LOW to indicate the OUTPUT LOW
situation. And, the IC will continue to function until the
VMAIN is dropped below 2V.
Bypass Capacitors
If the metal lead from battery to coils are long, its stray
resistance can put additional power loss to the system as AC
current is being conducted. In that case, bypass capacitors
should be placed closely to the coil, and connected from
VBAT to ground. This reduces AC component of coil current
passing through the long metal lead, thus minimizing that
portion of power loss.
Low–Battery–Detect
The Low–Battery–Detect block is actually a voltage
comparator. Pin LOWBAT is LOW, if the voltage of external
Pin LOWBATSEN is lower than 0.85V. The IC will neglect
this warning signal. Pin LOWBAT will become HIGH, if the
voltage of external Pin LOWBATSEN is recovered to more
than 1.1V. From Figure 1, with external resistors RLBa and
RLBb, thresholds of Low–Battery–Detect can be adjusted
based on the equations below.
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
LIBATCL
LIBATON
Action
0
X
The switch is ON when the battery is removed and VMAIN is dropped below LIBATIN by
more than 100mV;
The switch is OFF when the battery is plugged in.
1
0
The switch is OFF
1
1
The switch is ON
Figure 22. Lithium Battery Backup Control Truth Table
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13
MC33680
PACKAGE DIMENSIONS
32–LEAD LQFP
PLASTIC PACKAGE
CASE 873A–02
ISSUE A
A
4X
A1
AC T–U Z
25
BASE
METAL
ÉÉ
ÉÉ
ÉÉ
–U–
B
F
V
B1
DETAIL Y
17
8
9
D
J
SECTION AE–AE
4X
–Z–
9
V1
M
N
1
–T–
0.20 (0.008)
32
0.20 (0.008) AB T–U Z
0.20 (0.008) AC T–U Z
S1
–T–, –U–, –Z–
S
DETAIL AD
G
–AB–
SEATING
PLANE
–AC–
0.10 (0.004) AC
AE
8X
M_
P
R
AE
C E
W
K
X
DETAIL AD
Q_
GAUGE PLANE
H
0.250 (0.010)
DETAIL Y
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14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE
DETERMINED AT DATUM PLANE –AB–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE PROTRUSION
IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL
BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.500
0.700
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.020
0.028
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
MC33680
Notes
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MC33680
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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MC33680/D