SPM FSB67508 TM Smart Power Module (SPM®) Features General Description • RDS(ON).MAX=11mΩ @ ID=38A,TJ=25°C a half-bridge FRFET inverter including high voltage integrated circuit (HVIC) FSB67508 is a smart power module (SPM®) as a compact solution for small power motor drive applications such as Ebike. It is composed of 2 MOSFET, and 1 half-bridge HVIC for gate driving. This offers an extremely compact, high performance half-bridge inverter in a single isolated package . The package is optimized for the thermal performance and compactness for the use in the built-in motor application and any other application where the assembly space is concerned. • Negative dc-link terminals for inverter current sensing applications • HVIC for gate driving and protection functions • 3/5V CMOS/TTL compatible, active-high interface • Isolation voltage rating of 1500Vrms for 1min. • Embedded bootstrap diode in the package Absolute Maximum Ratings Symbol Parameter Conditions Rating Units 75 V VPN DC Link Input Voltage, Drain-source Voltage of each FET ID25 Each FET Drain Current, Continuous TC = 25°C 38 A ID80 Each FET Drain Current, Continuous TC = 80°C 28 A IDP Each FET Drain Current, Peak TC = 25°C, Pulsed* 95 A PD Maximum Power Dissipation TC = 25°C, Each 32 W VCC Control Supply Voltage Applied between VCC and COM 20 V VBS High-side Bias Voltage Applied between VB and U VIN Input Signal Voltage Applied between IN and COM TJ Operating Junction Temperature TSTG RθJC Storage Temperature Junction to Case Thermal Resistance Each under inverter operating condition (Note 1) 20 V -0.3 ~ VCC V -40 ~ 150 °C -50 ~ 150 °C 3.9 °C/W *Repetitive rating : Pulse width limited by maximum junction temperature ©2009 Fairchild Semiconductor Corporation FSB67508 Rev. A 1 www.fairchildsemi.com FSB67508 Smart Power Module (SPM®) October 2009 FSB67508 Smart Power Module (SPM®) Pin Descriptions Pin Number Pin Name Pin Description 1 P 2 VS Bias Voltage Ground for High Side MOSFET Driving 3 VB High-side Bias Voltage for MOSFET Driving 4 VCC Bias Voltage for IC and Low side MOSFET Driving 5 HIN Signal Input for High-side 6 LIN Signal Input for Low-side 7 COM Common Supply Ground 8 NC 9 N Negative DC-Link Input 10 U Output Positive DC–Link Input No connection (2) VS (3) VB VB (4) VCC VCC (5) HIN HIN (6) LIN LIN (8) NC NC (7) COM COM (1) P HO (10) U VS LO (9) N Note: Source terminal of each low-side MOSFET is not connected to supply ground or bias voltage ground inside SPM®. External connections should be made as indicated in Figure2. Figure 1. Internal Block Diagram 2 FSB67508 Rev. A www.fairchildsemi.com Inverter Part (Each MOSFET Unless Otherwise Specified) Symbol Min Typ 75 - - V Breakdown Voltage TemID = 250μA, Referenced to 25°C perature Coefficient - 0.6 - V IDSS Zero Gate Voltage Drain Current VIN= 0V, VDS = 75V - - 250 μA RDS(on) Static Drain-Source On-Resistance VCC = VBS = 15V, VIN = 5V, ID = 15A - 9.4 11 mΩ VSD Drain-Source Diode Forward Voltage VCC = VBS = 15V, VIN = 0V, ID = 15A - - 1.2 V VPN = 48V, VCC = VBS = 15V, ID = 15A VIN = 0V ↔ 5V Inductive load L=3mH High- and low-side FET switching - 550 - ns - 2000 - ns - 100 - ns - 40 - μJ - 190 - μJ BVDSS ΔBVDSS/ ΔTJ Parameter Drain-Source Breakdown VIN= 0V, ID = 250μA (Note 2) Voltage tON tOFF trr Conditions Switching Times EON (Note 3) EOFF RBSOA V = 55V, VCC = VBS = 15V, ID = IDP, VDS=BVDSS, Reverse-bias Safe Oper- PN TJ = 150°C ating Area High- and low-side FET switching (Note 3) Max Units Full Square Control Part (Each HVIC Unless Otherwise Specified) Symbol IQCC Parameter Quiescent VCC Current Conditions Min Typ Max Units VCC=15V, VIN=0V Applied between VCC and COM - - 160 μA Applied between VB(U)-U, VB(V)-V, VB(W)-W - - 100 μA IQBS Quiescent VBS Current VBS=15V, VIN=0V UVCCD Low-side Undervoltage Protection (Figure 6) VCC Undervoltage Protection Detection Level 7.4 8.0 9.4 V VCC Undervoltage Protection Reset Level 8.0 8.9 9.8 V High-side Undervoltage Protection (Figure 7) VBS Undervoltage Protection Detection Level 7.4 8.0 9.4 V VBS Undervoltage Protection Reset Level 8.0 8.9 9.8 V VIH ON Threshold Voltage Logic High Level 3.0 - - V VIL OFF Threshold Voltage Logic Low Level - - 0.8 V - 10 20 μA - - 2 μA UVCCR UVBSD UVBSR IIH IIL Input Bias Current VIN = 5V Applied between IN and COM Applied between IN and COM VIN = 0V Note: 1. BVDSS is the absolute maximum voltage rating between drain and source terminal of each FET inside SPM®. VPN should be sufficiently less than this value considering the effect of the stray inductance so that VDS should not exceed BVDSS in any case. 2. tON and tOFF include the propagation delay time of the internal drive IC. Listed values are measured at the laboratory test condition, and they can be different according to the field applcations due to the effect of different printed circuit boards and wirings. Please see Figure 3 for the switching time definition with the switching test circuit of Figure 4. 3. The peak current and voltage of each FET during the switching operation should be included in the safe operating area (SOA). Please see Figure 4 for the RBSOA test circuit that is same as the switching test circuit. Package Marking & Ordering Information Device Marking FSB67508 Device Package Reel Size Tape Width Quantity FSB67508 SPM10-AA _ _ 19 3 FSB67508 Rev. A www.fairchildsemi.com FSB67508 Smart Power Module (SPM®) Electrical Characteristics (TJ = 25°C, VCC=VBS=15V Unless Otherwise Specified) Symbol Parameter Value Conditions Units Min. Typ. Max. - 48 60 V VPN Supply Voltage Applied between P and N VCC Control Supply Voltage Applied between VCC and COM 13.5 15 16.5 V VBS High-side Bias Voltage Applied between VB and output 13 15 16.5 V 3.0 - VCC V 0 - 0.6 V 1.0 - - μs - 15 - kHz VIN(ON) Input ON Threshold Voltage VIN(OFF) Input OFF Threshold Voltage Applied between IN and COM tdead Blanking Time for Preventing VCC=VBS=13.5 ~ 20V, TJ ≤ 150°C Arm-short fPWM PWM Switching Frequency TJ ≤ 150°C These values depend on PWM control algorithm 15-V Line VS C1 VDC P P U Inverter Output VB VCC R5 HIN Micom HO VS LIN NC C5 10μF HIN LIN Output Note 1 0 0 Z Both FET Off 1 0 1 0 Low-side FET On 1 1 0 VDC High-side FET On 1 1 1 Forbidden Shoot-through 1 Open Open Z Same as (0, 0) 0 x x Z Same as (0, 0) C3 LO COM FO N N R3 C2 * Example of bootstrap paramters: C1 = C2 = 1μF ceramic capacitor, Note: (1) The snubber capacitor, C3, should be placed near SPM® (2) Parameters for bootsrap circuit elements are dependent on PWM algorithm. For 15 kHz of switching frequency, typical example of parameters is shown above. (3) RC coupling(R5 and C5) at each input (indicated as dotted lines) may be used to prevent improper input signal due to surge noise. Signal input of SPM® is compatible with standard CMOS or LSTTL outptus. (4) Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge voltage. Bypass capacitors such as C1, C2 and C3 should have good high-frequency characteristics to absorb high-frequency ripple current. Figure 2. Recommended CPU Interface and Bootstrap Circuit with Parameters Bootstrap Diode Part Symbol VRRM Parameter Conditions Maixmum Repetitive Reverse Voltage IF Forward Current TC = 25°C IFP Forward Current (Peak) TC = 25°C, Under 1ms Pulse Width TJ Operating Junction Temperature RB Equivalent Bootstrap Resistance TC = 25°C 4 FSB67508 Rev. A Rating Units 75 V 0.5 A 2 A -40 ~ 150 °C 15 Ω www.fairchildsemi.com FSB67508 Smart Power Module (SPM®) Recommended Operating Conditions FSB67508 Smart Power Module (SPM®) VIN VIN Irr VDS 120% of ID 100% of ID ID 10% of ID ID VDS tON trr tOFF (a) Turn-on (b) Turn-off Figure 3. Switching Time Definition V CC VS CB S ID P VB VCC H IN HO L + V DS - LIN NC V DC U VS LO N COM O n e-le g D iagra m of S P M Figure 4. Switching and RBSOA(Single-pulse) Test Circuit (Low-side) Input Signal UV Protection Status Low-side Supply, VCC RESET DETECTION RESET UVCCR UVCCD MOSFET Current Figure 5. Undervoltage Protection (Low-side) Input Signal UV Protection Status High-side Supply, VBS RESET DETECTION RESET UVBSR UVBSD MOSFET Current Figure 6. Undervoltage Protection (High-side) 5 FSB67508 Rev. A www.fairchildsemi.com VB VCC R5 (5) HIN C2 (10) U VS (1) P VCC (5) HIN Micom DC (9) N VB HO M (10) V HIN VS (6) LIN LIN (8) NC LO NC (7) COM (9) N COM (1) P (2) VS (3) VB (4) VCC VB VCC (5) HIN HO HIN (10) W VS (6) LIN LIN (8) NC LO NC (7) COM R V COM (2) VS (3) VB (4) VCC C2 3 LO NC (7) COM C2 C LIN (8) NC C5 HO HIN (6) LIN (9) N COM For 3-phase current sensing and protection 4 C4 R +15V Supply 3 Fig. 7. Example of Application Circuit Built in Bootstrap Diode VF-IF Characteristic 1.0 0.9 0.8 0.7 IF [A] 0.6 0.5 0.4 0.3 0.2 0.1 TC=25℃ 0.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VF [V] Note: Built in bootstrap diode includes around 15Ω resistance characteristic. Figure 8. Built in Bootstrap Diode Characteristics 6 FSB67508 Rev. A www.fairchildsemi.com FSB67508 Smart Power Module (SPM®) (1) P (2) VS (3) VB (4) VCC FSB67508 Smart Power Module (SPM®) Detailed Package Outline Drawings 7 FSB67508 Rev. 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AccuPower™ Auto-SPM™ Build it Now™ CorePLUS™ CorePOWER™ CROSSVOLT™ CTL™ Current Transfer Logic™ EcoSPARK® EfficentMax™ EZSWITCH™* ™* ® Fairchild® Fairchild Semiconductor® FACT Quiet Series™ FACT® FAST® FastvCore™ FETBench™ FlashWriter®* FPS™ F-PFS™ FRFET® SM Global Power Resource Green FPS™ Green FPS™ e-Series™ Gmax™ GTO™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ MotionMax™ Motion-SPM™ OPTOLOGIC® OPTOPLANAR® ® PDP SPM™ Power-SPM™ PowerTrench® PowerXS™ Programmable Active Droop™ QFET® QS™ Quiet Series™ RapidConfigure™ ™ Saving our world, 1mW/W/kW at a time™ SmartMax™ SMART START™ SPM® STEALTH™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SupreMOS™ SyncFET™ Sync-Lock™ ® * ® The Power Franchise TinyBoost™ TinyBuck™ TinyCalc™ TinyLogic® TINYOPTO™ TinyPower™ TinyPWM™ TinyWire™ TriFault Detect™ TRUECURRENT™* μSerDes™ UHC® Ultra FRFET™ UniFET™ VCX™ VisualMax™ XS™ * Trademarks of System General Corporation, used under license by Fairchild Semiconductor. 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Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I41 © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com