MC100LVE222 Low Voltage 1:15 Differential ÷1/÷2 ECL/PECL Clock Driver The MC100LVE222 is a low skew 1:15 differential ÷1/÷2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be differential or used single–ended (with VBB output reference bypassed and connected to the unused input of a pair). Either of two fully differential clock inputs may be selected. Each of the four output banks of 2, 3, 4, and 6 differential pairs may be independently configured to fanout 1X or 1/2X of the input frequency. The LVE222 specifically guarantees low output to output skew. Optimal design, layout, and processing minimize skew within a device and from lot to lot. The fsel pins and CLK_Sel pin are asynchronous control inputs. Any changes may cause indeterminate output states requiring a MR pulse to resynchronize any 1/2X outputs. To ensure that the tight skew specification is realized, both sides of any differential output pair need to be terminated identically even if only one side is being used. When fewer than all fifteen pairs are used, identically terminate all the output pairs on the same package side whether used or unused. If no outputs on a side are used, then leave all these outputs open (unterminated). This will maintain minimum output skew. Failure to do this will result in a 10–20ps loss of skew margin (propagation delay) in the output(s) in use. The MC100LVE222, as with most ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the LVE222 to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the LVE222’s performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line, terminations are typically used as they require no additional power supplies. All power supply pins must be connected. For more information on using PECL, designers should refer to Application Note AN1406/D. For a SPICE model, see Application Note AN1560/D. • 200ps Part–to–Part Skew • 50ps Output–to–Output Skew • Selectable 1x or 1/2x Frequency Outputs • Extended Power Supply Range of –3.0V to –5.25V (+3.0V to +5.25V) • 52–Lead TQFP Packaging • ESD > 2000V • Moisture Sensitivity Level 2, For Additional Information, See Application Note AND8003/D • Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34 • Transistor Count = 684 devices Semiconductor Components Industries, LLC, 1999 February, 2000 – Rev. 2 1 http://onsemi.com TQFP FA SUFFIX CASE 848D MARKING DIAGRAM* MC100LVE 222 AWLYYWW A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week 32 1 *For additional information, see Application Note AND8002/D ORDERING INFORMATION Device Package Shipping MC100LVE222FA TQFP 800 Units/Tray MC100LVE222FAR2 TQFP 1500 Tape & Reel Publication Order Number: MC100LVE222/D MC100LVE222 VCCO Qc0 Qc0 Qc1 Qc1 Qc2 Qc2 Qc3 Qc3 VCCO NC NC VCCO Pinout: 52–Lead TQFP (Top View) 39 38 37 36 35 34 33 32 31 30 29 28 27 VCCO 40 26 Qd0 Qb2 41 25 Qd0 Qb2 42 24 Qd1 Qb1 43 23 Qd1 Qb1 44 22 Qd2 Qb0 45 21 Qd2 Qb0 46 20 Qd3 VCCO 47 19 Qd3 Qa1 48 18 Qd4 Qa1 49 17 Qd4 Qa0 50 16 Qd5 Qa0 51 15 Qd5 VCCO 52 14 VCCO 7 8 fselb CLK0 CLK0 CLK_Sel CLK1 9 10 11 12 13 VEE 6 fseld 5 fselc 4 VBB 3 CLK1 2 fsela VCC 1 MR MC100LVE222 LOGIC SYMBOL MR CLK0 CLK0 CLK1 CLK1 ÷1 2 Qa0:1 Qa0:1 ÷2 CLK_Sel VBB fsela FUNCTION TABLE 3 Qb0:2 Qb0:2 fselb 4 Qc0:3 Qc0:3 6 Qd0:5 Qd0:5 fselc fseld http://onsemi.com 2 Function Input 0 1 MR CLK_Sel fseln Active CLK0 ÷1 Reset CLK1 ÷2 MC100LVE222 CLK RESET Q Figure 1. Timing Diagram MAXIMUM RATINGS* Symbol Parameter Value Unit VEE Power Supply (VCC = 0V) –8.0 to 0 VDC VI Input Voltage (VCC = 0V) 0 to –6.0 VDC Iout Output Current 50 100 mA TA Operating Temperature Range –40 to +85 °C Continuous Surge * Maximum Ratings are those values beyond which damage to the device may occur. ECL DC CHARACTERISTICS –40°C Symbol 0°C 25°C 70°C Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit VOH Output HIGH Voltage –1.085 –1.005 –0.880 –1.025 –0.955 –0.880 –1.025 –0.955 –0.880 –1.025 –0.955 –0.880 V VOL Output LOW Voltage –1.830 –1.695 –1.555 –1.810 –1.705 –1.620 –1.810 –1.705 –1.620 –1.810 –1.705 –1.620 V VIH Input HIGH Voltage –1.165 –0.880 –1.165 –0.880 –1.165 –0.880 –1.165 –0.880 V VIL Input LOW Voltage –1.810 –1.475 –1.810 –1.475 –1.810 –1.475 –1.810 –1.475 V VBB Output Reference Voltage –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 –1.38 –1.26 V VEE Power Supply Voltage –3.0 –5.25 –3.0 –5.25 –3.0 –5.25 –3.0 –5.25 V IIH Input HIGH Current 150 µA IIL Input CLK0, CLK1 LOW Current Others IEE Power Supply Current 150 –300 0.5 150 –300 0.5 122 136 150 –300 0.5 122 136 µA –300 0.5 122 136 125 139 mA PECL DC CHARACTERISTICS –40°C Symbol 0°C 25°C 70°C Characteristic Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit VOH Output HIGH Voltage1. 2.215 2.295 2.420 2.275 2.345 2.420 2.275 2.345 2.420 2.275 2.345 2.420 V VOL Output LOW Voltage1. 1.470 1.605 1.745 1.490 1.595 1.680 1.490 1.595 1.680 1.490 1.595 1.680 V VIH Input HIGH Voltage1. 2.135 2.420 2.135 2.420 2.135 2.420 2.135 2.420 V VIL Input LOW Voltage1. 1.490 1.825 1.490 1.825 1.490 1.825 1.490 1.825 V VBB Output Reference Voltage1. 1.92 2.04 1.92 2.04 1.92 2.04 1.92 2.04 V VCC Power Supply Voltage 3.0 5.25 3.0 5.25 3.0 5.25 3.0 5.25 V IIH Input HIGH Current 150 µA IIL Input CLK0, CLK1 LOW Current Others IEE Power Supply Current 150 –300 0.5 150 –300 0.5 122 136 150 –300 0.5 122 136 1. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC. http://onsemi.com 3 µA –300 0.5 122 136 125 139 mA MC100LVE222 ECL AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); VCC = VCCO = GND) –40°C Symbol Characteristic tPLH tPHL Propagation Delay to Output IN (differential) IN (single–ended) MR tskew Within–Device Skew Part–to–Part Skew (Diff) VPP Minimum Input Swing VCMR Common Mode Range VPP < 500mV VPP ≥ 500mV tr/tf Output Rise/Fall Time Min Typ 0°C Max Min 25°C Typ Max Min Typ 70°C Max Min Typ Max Unit Condition ps 1040 990 1100 1140 1140 1250 1240 1290 1400 1060 1010 1130 1160 1160 1280 50 200 400 1260 1310 1430 1080 1030 1170 1180 1180 1320 50 200 400 1280 1330 1470 1120 1070 1220 1220 1220 1370 50 200 400 Note 1. Note 2. 1320 1370 1520 50 200 400 VEE +1.3 –0.4 VEE +1.2 –0.4 VEE +1.2 –0.4 VEE +1.2 –0.4 VEE +1.6 –0.4 VEE +1.5 –0.4 VEE +1.5 –0.4 VEE +1.5 –0.4 200 600 200 600 200 600 200 600 ps Note 3. mV Note 4. V Note 5. ps 20%–80% 1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. 3. The within–device skew is defined as the worst case difference between any two similar delay paths within a single device. 4. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited for the LVE222. A differential input as low as 50 mV will still produce full ECL levels at the output. 5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min). PECL AC CHARACTERISTICS (VEE = GND; VCC = VCCO = VCC (min) to VCC (max)) –40°C Symbol Characteristic Min Typ 0°C Max Min 25°C Typ Max Min Typ 70°C Max Min Typ Max tPLH tPHL Propagation Delay to Output IN (differential) IN (single–ended) MR tskew Within–Device Skew Part–to–Part Skew (Diff) VPP Minimum Input Swing 400 VCMR Common Mode Range VPP < 500mV 1.3 VCC –0.4 1.2 VCC –0.4 1.2 VCC –0.4 1.2 VCC –0.4 VPP ≥ 500mV 1.6 VCC –0.4 1.5 VCC –0.4 1.5 VCC –0.4 1.5 VCC –0.4 200 600 200 600 200 600 200 600 tr/tf Output Rise/Fall Time Unit Condition ps 1040 990 1100 1140 1140 1250 1240 1290 1400 1060 1010 1130 1160 1160 1280 50 200 1260 1310 1430 1080 1030 1170 50 200 400 1180 1180 1320 1280 1330 1470 1120 1070 1220 50 200 400 1220 1220 1370 Note 1. Note 2. 1320 1370 1520 50 200 400 ps Note 3. mV Note 4. V Note 5. ps 20%–80% 1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. 3. The within–device skew is defined as the worst case difference between any two similar delay paths within a single device. 4. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited for the LVE222. A differential input as low as 50 mV will still produce full ECL levels at the output. 5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min). http://onsemi.com 4 MC100LVE222 PACKAGE DIMENSIONS FA SUFFIX TQFP PACKAGE CASE 848D–03 ISSUE C –X– X=L, M, N 4X 4X TIPS 0.20 (0.008) H L–M N 0.20 (0.008) T L–M N CL AB 52 G 40 1 AB 39 3X VIEW VIEW Y Y –L– –M– B B1 13 V J V1 27 14 0.13 (0.005) 26 A S 4X θ2 0.10 (0.004) T –H– –T– SEATING PLANE 4X θ3 VIEW AA 0.05 (0.002) D T L–M S N S SECTION AB–AB S1 C M U ROTATED 90_ CLOCKWISE –N– A1 ÉÉÉÉ ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ ÉÉÉÉ BASE METAL F PLATING S W θ1 2 X R R1 0.25 (0.010) C2 θ GAGE PLANE K C1 E Z VIEW AA http://onsemi.com 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –L–, –M– AND –N– TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –T–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z θ θ1 θ2 θ3 MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC ––– 1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0_ 7_ ––– 0_ 12 _ REF 5_ 13 _ INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC ––– 0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0_ 7_ ––– 0_ 12 _ REF 5_ 13 _ MC100LVE222 Notes http://onsemi.com 6 MC100LVE222 Notes http://onsemi.com 7 MC100LVE222 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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