FUJITSU SEMICONDUCTOR DATA SHEET DS04-22005-1E ASSP Communication Control IEEE1394-SCSI Tailgate MB86616 ■ DESCRIPTION The MB86616 is the LSI for protocol conversion to connect SCSI devices to the IEEE 1394 bus. This LSI integrates a 1394 controller compliant with the IEEE Standard for High Performance Serial Bus (IEEE Std. 1394-1995, or FireWire standard) and an SCSI protocol controller compliant with the SCSI-Fast20 standard on a single chip. It also incorporates the F2MC-16F as a processor for controlling the individual on-chip controllers, providing ease of control. The IEEE 1394 controller unit has two ports for use in a cable environment and contains a differential transceiver and a comparator. It supports S400 data transfer rates. In addition, it supports the Chain command to continuously issue request packets for data transmission and reception, improving the efficiency of data transfer. The SCSI protocol controller unit conforms to 8-bit Fast20 SCSI, enabling data transfer at a maximum of 20 Mbyte/s. For the SCSI bus terminal, the unit contains a totem pole type of single-end driver/receiver so that it can drive the SCSI bus directly. While inheriting the AT architecture of the F2MC-16/16H family, the instruction set for the F2MC-16F CPU core incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. ■ PACKAGE 144-pin Plastic LQFP (FPT-144P-M08) MB86616 ■ FEATURES • • • • • • • • • • • • IEEE 1394 Controller Unit Compliant with the IEEE Standard for High Performance Serial Bus (IEEE Std. 1394-1995 Physical and link layer modules integrated on a single chip Two cable ports Data transfer rates supported : S100, S200, S400 Data buffer dedicated to asynchronous transmission/reception 2-Kbyte (1/2/4 bank-switchable) , transmission/reception shared data buffer 128-byte buffer dedicated to asynchronous transmission and 128-byte buffer dedicated to asynchronous reception Automatic separation of the packet header and data upon reception and automatic packetization of information upon transmission 32-bit CRC generation and check functions Chain transfer function for data transfer sequence 4- and 4-conductor cables supported • SCSI Protocol Controller Unit • Dedicated to initiator operation • FAST-20 data transfer (8-bit) Synchronous transfer : 20 MBps Max. (Maximum offset value of 15) Asynchronous transfer : 5 MBps Max. • Internal 16-byte FIFO data register • Totem pole type of Fast20 single-end driver/receiver • 28-bit transfer byte counter enabling simultaneous transfer of up to 256 Mbytes of data • • • • F2MC-16F Unit Minimum instruction execution time : 40.7 ns (at 24.576 MHz) Instruction set optimized for controller applications Instruction set supporting high-level languages (including C) and multi tasking • Miscellaneous • Supply voltage : 3.3 V and 5 V power supplies • Package : LQFP-144 (FPT-144P-M08) 2 MB86616 ■ PIN ASSIGNMENT DRAWING (TOP VIEW) VDD3 VSS A06 A07 A08 A09 A10 A11 VSS VDD3 A12 A13 A14 A15 A16 A17 A18 VDD3 VSS TEST2 WR RD TEST3 P74 P75 P76 P90/INT0 P91/INT1 VDD3 VSS P92 P93 CS TEST4 TEST5 TEST6 109 110 115 120 125 130 135 140 144 VDD3 VSS MD0 MD1 MD2 SVSS RST BSY SEL SVSS SVDD5 VSS VDD3 MSG CD IO SVSS ATN REQ ACK SVSS DBP DB7 DB6 SVSS SVDD5 VSS VDD3 DB5 DB4 DB3 SVSS DB2 DB1 DB0 SVSS 1 108 105 5 100 10 95 15 MB86616 90 20 85 25 80 30 75 35 36 73 A05 A04 A03 A02 A01 TEST1 VSS VDD3 D15 D14 D13 D12 D11 D10 D09 D08 D07 VSS VDD3 D06 D05 D04 D03 D02 D01 D00 VDD3 VSS N.C. PWR3 PWR2 PWR1 LINKON PMODE VSS VDD3 72 70 65 60 55 50 45 40 37 AVSS AVDD TPBIAS0 TPA0 TPA0 TPB0 TPB0 AVDD AVSS AVSS AVDD TPBIAS1 TPA1 TPA1 TPB1 TPB1 AVDD AVSS CPS R0 AVDD AVSS RF FIL AVDD AVSS SCLK VSS N.C. TESTP MODEC MODEB MODEA RESET VSS VDD3 (FPT-144P-M08) 3 MB86616 ■ PIN ASSIGNMENT TABLE 4 Pin No. I/O Pin Name Pin No. I/O Pin Name Pin No. I/O Pin Name Pin No. I/O Pin Name 1 VDD3 37 VDD3 73 VDD3 109 VDD3 2 VSS 38 VSS 74 VSS 110 VSS 3 ID MD0 39 ID RESET 75 ID PMODE 111 ID/O A06 4 ID MD1 40 ID MODEA 76 O LINKON 112 ID/O A07 5 ID MD2 41 ID MODEB 77 ID PWR1 113 ID/O A08 6 SVSS 42 ID MODEC 78 ID PWR2 114 ID/O A09 7 SI/O RST 43 O TESTP 79 ID PWR3 115 ID/O A10 8 SI/O BSY 44 N.C. 80 N.C. 116 ID/O A11 9 SI/O SEL 45 VSS 81 VSS 117 VSS 10 SVSS 46 ID SCLK 82 VDD3 118 VDD3 11 SVDD5 47 AVSS 83 ID/O D00 119 ID/O A12 12 VSS 48 AVDD 84 ID/O D01 120 ID/O A13 13 VDD3 49 AO FIL 85 ID/O D02 121 ID/O A14 14 SI/O MSG 50 AO RF 86 ID/O D03 122 ID/O A15 15 SI/O CD 51 AVSS 87 ID/O D04 123 ID/O A16 16 SI/O IO 52 AVDD 88 ID/O D05 124 ID/O A17 17 SVSS 53 AO R0 89 ID/O D06 125 ID/O A18 18 SI/O ATN 54 I CPS 90 VDD3 126 VDD3 19 SI/O REQ 55 AVSS 91 VSS 127 VSS 20 SI/O ACK 56 AVDD 92 ID/O D07 128 O TEST2 21 SVSS 57 AI/O TPB1 93 ID/O D08 129 IU/O WR 22 SI/O DBP 58 AI/O TPB1 94 ID/O D09 130 IU/O RD 23 SI/O DB7 59 AI/O TPA1 95 ID/O D10 131 O TEST3 24 SI/O DB6 60 AI/O TPA1 96 ID/O D11 132 ID/O P74 25 SVSS 61 AO TPBIAS1 97 ID/O D12 133 ID/O P75 26 SVDD5 62 AVDD 98 ID/O D13 134 ID/O P76 27 VSS 63 AVSS 99 ID/O D14 135 ID/O P90/INT0 28 VDD3 64 AVSS 100 ID/O D15 136 ID/O P91/INT1 29 SI/O DB5 65 AVDD 101 VDD3 137 VDD3 30 SI/O DB4 66 AI/O TPB0 102 VSS 138 VSS 31 SI/O DB3 67 AI/O TPB0 103 O TEST1 139 ID/O P92 32 SVSS 68 AI/O TPA0 104 ID/O A01 140 ID/O P93 33 SI/O DB2 69 AI/O TPA0 105 ID/O A02 141 IU/O CS 34 SI/O DB1 70 AO TPBIAS0 106 ID/O A03 142 O TEST4 35 SI/O DB0 71 AVDD 107 ID/O A04 143 O TEST5 36 SVSS 72 AVSS 108 ID/O A05 144 O TEST6 MB86616 I/O types: ID : Digital input pin (with pull-down resistor) O : Digital output pin ID/O : Digital input/output pin (with pull-down resistor) IU/O : Digital input/output pin (with pull-up resistor) SI/O : SCSI input/output pin AI : Analog input pin AO : Analog output pin AI/O : Analog input/output pin 5 MB86616 ■ PIN DESCRIPTION 1. IEEE 1394 Interface Signal name I/O TPA0, TPA1 I/O TPA positive-signal input/output pin at IEEE 1394 port TPA0, TPA1 I/O TPA negative-signal input/output pin at IEEE 1394 port TPB0, TPB1 I/O TPB positive-signal input/output pin at IEEE 1394 port TPB0, TPB1 I/O TPB negative-signal input/output pin at IEEE 1394 port TPBIAS0, TPBIAS1 O Common-voltage reference voltage output pin at IEEE 1394 port 2. Function SCSI Interface Signal name I/O Function REQ, ACK, ATN, MSG, CD, IO, RST, BSY, SEL I/O SCSI control signal input/output pins DB0 to DB7 I/O Input/output pins for SCSI data bus DBP I/O Parity bit input/output pins for SCSI data bus 3. Internal CPU Pins (for Normal Operation Mode) Note that the pin functions covered in this section are enabled only in the normal operation mode (with the MODEA pin = “L”) . 6 Signal name I/O Function A01 to A18 O Address output pins D00 to D15 I/O Data input pins WR O Write strobe signal output pin RD O Read strobe signal output pin CS O Pin to output the external flash ROM chip enable signal. This signal is output for accessing an address from F80000h to FFFFFFh in memory space. P74 to P76 P90 to P93 I/O General-purpose input/output port pins MD0 to MD2 I CPU block mode setting pins. Connect all of these pins to GND on this device. MB86616 4. CPU Interface (for External CPU Mode) Note that the pin functions covered in this section are enabled only in the external CPU mode (with the MODEA pin = “H”) . Signal name I/O Function A01 to A09 I D00 to D15 I/O CS I Pin to input the chip select signal to this device WR I Pin to input the write strobe signal to this device RD I Pin to input the read strobe signal to this device INT0 O Interrupt request output pin for the IEEE 1394 block INT1 O Interrupt request output pin for the SCSI block External CPU address input pin External CPU data input/output pin 5. Other Pins Signal name I/O RESET I Reset signal input pin. Leave this pin at the “L” level while the IEEE 1394 block is operating with cable supplied power. MODEA I Pin for setting the operation mode of this device. “L” input : Use the internal CPU. “H” input : Use an external CPU to control this device without using the internal CPU. MODEB, MODEC I Connect these pins to GND. SCLK I Reference clock input pin for the internal PLL (24.576 MHz) RF O Connect this pin to GND via a 5.1 kΩ resistor. FIL O External filter circuit connection pin for the internal PLL R0 O Connect this pin to GND via a 5.1 kΩ resistor. I Pin to input power supplied through the IEEE 1394 cable. The pin detects cable supplied power of 0 to 33 V (an external resistor is required to regulate/divide the voltage) . Connect this pin to GND if the device is not powered through the IEEE 1394 cable. I Power input evaluation pin. “L” input : Operate the device with power supplied through the IEEE 1394 cable. (Only the IEEE 1394 block operates with the cable supplied power, with the other blocks left in the reset state.) “H” input : Operate the device with the system power supply. CPS PMODE Function Pins to set the POWER_CLASS bit in the Self-ID packet which is transmitted during operation with power supplied through the IEEE 1394 cable. PWR1 to PWR3 I Note : The POWER_CLASS in the Self-ID packet transmitted during operation with the system power supply depends not on these pins but on the settings of the Pwr bits (Bits 2 to 0) in physical register #4. (Continued) 7 MB86616 (Continued) Signal name I/O Function LINKON O Output pin for detection of Link-on packet reception. This pin outputs the “H” level signal upon reception of the Link-on packet during operation with power supplies through the IEEE 1394 cable. The output signal level changes to “L” the moment the PMODE signal becomes “H”. The output from this pin remains unchanged with PMODE = “H”. Leave this pin open when not in use. TESTP, TEST1 to TEST6 O Test pin. Leave it open. N.C. Leave this pin open. 6. Power/GND Pins 8 Signal name I/O Function VDD3 3.3 V digital power supply pin VSS Digital ground pin SVDD5 5 V power supply pin for SCSI I/O SVSS Ground pin for SCSI I/O AVDD 3.3 V analog power supply pin AVSS Analog ground pin MB86616 ■ BLOCK DIAGRAM A01 to A18 D00 to D15 RD WR CS • Normal Operation Mode External interface RAM 4 kbyte SCLK FIL F2MC-16F bus PLL F2MC-16F CPU RF Clock frequency divider TPA0/TPA1 TPA0/TPA1 TPB0/TPB1 TPB0/TPB1 TPBIAS0/TPBIAS1 External interrupt CPU bus DREQA IEEE1394 block DWRA 16 bit Timer ×3 DREQB Exchange block DRDA DWRB DRDB DMA data bus SCSI block RST BSY SEL MSG CD IO REQ ACK ATN DBP DB0 to DB7 9 MB86616 A01 to A09 D00 to D15 RD WR CS INT0, INT1 • External CPU Mode CPU-I/F SCLK FIL PLL CPU bus RF Clock frequency divider RST DREQA TPA0/TPA1 TPA0/TPA1 TPB0/TPB1 TPB0/TPB1 TPBIAS0/TPBIAS1 BSY DREQB SEL IEEE1394 block DWRA Exchange block DRDA DWRB DRDB SCSI block MSG CD IO REQ ACK ATN DBP DB0 to DB7 DMA data bus 10 MB86616 ■ FUNCTIONS of BLOCKS • CPU Block This block controls the individual blocks. It incorporates the F2MC-16F as the core and RAM, 16-bit timers (3 channels) , and an external interrupt controller as peripheral circuits. • IEEE 1394 Block This block controls the IEEE 1394 interface. • SCSI Block This block controls the SCSI interface. • PLL Circuit This block generates clock signals for individual blocks from the reference clock signal generated by the clock module. Reference oscillation frequency : 24.576 MHz Clock frequency for CPU block : 24.576 MHz Clock frequency for IEEE 1394 block : 393.216 MHz (for bus) , 49.152 MHz (for internal operation) Clock frequency for SCSI block : 39.322 MHz Clock frequency for Exchange block : 39.322 MHz 11 MB86616 ■ INTERNAL REGISTERS 1. Memory Space FFFFFFH (External flash ROM) F80000H Inaccessible area 002300H 002200H Exchange block SCSI block 002100H IEEE 1394 block 002000H 001100H RAM General registers 000100H 0000C0H 000000H CPU block External ROM/external bus mode 12 MB86616 2. CPU Block Internal Registers Address (HEX) WRITE operation READ operation Resource name Register name Abbreviation Register name Abbreviation 000000 to 000006 System reserved area System reserved area 000007 Port-7 data register PDR7 Port-7 data register PDR7 Port 7 000008 System reserved area System reserved area 000009 Port-9 data register PDR9 Port-9 data register PDR9 Port 9 00000A to 00000F (reserved) (reserved) 000010 to 000016 System reserved area System reserved area 000017 Port-7 direction register DDR7 Port-7 direction register DDR7 Port 7 000018 System reserved area System reserved area 000019 Port-9 direction register DDR9 Port-9 direction register DDR9 Port 9 000019 to 00002F (reserved) (reserved) 000030 Interrupt/DTP enable register ENIR Interrupt/DTP enable register ENIR 000031 Interrupt/DTP source register ENRR Interrupt/DTP source register ENRR 000032 Request level set register ELVR Request level set register ELVR 000033 to 00003F (reserved) (reserved) Timer control status #0 TMCSR0 Timer control status #0 TMCSR0 (reserved) 16 bit timer #0 TMT0 16-bit timer reload #0 TMRLR0 (reserved) (reserved) (reserved) Timer control status #1 TMCSR1 Timer control status #1 TMCSR1 (reserved) 16 bit timer #1 TMT1 16 bit timer reload #1 TMRLR1 (reserved) (reserved) (reserved) 000040 000041 000042 000043 000044 000045 000046 to 000047 000048 000049 00004A 00004B 00004C 00004D 00004E to 00004F DTP/external interrupt 16-bit timer #0 16-bit timer #1 (Continued) 13 MB86616 Address (HEX) WRITE operation READ operation Resource name Register name Abbreviation Register name Abbreviation Timer control status #2 TMCSR2 Timer control status #2 TMCSR2 (reserved) 16 bit timer #2 TMT2 16 bit timer reload #2 TMRLR2 (reserved) 000056 to 00008F (reserved) (reserved) 000090 to 00009E System reserved area System reserved area 00009F Delayed interrupt source generate/reset register DIRR Delayed interrupt source generate/reset register DIRR Delayed interrupt 0000A0 Standby control register STBYC Standby control register STBYC Low power consumption 0000A1 to 0000A2 (reserved) (reserved) 0000A3 Middle address control register MACR (reserved) External pin 0000A4 High address control register HACR (reserved) External pin 0000A5 External pin control register EPCR (reserved) External pin 0000A6 to 0000A7 (reserved) (reserved) 0000A8 Watchdog timer control register TWC Watchdog timer control register TWC Watchdog timer 0000A9 Time-base timer control register TBTC Time-base timer control register TBTC Time-base timer 0000AA to 0000AF (reserved) (reserved) 0000B0 Interrupt control register 0 ICR0 Interrupt control register 0 ICR0 0000B1 Interrupt control register 1 ICR1 Interrupt control register 1 ICR1 0000B2 System reserved area System reserved area 0000B3 System reserved area System reserved area 0000B4 Interrupt control register 4 ICR4 Interrupt control register 4 ICR4 0000B5 Interrupt control register 5 ICR5 Interrupt control register 5 ICR5 0000B6 System reserved area System reserved area 000050 000051 000052 000053 000054 000055 16-bit timer #2 Interrupt controller (Continued) 14 MB86616 (Continued) WRITE operation READ operation Address (HEX) Register name Abbreviation Register name Abbreviation 0000B7 Interrupt control register 7 ICR7 Interrupt control register 7 ICR7 0000B8 Interrupt control register 8 ICR8 Interrupt control register 8 ICR8 0000B9 Interrupt control register 9 ICR9 Interrupt control register 9 ICR9 0000BA Interrupt control register 10 ICR10 Interrupt control register 10 ICR10 0000BB System reserved area System reserved area 0000BC System reserved area System reserved area 0000BD System reserved area System reserved area 0000BE System reserved area System reserved area 0000BF Interrupt control register 15 ICR15 Interrupt control register 15 ICR15 Resource name Interrupt controller 15 MB86616 3. IEEE 1394 Block Internal Registers WRITE operation READ operation Address (HEX) Register name Abbreviation Register name Abbreviation 002000 mode-control MCTL mode-control MCTL 002002 (reserved) flag & status FLST 002004 instruction-fetch INST instruction-fetch INST 002006 Interrupt-mask set register INTM Interrupt-code display register INTC 002008 (reserved) Reception acknowledge display register RACK 00200A A-buffer data port transmit register SADP A-buffer data port receive register RADP 00200C D-buffer data port transmit register SDDP D-buffer data port receive register RDDP 00200E (reserved) (reserved) 002010 (reserved) (reserved) 002012 Transmission ASYNC-des-ID set register SADID (reserved) 002014 Transmission ASYNC-PKT-param set register SAPP Reception ASYNC-PKT-param display register RAPP 002016 Transmission ASYNC-data-length set register SADL Reception ASYNC-data-length display register RADL 002018 Transmission ASYNC-ex-tcode set register SAET Reception ASYNC-ex-tcode display register RAET 00201A Transmission ASYNC-source-busID set register SASID Reception ASYNC-source-ID display register RASID 00201C Transmission ASYNC-rcode set register SARC Reception ASYNC-rcode display register RARC 00201E Transmission ASYNC-des-offset set register (upper) SADOU Reception ASYNC-des-offset display register (upper) RADOU 002020 Transmission ASYNC-des-offset set register (middle) SADOM Reception ASYNC-des-offset display register (middle) RADOM 002022 Transmission ASYNC-des-offset set register (lower) SADOL Reception ASYNC-des-offset display register (lower) RADOL 002024 Total chain data-length set register (upper) CSDLU Remaining chain data byte counter (upper) CRBCU 002026 Total chain data length set register (lower) CSDLL Remaining chain data byte counter (lower) CRBCL 002028 Chain transmission des-ID set register CDID Ping time monitor PTMN 00202A Chain transmission des-offset set register (upper) CDOU (reserved) 00202C Chain transmission des-offset set register (middle) CDOM (reserved) (Continued) 16 MB86616 (Continued) Address (HEX) WRITE operation READ operation Register name Abbreviation Register name Abbreviation 00202E Chain transmission des-offset set register (lower) CDOL (reserved) 002030 Chain transmission data-length set register CSDL Received packet transfer rate display register PSPD 002032 Chain retry-limit set register CRLM Cycle-timer-monitor display register (upper) CTMU 002034 (reserved) Cycle-timer-monitor display register (lower) CTML 002036 (reserved) Revision display register REVM 002038 PHY/LINK register address set register PLRA PHY/LINK register address set register PLRA 00203A PHY/LINK register access port (Write) WPLAP PHY/LINK register access port (Read) RPLAP 00203C to 0000FE (reserved) (reserved) 17 MB86616 4. SCSI Block Internal Registers WRITE operation READ operation Address (HEX) Register name Abbreviation Register name Abbreviation 002100 Bus Device ID BDID Bus Device ID BDID 002102 SCSI Control SCTL SCSI Control SCTL 002104 SCSI Command SCMD SCSI Command SCMD 002106 Transfer Mode TMOD Transfer Mode TMOD 002108 Interrupt Sense INTS Interrupt Sense INTS 00210A SCSI Diagnostic Control SDGC Phase Sense PSNS 00210C (reserved) SCSI Block Status SSTS 00210E (reserved) SCSI Error Status SERR 002110 Phase Control PCTL Phase Control PCTL 002112 Extend Transfer Counter TCE Extend Transfer Counter TCE 002114 Data Register (SCSI output) DREG Data Register (SCSI input) DREG 002116 Temporary (SCSI output) TEMP Temporary (SCSI input) TEMP 002118 Transfer Counter (High) TCH Transfer Counter (High) TCH 00211A Transfer Counter (Mid) TCM Transfer Counter (Mid) TCM 00211C Transfer Counter (Low) TCL Transfer Counter (Low) TCL 00211E REQ/ACK Timeout Set RATO Modified Byte Counter MBC 002120 to 0000FE (reserved) (reserved) 5. Exchange Block Internal Registers 18 WRITE operation READ operation Address (HEX) Register name Abbreviation Register name Abbreviation 002200 Mode Control EMOD Mode Control EMOD 002202 Signal Control ESCTL Signal Sense ESSNS 002204 Data Port (Input) EDPI Data Port (Output) EDPO 002206 to 0000FE (reserved) (reserved) MB86616 ■ ABSOLUTE MAXIMUM RATINGS (Vss = 0 V) Parameter Power supply voltage Input voltage Output voltage Symbol Rating Min. Max. Unit VSS − 0.5 4.0 V DD5*1 VSS − 0.5 6.0 V VI3 VSS − 0.5 VDD3 + 0.5 V VI5*1 VSS − 0.5 VDD5 + 0.5 V VO3 VSS − 0.5 VDD3 + 0.5 V VSS − 0.5 VDD5 + 0.5 V VDD3 V O5*1 V Ambient storage temperature Tst −55 +125 °C Operating junction temperature Tj −40 +125 °C Output current*2 IO IOL = 4 mA ±14 mA Overshoot VDD3 + 1.0 Undershoot VSS − 1.0 *3 *3 V V *1 : For SCSI I/O *2 : Maximum supply current which can flow in steady state. Exceeding it is allowed only within 1 second per LSI unit excluding the SCSI I/O. *3 : Within 50 ns WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 19 MB86616 ■ RECOMMENDED OPERATING CONDITIONS (Vss = 0 V) Parameter Power supply voltage “H” level input voltage Symbol Values Min. Typ. Max. Unit 3.3 V power supply VDD3 3.0 3.3 3.6 V 5 V power supply (for SCSI-I/O) VDD5 4.5 5.0 5.5 V CMOS Normal*1 VIHN VDD3 × 0.65 VDD3 + 0.3 V CMOS Schmitt*2 VIHS VDD3 × 0.80 VDD3 + 0.3 V SCSI VIHSC 2.0 VDD5 + 0.3 V *1 VILN VSS VDD3 × 0.25 V *2 CMOS Schmitt VILS VSS VDD3 × 0.20 V SCSI VILSC VSS 0.8 V Differential input voltage (for data transfer) IEEE1394 VIDD 118 260 mV Differential input voltage (for arbitration) IEEE1394 VIDA 168 265 mV S100 VCM100 1.165 2.515 V S200 VCM200 0.935 2.515 V S400 VCM400 0.523 2.515 V CMOS Normal “L” level input voltage Common-mode input voltage IEEE1394 Receiving input jitter IEEE1394 0.315 ns Receiving input skew IEEE1394 0.8 ns Ta 0 70 °C Operating temperature *1 : D00 to D15 *2 : MD0 to MD2, RESET, MODEA to MODEC, PMODE, PWR1 to PWR3, A01 to A18, CS, WR, RD, P74 to P76, P90 to P93, TEST2 to TEST6. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 20 MB86616 ■ ELECTRICAL CHARACTERISTICS 1. DC CHARACTERISTICS The DC characteristics guarantee the worst-case values of static characteristics of the input/output buffers within the recommended operating condition ranges. (1) Digital I/O Pins (VDD3 = 3.3 ± 0.3 V, Vss = 0 V, Ta = 0 to 70 °C) Parameter Symbol “H” level output voltage IOH = −4 mA Unit Min. Typ. Max. VDD − 0.5 VDD V VOL IOL = 4 mA VSS 0.4 V IOS VO = 0 V or VDD ± 60 mA Normal Input ILI 3state Input ILZ VI = 0 V to VDD −5 5 µA 25 50 200 kΩ Output short-circuit current Input resistance VOH Values *1 “L” level output voltage Input leakage current*2 Conditions pull-up Rpu VIL = 0 V pull-down Rpd VIH = VDD *1 : Maximum current that flows when the output pin is connected to Vdd or Vss, for one second per LSI pin. *2 : The input leakage current may exceed the above value when an input buffer with pull-up or pull-down resistor is used. (2) SCSI I/O Pins Parameter (VDD5 = 5.0 ± 0.5 V, Vss = 0 V, Ta = 0 to 70 °C) Symbol Conditions Values Min. Typ. Max. Unit “H” level output voltage VOHSC IOH = −7 mA 2 VDD V “L” level output voltage VOLSC IOL = 48 mA VSS 0.5 V Input hysteresis voltage width VHYS 0.2 V 21 MB86616 (3) IEEE 1394 Driver and Comparator • Driver (VDD3 = 3.3 ± 0.3 V, Vss = 0 V, Ta = 0 to 70 °C) Parameter Symbol Conditions VOD S100 Typ. Max. RL = 56 Ω 172 265 mV ICM Driver enable, signaling off −0.81 0.44 mA S200 ISP200 S200 speed signaling enable −2.53 −4.84 mA S400 ISP400 S400 speed signaling enable −8.10 −12.40 mA VOFF Driver disable 20 mV S100 VOM Driver enable, signaling off 1.665 2.015 V S200 VSP200 S200 speed signaling enable 1.438 2.015 V S400 VSP400 S400 speed signaling enable 1.030 2.015 V Off-state voltage Common-mode output voltage Unit Min. Differential output voltage Common-mode output current Values • Comparator (VDD3 = 3.3 ± 0.3 V, Vss = 0 V, Ta = 0 to 70 °C) Parameter Symbol Conditions IIC H-level detection Port-status Comparator Typ. Max. Driver disable −20 20 µA VACH 168 mV Z-level detection VACZ −89 89 mV L-level detection VACL 168 mV connection detection VPCH 1.0 V disconnection detection VPCL 0.6 V (4) Supply Current 22 Unit Min. Common-mode input current Arbitration Comparator Values (VDD3 = 3.3 ± 0.3 V, VDD5 = 5.0 ± 0.5 V, Vss = 0 V, Ta = 0 to 70 °C) Parameter Symbol Conditions Supply current (3.3 V power supply) IDD3 Supply current (5.0 V power supply) IDD5 Values Unit Min. Typ. Max. 300 mA 100 mA MB86616 2. AC CHARACTERISTICS (1) Clock Input Parameter Symbol Pin name Values Min. Typ. Max. Unit Clock frequency FC 24.576 MHz Clock cycle time tC 1/FC ns 15 ns 3 ns “H” and “L” level clock pulse widths Clock rise time, clock fall time SCLK tWCH, tWCL tCR, tCF FCPU 24.576 MHz tCPU 1/Fcpu ns F1394 393.216 MHz FSCSI 39.322 MHz tSCSI 1/Fscsi ns FEXC 39.322 MHz tCYC tcpu 16 tcpu ns IEEE 1394 bus (Note 2) F1394B 98.304 196.608 393.216 MHz SCSI bus (Synchronous transfer) FSCSIB 1.229 19.661 MHz CPU block Clock input to each IEEE 1394 block block SCSI block Exchange block CPU block machine clock (Note 1) Note1 : The maximum value assumes the minimum speed (1/16) set by the clock gear feature. Note2 : The values are transfer rates at S100/S200/S400. tWCH tC tCF tCR 0.65 VDD 0.25 VDD SCLK tWCL 23 MB86616 (2) Reset Input Parameter “L” level reset pulse width Symbol Pin name tWRSL RESET tWRSL RESET 24 Values Min. Typ. Max. 5 tcp Unit ns MB86616 ) (3) External Bus Interface (Flash ROM Interface) 3-1 Bus Read Parameter (Load pin capacitance = 30 pF) Symbol Pin name Address cycle time tACYC Valid address→RD↓ Values Unit Min. Max. A01 to A18, CS (2 + n*) tcyc − 10 ns tAVRL A01 to A18, CS, RD tcyc / 2 − 13 ns RD “L” level pulse width tRLRH RD (1 + n*) tcyc − 25 ns RD↓ →Valid data tRLDV RD, D00 to D15 (1 + n*)tcyc − 30 ns RD↑→Data hold tRHDX RD, D00 to D15 0 ns Valid address→Valid data tAVDV A01 to A18, CS, D00 to D15 (3 / 2 + n*)tcyc − 10 ns RD↑→Valid address tRHAX RD, A01 to A18, CS tcyc / 2 − 20 ns *: n is the number of wait cycle.(no wait ; n = 0) The number of wait cycle is set by external pin control registor. tACYC A01 to A18 CS tAVRL tRHAX tRLRH RD tRHDX tRLDV D00 to D15 tAVDV 25 MB86616 3-2 Bus Write (Load pin capacitance = 30 pF) Parameter Symbol Pin name Address cycle time tACYC Valid address→WR↓ Values Unit Min. Max. A01 to A18, CS (2 + n*) tcyc − 10 ns tAVWL A01 to A18, CS, WR tcyc / 2 − 13 ns WR “L” level pulse width tWLWH WR (1 + n*) tcyc − 20 ns Written data→WR↑ tDVWH WR, D00 to D15 (1 + n*) tcyc − 25 ns WR↑→Data hold tWHDX WR, D00 to D15 tcyc / 2 − 15 ns WR↑→Valid address tWHAX WR, A01 to A18, CS tcyc / 2 − 15 ns *: n is the number of wait cycle.(no wait ; n = 0) The number of wait cycle is set by external pin control registor. tACYC A01 to A18 CS tAVWL tWHAX tWLWH WR tDVWH tWHDX D00 to D15 (4) IEEE 1394 Driver Parameter Symbol Pin name Transmission jitter tJT Transmission skew tDK TPA, TPA, TPB, TPB Transmission rise time, fall time * tDR, tDF * : Measurement conditions : CL = 10 pF, RL = 56 Ω 26 Values Unit Min. Max. ±0.15 ns ±0.10 ns 1.2 ns MB86616 (5) SCSI Interface 5-1 Target Selection Operation (with Arbitration) Parameter Symbol Pin name SEL↓→BSY↑ ts011 ID assert→BSY↑ Values Unit Min. Max. SEL, BSY 0 ns ts012 DB0 to DB7, DBP, BSY 0 ns IO↑→BSY↑ ts013 IO, BSY 0 ns BSY↑→BSY↓ ts014 BSY 18 tscsi 19 tscsi + 20 ns BSY↓→SEL↑ ts015 BSY, SEL 0 ns BSY↓→ID hold ts016 DB0 to DB7, DBP, BSY 10 ns SEL↑→Phase signal output ts017 SEL, IO CD, MSG 9 tscsi 10 tscsi + 20 ns BSY tS011 tS014 tS015 SEL tS012 tS016 DB0 to DB7, DBP tS013 tS017 IO, CD, MSG 27 MB86616 5-2 Target Selection Operation (without Arbitration) Parameter Symbol Pin name ID assert→SEL↓ ts021 IO↑→SEL↓ Values Max. DB0 to DB7, DBP, SEL 0 ns ts022 IO, SEL 0 ns SEL↓→BSY↓ ts023 SEL, BSY 18 tscsi 19 tscsi + 20 ns BSY↓→SEL↑ ts015 BSY, SEL 0 ns BSY↓→ID hold ts016 BSY, DBP DB0 to DB7 10 ns SEL↑ →Phase signal output ts017 SEL, IO, CD, MSG 9 tscsi 10 tscsi + 20 ns BSY tS023 tS015 SEL tS021 tS016 DB0 to DB7, DBP tS022 IO, CD, MSG 28 Unit Min. tS017 MB86616 5-3 Initiator Selection Operation (with Arbitration) Parameter Symbol Pin name Bus free→BSY↓ ts031 BSY↓→Self-ID output Values Unit Min. Max. BSY (21 + n*) tscsi (22 + n*) tscsi + 20 ns ts032 BSY, DBP, DB0 to DB7 0 15 ns BSY↓→SEL↓ ts033 BSY, SEL 128 tscsi − 10 128 tscsi + 15 ns SEL↓→ATN↓ & ID output ts034 SEL, ATN, DBP, DB0 to DB7 52 tscsi − 10 52 tscsi + 15 ns ID output→BSY↑ ts035 DB0 to DB7, DBP, BSY 8 tscsi − 10 8 tscsi + 15 ns BSY↓→SEL↑ & ID hold ts036 BSY, SEL, DBP, DB0 to DB7 8 tscsi 9 tscsi + 20 ns * : SCSI block TCL register value BSY tS031 tS033 tS035 tS036 SEL tS032 tS034 DB0 to DB7, DBP ATN 29 MB86616 5-4 Initiator Selection Operation (without Arbitration) Parameter Symbol Pin name Bus free→ID output ts041 ID output→SEL↓ & ATN↓ BSY↓→SEL↑ & ID hold Values Max. DB0 to DB7, DBP (21 + n*) tscsi (22 + n*) tscsi + 10 ns ts042 DB0 to DB7, DBP, SEL, ATN 44 tscsi − 15 44 tscsi + 10 ns ts036 BSY, SEL, DBP, DB0 to DB7 8 tscsi 9 tscsi + 20 ns * : SCSI block TCL register value BSY tS036 SEL tS041 DB0 to DB7, DBP ATN 30 Unit Min. tS042 MB86616 5-5 Target Reselection Operation Parameter Symbol Pin name Bus free→BSY↓ ts031 BSY↓ →Self-ID output Values Unit Min. Max. BSY (21 + n*) tscsi (22 + n*) tscsi + 20 ns ts032 BSY, DBP, DB0 to DB7 0 15 ns BSY↓→SEL↓ ts033 BSY, SEL 128 tscsi − 10 128 tscsi + 15 ns SEL↓→Phase signal & ID output ts051 SEL, IO, CD, MSG, DBP, DB0 to DB7 52 tscsi − 10 52 tscsi + 15 ns ID output→BSY↑ ts035 DB0 to DB7, DBP, BSY 8 tscsi − 10 8 tscsi + 15 ns BSY↓→BSY↓output ts052 BSY 8 tscsi 9 tscsi + 20 ns BSY↓output→ SEL↑ & ID hold ts053 BSY, SEL, DBP, DB0 to DB7 4 tscsi 9 tscsi + 20 ns * : SCSI block TCL register value BSY tS031 tS035 tS033 tS052 tS053 SEL tS032 tS051 DB0 to DB7, DBP IO CD, MSG 31 MB86616 5-6 Initiator Reselection Operation Parameter Symbol Pin name SEL↓→BSY↑ ts011 ID assert→BSY↑ Values Max. SEL, BSY 0 ns ts012 DB0 to DB7, DBP, BSY 0 ns IO↓→BSY↑ ts061 IO, BSY 0 ns BSY↑→BSY↓ ts014 BSY 18 tscsi 19 tscsi + 20 ns BSY↓→SEL↑ ts015 BSY, SEL 0 ns BSY↓→ID hold ts016 BSY, DBP, DB0 to DB7 10 ns BSY↓→IO hold ts062 BSY, IO 10 ns SEL↑→BSY↓ (Output stop) ts063 SEL, BSY 8 tscsi 9 tscsi + 20 ns BSY tS011 tS014 tS015 SEL tS012 tS016 DB0 to DB7, DBP tS061 IO 32 Unit Min. tS062 tS063 MB86616 5-7 Target Asynchronous Transfer (REQ/ACK Timing) Parameter Symbol Pin name REQ↓→ACK↓ ts071 ACK↓→REQ↑ Values Unit Min. Max. REQ, ACK 0 ns ts072 ACK, REQ 0 25 ns REQ↑→ACK↑ ts073 REQ, ACK 0 ns ACK↑→REQ↓ (Note 2) ts074 ACK, REQ 0 25 ns ACK↓→REQ↓ (Notes 1, 2) ts075 ACK, REQ 8 tscsi 9 tscsi + 5 ns Note1 : The “ACK rise to REQ fall” time is regulated by (ts072 + ts073 + ts074) or ts075, whichever is longer. Note2 : In the following cases, the time regulation is not applied because data transfer is aborted. • The data register is empty during data output to the SCSI bus. • The data register is full during data input from the SCSI bus. REQ tS071 tS072 tS073 tS074 ACK tS075 33 MB86616 5-8 Target Asynchronous Transfer (Data Output) Parameter Symbol Pin name IO↓→Data bus drive ts081 Data output assert→REQ↓ ACK↓→Data hold Values Max. IO, DBP, DB0 to DB7 33 tscsi 34 tscsi + 10 ns ts082 DB0 to DB7, DBP, REQ 8 tscsi − 5 ns ts083 ACK, DBP, DB0 to DB7 0 ns REQ ACK tS082 DB0 to DB7, DBP tS081 IO 34 Unit Min. tS083 MB86616 5-9 Target Asynchronous Transfer (Data Input) Parameter Symbol Pin name IO↑→Data bus driving stop ts091 Data setup→ACK↓ REQ↑→Data hold Values Unit Min. Max. IO, DBP, DB0 to DB7 0 10 ns ts092 DB0 to DB7, DBP, ACK 10 ns ts093 REQ, DBP, DB0 to DB7 5 ns REQ ACK tS092 tS093 DB0 to DB7, DBP tS091 IO 35 MB86616 5-10 Target Synchronous Transfer (REQ/ACK Timing) Parameter Symbol Pin name REQ assert time ts101 REQ negate time Unit Min. Max. REQ n*•tscsi ns ts102 REQ n*•tscsi ns ACK assert time ts103 ACK 10 ns ACK negate time ts104 ACK 10 ns ACK cycle time (1) ts105 ACK 1 tscsi ns ACK cycle time (2) ts106 ACK 3 tscsi ns * : Value set in bits 3 to 0 in the SCSI block TMOD register REQ tS101 tS102 ACK tS103 tS104 tS105 tS106 36 Values MB86616 5-11 Target Synchronous Transfer (REQ Output Delay Time) Parameter REQ output delay time (Note) Symbol Pin name ts111 ACK, REQ Values Min. Max. 3 tscsi 4 tscsi + 10 Unit ns Note : The minimum time from the reception of ACK in the (N-m) -th byte to the output of REQ in the N-th byte with Maximum offset count = m. The following timing chart assumes that REQ output is aborted because output of REQ in the N-1-th byte has made the number of offsets the maximum offset count = m. The maximum offset count is set by bits 7 to 4 in the SCSI block transfer mode register. REQ N−2 N−1 N tS111 ACK N−m 37 MB86616 5-12 Target Synchronous Transfer (Data Output) Parameter IO↓→Data bus drive Symbol Pin name ts081 Max. IO, DBP, DB0 to DB7 33 tscsi 34 tscsi + 10 ns ts121 DB0 to DB7, DBP, REQ 8 tscsi − 5 ns ts122 DB0 to DB7, DBP, REQ n*•tscsi − 5 ns ts123 DB0 to DB7, DBP, REQ n*•tscsi ns * : Value set in bits 3 to 0 in the SCSI block TMOD register REQ tS121 DB0 to DB7, DBP IO 38 tS123 Asserted data tS081 Unit Min. Data output assert→REQ↓ REQ↓→Data hold Values tS122 MB86616 5-13 Target Synchronous Transfer (Data Input) Parameter Symbol Pin name IO↑→Data bus driving stop ts091 Data setup→ACK↓ ACK↓→Data hold Values Unit Min. Max. IO, DBP, DB0 to DB7 0 10 ns ts131 DB0 to DB7, DBP, ACK 5 ns ts132 ACK, DBP, DB0 to DB7 5 ns ACK tS131 tS132 DB0 to DB7, DBP tS091 IO 39 MB86616 5-14 Initiator Asynchronous Transfer (REQ/ACK Timing) Parameter Symbol Pin name REQ↓→ACK↓ (Note 3) ts141 ACK↓→REQ↑ Values Unit Min. Max. REQ, ACK 0 25 ns ts142 ACK, REQ 0 ns REQ↑→ACK↑ (Note 3) ts143 REQ, ACK 0 1 tscsi ns ACK↑→REQ↓ ts144 ACK, REQ 0 ns REQ↑→ACK↓ (Notes 1, 3) ts145 REQ, ACK 8 tscsi 9 tscsi + 5 ns REQ↑→ACK↓ (Notes 2, 3) ts146 REQ, ACK 4 tscsi 5 tscsi + 5 ns REQ↓→ACK↑ (Notes 2, 3) ts147 REQ, ACK 8 tscsi 9 tscsi + 5 ns Note1 : Applies to data output to the SCSI bus. The “REQ rise to ACK fall” time is regulated by (ts143 + ts144 + ts141) or ts145, whichever is longer. Note2 : Applies to data input from the SCSI bus. The “REQ rise to ACK fall” time is regulated by (ts143 + ts144 + ts141) or ts146, whichever is longer. The “REQ fall to ACK rise” time is regulated by (ts141 + ts142 + ts143) or ts147, whichever is longer. Note3 : In the following cases, either time regulation is not applied because data transfer is aborted. • The data register is empty during data output to the SCSI bus. • The data register is full during data input from the SCSI bus. • ATN is output upon detection of a parity error during data input from the SCSI bus. • During transfer of the first or last byte tS145, tS146 REQ tS141 tS142 ACK tS147 40 tS143 tS144 MB86616 5-15 Initiator Asynchronous Transfer (Data Output) Parameter Symbol Pin name IO↑→Data bus drive ts151 Phase signal assert→REQ↓ Values Unit Min. Max. IO, DBP, DB0 to DB7 0 10 ns ts152 IO, CD, MSG, REQ 30 ns Data output assert→ACK↓ ts153 DB0 to DB7, DBP, ACK 8 tscsi − 5 ns REQ↑→Data hold ts154 REQ, DBP, DB0 to DB7 0 ns ACK↑→Phase signal hold ts155 ACK, IO, CD, MSG 10 ns REQ tS152 ACK tS153 DB0 to DB7, DBP tS154 Asserted data tS151 tS155 IO CD, MSG 41 MB86616 5-16 Initiator Asynchronous Transfer (Data Input) Parameter Symbol Pin name IO↓→Data bus drive stop ts161 Phase signal assert→REQ↓ Values Max. IO, DBP, DB0 to DB7 30 ns ts152 IO, CD, MSG, REQ 30 ns Data setup→REQ↓ ts162 DB0 to DB7, DBP, REQ 10 ns ACK↓→Data hold ts163 ACK, DBP, DB0 to DB7 5 ns ACK↑→Phase signal hold ts155 ACK, IO, CD, MSG 10 ns REQ tS152 ACK tS162 tS163 DB0 to DB7, DBP tS161 IO CD, MSG 42 Unit Min. tS155 MB86616 5-17 Initiator Synchronous Transfer (REQ/ACK Timing) Parameter Symbol Pin name REQ assert time ts171 REQ negate time Values Unit Min. Max. REQ 10 ns ts172 REQ 10 ns REQ cycle time (1) ts173 REQ 1 tscsi ns REQ cycle time (2) ts174 REQ 3 tscsi ns ACK assert time ts175 ACK n*•tscsi ns ACK negate time ts176 ACK n*•tscsi ns * : Value set in bits 3 to 0 in the SCSI block TMOD register tS174 tS173 tS171 tS172 REQ tS175 tS176 ACK 43 MB86616 5-18 Initiator Synchronous Transfer (ACK Output Delay Time) Parameter Symbol Pin name ACK output delay time (1) (Notes 1, 2) ts181 ACK output delay time (2) (Notes 1, 3) ts182 Values Unit Min. Max. REQ, ACK 9 tscsi 12 tscsi + 5 ns REQ, ACK 3 tscsi 4 tscsi + 5 ns Note1 : The minimum time from the reception of REQ in the N-th byte to the output of ACK in the N-th byte. Note2 : Applies to data input from the SCSI bus, with the maximum offset count set to 8 to 15. The maximum offset count is set by bits 7 to 4 in the SCSI block transfer mode register. Note3 : Applies in any case other than Note 2. REQ N−1 N+1 N tS181, tS182 ACK 44 N−2 N−1 N MB86616 5-19 Initiator Synchronous Transfer (Data Output) Parameter Symbol Pin name IO↑→Data bus drive ts151 Phase signal assert→REQ↓ Values Unit Min. Max. IO, DBP, DB0 to DB7 0 10 ns ts152 IO, CD, MSG, REQ 30 ns ts191 DB0 to DB7, DBP, ACK 8 tscsi − 5 ns ts192 DB0 to DB7, DBP, ACK n*•tscsi − 5 ns ACK↓→Data hold ts193 DB0 to DB7, DBP, ACK n*•tscsi ns ACK↑→Phase signal hold ts155 ACK, IO, CD, MSG 10 ns Data output assert→ACK↓ (Note ) * : Value set in bits 3 to 0 in the SCSI block TMOD register Note : The "data output assert to ACK fall" time is regulated by ts191 or ts192, whichever is shorter. REQ tS152 ACK tS191 DB0 to DB7, DBP tS193 tS192 Asserted data tS151 tS155 IO CD, MSG 45 MB86616 5-20 Initiator Synchronous Transfer (Data Input) Parameter Symbol Pin name IO↓→Data bus drive stop ts161 Phase signal assert→REQ↓ Values Unit Min. Max. IO, DBP, DB0 to DB7 30 ns ts152 IO, CD, MSG, REQ 30 ns Data setup→REQ↓ ts162 DB0 to DB7, DBP, REQ 5 ns REQ↓→Data hold ts201 REQ, DBP, DB0 to DB7 5 ns ACK↑→Phase signal hold ts155 ACK, IO, CD, MSG 10 ns REQ tS152 ACK tS162 tS201 DB0 to DB7, DBP tS161 IO CD, MSG 46 tS155 MB86616 5-21 Arbitration Failure Parameter Symbol Pin name Arbitration start→ BSY↑ & Self-ID output stop ts211 Other device’s SEL↓→ BSY↑ & Self-ID output stop ts212 Values Unit Min. Max. BSY, DBP, DB0 to DB7 128 tscsi − 10 128 tscsi + 15 ns SEL, BSY, DB0 to DB7, DBP 8 tscsi 9 tscsi + 20 ns tS211 BSY tS212 SEL DB0 to DB7, DBP 47 MB86616 5-22 Selection/Reselection Time-out Parameter TIME OUT interrupt reset→ SCSI bus clear Symbol Pin name ts222 SEL, IO, DBP, DB0 to DB7 Write strobe tS221 SEL DB0 to DB7, DBP IO 48 Values Min. Max. 3 tscsi − 10 3 tscsi + 15 Unit ns MB86616 5-23 Target Disconnect Operation Parameter Symbol Pin name REL command issue →BSY↑ ts231 REL command issue→SCSI bus clear ts232 Values Unit Min. Max. BSY 3 tscsi − 10 3 tscsi + 15 ns REQ, IO, CD, MSG, DBP, DB0 to DB7 3 tscsi − 10 3 tscsi + 15 ns Write strobe tS231 BSY tS232 DB0 to DB7, DBP REQ, IO, CD, MSG 49 MB86616 5-24 Initiator Disconnect Operation Parameter BSY↑→SCSI bus clear Symbol Pin name ts241 BSY, ACK, ATN, DBP, DB0 to DB7 BSY tS241 DB0 to DB7, DBP ATN, ACK 50 Values Min. Max. 21 tscsi + 20 Unit ns MB86616 5-25 Reset Condition Detection Parameter Symbol Pin name Reset condition detection time ts251 RST↓→SCSI bus clear ts252 Values Unit Min. Max. RST 12 tscsi ns All SCSI bus pins 12 tscsi + 20 ns tS251 RST tS252 SCSI bus signals other than RST 51 MB86616 5-26 Reset Condition Generation Parameter Symbol Pin name Write “1” to RST OUT bit→ RST↓ ts261 RST↓→SCSI bus clear Write “0” to RST OUT bit→ RST↑ Values Max. RST 10 ns ts262 All SCSI bus pins 10 ns ts263 RST 10 ns Write strobe tS261 RST tS262 SCSI bus signals other than RST 52 Unit Min. MB86616 (6) IEEE 1394/SCSI/Exchange Block Register Access 6-1 Read Operation Parameter Symbol Pin name Address setup tRAVRL Address hold Values Unit Min. Max. A01 to A09, CS, RD 10 ns tRRHAX A01 to A09 CS, RD 5 ns RD “L” level pulse width tRRLRH RD 40 ns RD↓→Valid data tRRLDV RD, D00 to D15 25 ns RD↑→Data hold tRRHDX RD, D00 to D15 5 ns WR↑→RD↓ tRWHRL WR, RD 45 ns A01 to A09 CS tRAVRL tRRLRH tRRHAX RD tRRHDX tRRLDV D00 to D15 tRWHRL WR 53 MB86616 6-2 Write Operation Parameter Symbol Pin name Address setup tRAVWL Address hold Values Max. A01 to A09, CS, WR 10 ns tRWHAX A01 to A09 CS, WR 5 ns WR “L” level pulse width tRWLWH WR 40 ns Data setup tRDVWH WR, D00 to D15 30 ns Data hold tRWHDX WR, D00 to D15 5 ns A01 to A09 CS tRAVWL tRWLWH tRWHAX WR tRDVWH D00 to D15 54 Unit Min. tRWHDX MB86616 6-3 Register Access Recovery Time • Continuous Read/Write Operation Shown below is the timing of continuously reading or writing the register at the same address. Parameter Symbol Pin name RD (WR) ↑→RD (WR) ↓ tRWHRWL1 RD (WR) ↑→RD (WR) ↓ (Note) tRWHRWL2 Values Unit Min. Max. RD/WR 25 ns WR/RD 45 ns Note : Applies to access to an internal register of the IEEE 1394 block in forced sleep mode. tRWHRWL1, 2 RD (WR) • Write Operation→Read Operation Shown below is the timing of reading after writing the register at the same address. Parameter Symbol Pin name WR↑→RD↓ tWRHRDL1 WR↑→RD↓ (Note ) tWRHRDL2 Values Unit Min. Max. WR, RD 80 ns WR, RD 160 ns Note : Applies to access to an internal register of the IEEE 1394 block in forced sleep mode. WR tWRHRDL1, 2 RD 55 MB86616 • IEEE 1394 Block PHY/LINK Register Read Operation Shown below is the timing from writing the PHY/LINK register address set register (address 002038h) to reading the PHY/LINK access port (address 00203Ah) to access the PHY-LINK register in the IEEE 1394 block. Parameter Symbol Pin name WR↑→RD↓ tPLWHRL1 WR↑→RD↓ (Note ) tPLWHRL2 Values Unit Min. Max. WR, RD 100 ns WR, RD 200 ns Note : Applies to access in forced sleep mode. tPLWHRL1, 2 WR Write to address 002038h RD Read from address 00203Ah • IEEE 1394 Block PHY/LINK Register Write Operation Shown below is the timing from writing the PHY/LINK register address set register (address 002038h) to writing the PHY/LINK access port (address 00203Ah) to access the PHY-LINK register in the IEEE 1394 block. Parameter WR↑→WR↓ Symbol Pin name tPLWHWL1 WR Values Min. Max. 100 tPLWHWL1, 2 WR Write to address 002038h 56 Write to address 00203Ah Unit ns MB86616 ■ SYSTEM CONFIGURATION EXAMPLES 1. Recommended Connection Example of IEEE 1394 Port (1 Port) TPBIAS 56 Ω ± 1% 1 µF ± 5% TPA Cable TPB TPA Cable TPB TPB Cable TPA Cable TPA Cable Power (8 to 33 V) 56 Ω ± 1% 56 Ω ± 1% TPB 56 Ω ± 1% 5.1 kΩ ± 1% 250 pF ± 5% R0 5.1 kΩ ± 1% Cable Power 510 kΩ ± 5% Cable Ground CPS 91 kΩ ± 5% 57 MB86616 2. Recommended Connection Example of Internal PLL Loop Filter FIL 390 Ω ± 5% 3300 pF ± 5% RF 5.1 kΩ ± 1% 58 MB86616 3. Sample System Configurations • Normal Mode (Using the Internal CPU) RESET TPA0 SCLK TPA0 MODEA TPB0 IEEE1394 Connector0 TPB0 MODEB, MODEC TPBIAS0 MD0 to MD2 TPA1 MB86616 TPA1 TPB1 WR TPB1 RD TPBIAS1 IEEE1394 Connector1 CS DBP ATN DB0 to DB7 ACK IO REQ CD PWR1 to PWR3 SEL P74 to P76, P90 to P93 MSG PMODE RST D00 to D15 BSY External flash ROM A01 to A18 SCSI Connector 59 MB86616 • External CPU Mode RESET TPA0 SCLK TPA0 MODEA TPB0 IEEE1394 Connector0 TPB0 MODEB, MODEC TPBIAS0 MD0 to MD2 TPA1 MB86616 TPA1 External CPU A01 to A09 TPB1 WR TPB1 RD TPBIAS1 CS D00 to D15 PMODE INT0 INT1 SCSI Connector 60 DBP ATN DB0 to DB7 ACK IO REQ CD SEL MSG RST BSY PWR1 to PWR3 IEEE1394 Connector1 MB86616 ■ ORDERING INFORMATION Part number MB86616PFV-G-BND Package Remarks 144-pin Plastic LQFP (FPT-144P-M08) 61 MB86616 ■ PACKAGE DIMENSION 144-pin Plastic LQFP (FPT-144P-M08) 22.00±0.30(.866±.012)SQ 1.70(.67)MAX (Mounting height) 20.00±0.10(.787±.004)SQ 108 0(0)MIN (STAND OFF) 73 109 72 17.50 (.686) REF 21.00 (.827) NOM Details of "A" part 0.15(.006) 0.15(.006) INDEX 0.15(.006)MAX 144 37 0.40(.016)MAX "A" LEAD No. 1 36 0.50(.0197)TYP 0.20±0.10 (.008±.004) 0.08(.003) Details of "B" part M 0.15±0.05 (.006±.002) 0 0.10(.004) C 10° 0.50±0.20(.020±.008) "B" 2000 FUJITSU LIMITED F144019S-1C-3 Dimensions in mm (inches) 62 MB86616 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. 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