Revised August 2000 100323 Low Power Hex Bus Driver General Description Features The 100323 is a monolithic device containing six bus drivers capable of driving terminated lines with terminations as low as 25Ω. To reduce crosstalk, each output has its own respective ground connection. Transition times were designed to be longer than on other F100K devices. The driver itself performs the positive logic AND of a data input (D1–D6) and the OR of two select inputs (E and either DE1, DE2, or DE3). ■ 50% power reduction of the 100123 ■ 2000V ESD protection ■ −4.2V to −5.7V operating range ■ Drives 25Ω load Enabling of data is possible in multiples of two, i.e., 2, 4 or all 6 paths. All inputs have 50 kΩ pull-down resistors. The output voltage LOW level is designed to be more negative than normal ECL outputs (cut off state). This allows an emitter-follower output transistor to turn OFF when the termination supply is −2.0V and thus present a high impedance to the data bus. Ordering Code: Order Number Package Number Package Description 100323PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100323QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagrams 24-Pin DIP Pin Descriptions Pin Names Description D1–D6 Data Inputs DE1–DE3 Dual Enable Inputs E Common Enable Input O1–O6 Data Outputs © 2000 Fairchild Semiconductor Corporation 28-Pin PLCC DS009877 www.fairchildsemi.com 100323 Low Power Hex Bus Driver July 1988 100323 Truth Table E DEn Dn Dn+1 On On+1 L L X X Cutoff Cutoff X H L L Cutoff Cutoff X H L H Cutoff H X H H L H Cutoff X H H H H H H X L L Cutoff Cutoff H X L H Cutoff H H X H L H Cutoff H X H H H H H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Cutoff = Lower-than-LOW State Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions −65°C to +150°C Storage Temperature Maximum Junction Temperature +150°C VEE Pin Potential to Ground Pin −7.0V to +0.5V Output Current (DC Output High) −50 mA ESD ≥2000V −5.7V to −4.2V Supply Voltage (VEE) VEE to +0.5V Input Voltage (DC) 0°C to +85°C Case Temperature Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. DC Electrical Characteristics (Note 3) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Symbol Parameter Min Typ VIH Input HIGH Voltage −1165 VIL Input LOW Voltage −1830 VOH Output HIGH Voltage −1025 VOHC Output HIGH Voltage −1035 VOLZ Cut-Off LOW Voltage IIL Input LOW Current IIH Input HIGH Current IEE Power Supply Current −955 Max Units −870 mV Guaranteed High Signal for ALL Inputs −1475 mV Guaranteed Low Signal for ALL Inputs −870 mV VIN = VIH (max) or VIL (min) Loading with 25Ω to −2.0V −1950 0.50 −121 −91 Conditions mV VIN = VIH (min) or VIL (max) Loading with 25Ω to −2.0V mV VIN = VIH (min) or VIL (max) Loading with 25Ω to −2.0V µA VIN = VIL (min) 240 µA VIN = VIH (max) −57 mA Inputs Open Note 3: The specified limits represent “worst case” values for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. DIP AC Electrical Characteristics (Note 4) VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter TC = 0°C TC = +25°C TC = +85°C Min Max Min Max Min Max 3.80 tPZH Propagation Delay 1.90 3.60 1.90 3.60 2.00 tPHZ Data to Output 1.30 2.70 1.30 2.70 1.50 2.70 tPZH Propagation Delay 1.90 3.60 1.90 3.60 2.00 3.90 tPHZ Dual Enable to Output 1.60 3.00 1.60 3.00 1.70 3.40 tPZH Propagation Delay 1.80 3.50 1.80 3.50 2.00 3.80 tPHZ Common Enable to Output 1.50 2.90 1.50 2.90 1.60 3.00 tTZH Transition Time 0.50 1.80 0.50 1.80 0.50 1.80 tTHZ 20% to 80%, 80% to 20% 0.35 1.40 0.35 1.40 0.35 1.40 Units Conditions ns ns Figures 1, 2 ns ns Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. PLCC AC Electrical Characteristics (Note 5) VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter TC = 0°C TC = +25°C TC = +85°C Min Max Min Max Min Max tPZH Propagation Delay 1.90 3.40 1.90 3.40 2.00 3.60 tPHZ Data to Output 1.30 2.50 1.30 2.50 1.50 2.70 tPZH Propagation Delay 1.90 3.40 1.90 3.40 2.00 3.70 tPHZ Dual Enable to Output 1.60 2.80 1.60 2.80 1.70 3.00 tPZH Propagation Delay 1.80 3.30 1.80 3.30 2.00 3.60 2.80 tPHZ Common Enable to Output 1.50 2.70 1.50 2.70 1.60 tTZH Transition Time 0.50 1.70 0.50 1.70 0.50 1.70 tTHZ 20% to 80%, 80% to 20% 0.35 1.30 0.35 1.20 0.35 1.30 Units Conditions ns ns Figures 1, 2 ns ns Note 5: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. 3 www.fairchildsemi.com 100323 Absolute Maximum Ratings(Note 1) 100323 Test Circuitry Note: • VCC, VCCA = +2V, VEE = −2.5V • L1 and L2 = equal length 50Ω impedance lines • RT = 50Ω terminator internal to scope • Decoupling 0.1 µF from GND to VCC and VEE • All unused outputs are loaded with 25Ω to GND • CL = Fixture and stray capacitance ≤ 3 pF • Pin numbers shown are for flatpak; for DIP see logic symbol FIGURE 1. AC Test Circuit Timing Waveform FIGURE 2. Propagation Delay and Transition Times www.fairchildsemi.com 4 100323 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E 5 www.fairchildsemi.com 100323 Low Power Hex Bus Driver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6