SEMICONDUCTOR TECHNICAL DATA L SUFFIX CERAMIC CASE 620 The MC14547 BCD–to–seven segment decoder/driver is constructed with complementary MOS (CMOS) enhancement mode devices and NPN bipolar output drivers in a single monolithic structure. The circuit provides the functions of an 8421 BCD–to–seven segment decoder with high output drive capability. Blanking (BI), can be used to turn off or pulse modulate the brightness of the display. The MC14547 can drive seven–segment light–emitting diodes (LED), incandescent, fluorescent or gas discharge readouts either directly or indirectly. Applications include instrument (e.g., counter, DVM, etc.) display driver, computer/calculator display driver, cockpit display driver, and various clock, watch, and timer uses. P SUFFIX PLASTIC CASE 648 DW SUFFIX SOIC CASE 751G ORDERING INFORMATION • • • • • • • • High Current Sourcing Outputs (Up to 65 mA) Low Logic Circuit Power Dissipation Supply Voltage Range = + 3.0 V to + 18 V Blanking Input Readout Blanking on All Illegal Combinations Lamp Intensity Modulation Capability Multiplexing Capability Capable of Driving Two Low–Power TTL Loads, One Low–Power Schottky TTL Load or Two HTL Loads over the Rated Temperature Range • Use MC14511B for Applications Requiring Data Latches MC14XXXBCP MC14XXXBCL MC14XXXBDW TA = – 55° to 125°C for all packages. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* (Voltages referenced to VSS, Pin 8) Rating DC Supply Voltage Symbol Plastic Ceramic SOIC B 1 16 VDD C 2 15 f NC 3 14 g BI 4 13 a NC 5 12 b Value Unit D 6 11 c VDD – 0.5 to + 18 V A 7 10 d Vin – 0.5 to VDD + 0.5 V VSS 8 9 e Operating Temperature Range TA – 55 to + 125 _C Tstg – 65 to + 150 _C IOHmax 65 mA PD 1200* Maximum Continuous Output Drive Current (Source) per Output Maximum Continuous Power Dissipation e b c d Input Voltage, All Inputs Storage Temperature Range a g f DISPLAY 0 1 2 3 4 5 6 7 8 9 mW TRUTH TABLE * Maximum Ratings are those values beyond which damage to the device may occur. * See Power Derating Curve Figure 1. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. A destructive high current mode may occur if Vin and Vout is not constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the outputs are shorted to VSS and are at a logical 1 (See Maximum Ratings). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Inputs Outputs BI D C B A a b c d e f g Display 0 X X X X 0 0 0 0 0 0 0 Blank 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 1 0 1 0 0 0 0 0 1 1 0 1 2 3 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 0 1 1 1 1 1 0 1 1 0 0 0 1 0 1 1 1 0 1 1 1 0 4 5 6 7 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 8 9 Blank Blank 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Blank Blank Blank Blank X = Don’t care REV 3 1/94 MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA MC14547B 1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol 25_C 125_C Min Max Min Typ # Max Min Max Unit “0” Level VOL 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0 0 0 0.05 0.05 0.05 — — — 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.1 9.1 14.1 — — — 4.4 9.4 14.4 4.6 9.6 14.6 — — — 4.3 9.3 14.4 — — — Vdc 5.0 10 15 — — — 1.5 3.0 4.0 — — — 2.25 4.50 6.75 1.5 3.0 4.0 — — — 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — 5.0 4.0 — 3.8 — 3.1 — — — — 4.2 4.1 3.9 3.7 3.2 4.3 4.3 4.2 4.0 3.7 — — — — — 4.3 — 4.0 — 3.0 — — — — — Vin = 0 or VDD Input Voltage # “0” Level (VO = 3.8 or 0.5 Vdc) (VO = 8.8 or 1.0 Vdc) (VO = 13.8 or 1.5 Vdc) (VO = 0.5 or 3.8 Vdc) (VO = 1.0 or 8.8 Vdc) (VO = 1.5 or 13.8 Vdc) Output Drive Voltage (IOH = 5.0 mA) (IOH = 10 mA) (IOH = 20 mA) (IOH = 40 mA) (IOH = 65 mA) – 55_C VDD Vdc VIL VIH Vdc VOH Source Vdc Vdc (IOH = 5.0 mA) (IOH = 10 mA) (IOH = 20 mA) (IOH = 40 mA) (IOH = 65 mA) 10 9.1 — 8.8 — 8.4 — — — — — 9.2 9.1 9.0 8.9 8.5 9.3 9.3 9.2 9.0 8.8 — — — — — 9.3 — 9.2 — 8.1 — — — — — Vdc (IOH = 5.0 mA) (IOH = 10 mA) (IOH = 20 mA) (IOH = 40 mA) (IOH = 65 mA) 15 14 — 13.8 — 13.5 — — — — — 14.2 14.1 14.0 13.8 13.5 14.3 14.3 14.2 14.0 13.7 — — — — — 14.4 — 14.2 — 13.3 — — — — — Vdc 5.0 10 15 0.32 0.80 2.10 — — — 0.26 0.65 1.7 0.44 1.13 4.4 — — — 0.18 0.45 1.2 — — — Output Drive Current (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) IOL Sink mAdc Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc Input Capacitance Cin — — — — 5.0 7.5 — — pF Quiescent Current (Per Package) Vin = 0 or VDD, Iout = 0 µA IDD 5.0 10 15 — — — 5.0 10 20 — — — 0.005 0.010 0.015 5.0 10 20 — — — 150 300 600 µAdc Total Supply Current**† (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT 5.0 10 15 IT = (1.9 µA/kHz) f + IDD IT = (3.8 µA/kHz) f + IDD IT = (5.7 µA/kHz) f + IDD µAdc #Noise immunity specified for worst input combination. Noise Margin for both “1” and “0” level = 1.0 V min @ VDD = 5.0 V = 2.0 V min @ VDD = 10 V = 2.5 V min @ VDD = 15 V †To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf where: IT is in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency. ** The formulas given are for the typical characteristics only at 25_C. MC14547B 2 MOTOROLA CMOS LOGIC DATA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C) Characteristic Symbol VDD Vdc Min Typ Max Unit Output Rise Time tTLH 5.0 10 15 — — — 40 40 40 80 80 80 ns Output Fall Time tTHL 5.0 10 15 — — — 125 75 70 250 150 140 ns Data Propagation Delay Time tPLH 5.0 10 15 — — — 750 300 200 1500 600 400 ns tPHL 5.0 10 15 — — — 750 300 200 1500 600 400 tPLH 5.0 10 15 — — — 750 300 200 1500 600 400 tPHL 5.0 10 15 — — — 500 250 170 1000 500 340 Blank Propagation Delay Time MOTOROLA CMOS LOGIC DATA ns MC14547B 3 LOGIC DIAGRAM BI 4 A 7 13 a 12 b B 1 11 c 10 d C 2 9 e 15 f D 6 14 g PD, MAXIMUM POWER DISSIPATION (mW) PER PACKAGE 1200 1000 (L) CERAMIC 800 600 (P) PDIP 400 410 mW (L) (D) SOIC 230 mW (P) 150 mW (D) 200 0 25 50 75 100 125 150 175 TA, AMBIENT TEMPERATURE (0°C) Figure 1. Ambient Temperature Power Derating MC14547B 4 MOTOROLA CMOS LOGIC DATA CONNECTIONS TO VARIOUS DISPLAY READOUTS LIGHT EMITTING DIODE (LED) READOUT VDD VDD COMMON ANODE LED COMMON CATHODE LED ≈ 1.7 V ≈ 1.7 V VSS VSS INCANDESCENT READOUT VDD VDD LIGHT–EMITTING DIODE (LED) READOUT USING A ZENER DIODE TO REPLACE DROPPING RESISTORS VDD ** COMMON CATHODE LED VSS VSS GAS DISCHARGE READOUT VDD APPROPRIATE VOLTAGE VZD* VSS FLUORESCENT READOUT VDD DIRECT (LOW BRIGHTNESS) VSS * VZD should be set at VDD – 1.3 V – VLED. Wattage of zener diode must be calculated for number of segments and worst–case conditions. ** A filament pre–warm resistor is recommended to reduce filament thermal shock and increase the effective cold resistance of the filament. MOTOROLA CMOS LOGIC DATA FILAMENT SUPPLY VSS VSS OR APPROPRIATE VOLTAGE BELOW VSS. (Caution: Absolute maximum working voltage = 18.0 V) MC14547B 5 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– K H G D J 16 PL 0.25 (0.010) MC14547B 6 SEATING PLANE M T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C –T– SEATING PLANE M D 16 PL 0.25 (0.010) M T B S A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MOTOROLA CMOS LOGIC DATA ◊ *MC14547B/D* MC14547B MC14547B/D 7