74ABT3284 18-Bit Synchronous Datapath Multiplexer Y General Description Y The 74ABT3284 is a synchronous datapath buffer designed to transmit four 9-bit bytes of data onto one or two 9-bit bytes in 2:1 or 4:1 multiplexed configurations. In addition, the non-inverting transceiver supports bidirectional data transfer in transparent or registered modes. A data byte from any one of the six ports can be stored during transparent operation for later recall. Data input to any port may also be read back to itself for byte manipulation or system self-diagnostic purposes. The 74ABT3284 is useful for interleaving data in memory applications or for use in bus-to-bus communications where variations in data word length or construction are required. Y Y Y Y Y Y Y 18-bit 2:1 or 9-bit 4:1 multiplexed modes Registered or transparent datapath operation Output enables and select lines have the option of being synchronized for pipelined operation Independent input, output register and control synchronizing clocks insure maximum timing flexibility Independent control signals insure functional flexibility Guaranteed simultaneous switching noise level and dynamic threshold performance Guaranteed latchup protection High impedance glitch free bus loading during entire power up and power down cycle Non-destructive hot insertion capability Features Y Advanced BiCMOS technology provides high speed at low power consumption Commercial 74ABT3284VJG Package Number VJG100A Connection Diagram Package Description 100-Lead (14mm x 14mm) Molded Plastic Quad Flatpak, JEDEC Pin Assignment Pin TL/F/11582–1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin ModeÐSO CPÐAX OEC LDCI LDCO SA2X1 SA2X0 X0 X1 GND X2 X3 X4 X5 X6 GND X7 X8 OEX XSEL0 XSEL1 LDAO LDAI OEA VCC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin VCC A8 A7 A6 GND A5 A4 A3 A2 GND A1 A0 VCC B0 B1 GND B2 B3 B4 B5 GND B6 B7 B8 VCC 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pin CPÐIN OEB LDBI LDBO ModeÐW YSEL OEY Y8 Y7 GND Y6 Y5 Y4 Y3 Y2 GND Y1 Y0 LDDO LDDI ASEL1 ASEL0 OED CPÐXA ModeÐSC 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VCC D8 D7 D6 GND D5 D4 D3 D2 GND D1 D0 VCC C0 C1 GND C2 C3 C4 C5 GND C6 C7 C8 VCC TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/11582 RRD-B30M125/Printed in U. S. A. 74ABT3284 18-Bit Synchronous Datapath Multiplexer October 1995 Functional Description All Data Path Control Inputs and Input/Output Register Load Enable Inputs are active high and can be asserted asynchronously or synchronously. When MODEÐSC is low, these inputs operate asynchronously. When MODEÐSC is high, the inputs are asserted synchronously on the positive edge of the CPÐIN clock. When operating the Data Path Control and/or the Output Enable Input groups with MODEÐSC and/or MODEÐSO ‘‘hard wired’’ high for synchronous mode, a single pre-clock of CPÐIN will be required following power-up to insure that all internal synchronous control registers are in the appropriate known state. if the application requires ‘‘on the fly’’’ changes from asynchronous to synchronous operation, then the respective control/enable pin data must be preclocked via CPÐIN and held steady prior to and during any low to high transition of the MODEÐSO or MODEÐSC to properly initiate the sync control registers for synchronous control mode. The 74ABT3284 is a bi-directional registered data-path routing device which can multiplex/de-multiplex four 9-bit ‘‘Aside’’ data ports (Ports A, B, C, D) onto/from one 9-bit ‘‘Xside’’ port (Port X). Alternatively, it can be configured for mux/demux of two 18-bit data paths (Ports A and C, B and D) onto/from one 18-bit data path (Ports X and Y). Each of the six 9-bit I/O ports have independent active low TRI-STATEÉ output enable control logic which can be configured to operate asynchronously or synchronously. With MODEÐSO low, direct asynchronous output control is provided. With MODEÐSO high, output enable control is asserted synchronously on the positive edge of the CPÐIN clock. All I/O port inputs are continuously active allowing output state feedback. The four A-side ports (A, B, C, D) contain independently enabled input and output data registers for storage of data passing in either direction. The input register (AIR, BIR, CIR, DIR) is loaded/held on the positive edge of CPÐAX when the respective Load Control pin (LDAI, LDBI, LDCI, LDDI) is asserted high/low. The Input Registers can be loaded with data from the corresponding A-side port. The output register (AOR, BOR, COR, DOR) is loaded/held on the positive edge of CPÐXA when the respective Load Control pin (LDAO, LDBO, LDCO, LDDO) is asserted high/low. The Output Registers can be loaded with data from Port X when MODEÐWS is asserted low. When MODEÐWS is asserted high, the Output Registers A and C can be loaded with Port X data and the B and D Output Registers can be loaded with data from Port Y. When routing data from A-side to X-side, Data Path Control is provided for the following options via the SA2X inputs; Transparent mode where Input Register is bypassed but can simultaneously monitor A-side data; Registered Mode where X-side receives data from the selected Input Registers; Readback Mode where X-side receives data from the selected Output Registers. A-side data from Ports A, B, C, or D can be selected to Port X via the XSEL data path select inputs. Ports B or D can be selected to Port Y via the YSEL data path select input. When routing data from X-side to A-side, Data Path Control is provided for the following options via the ASEL inputs; Transparent mode where Output Register is bypassed but can simultaneously monitor X-side data; Registered Mode where the A-side Port receives data from the corresponding Output Register; Readback Mode where the A-side Port receives data from the corresponding Input Registers. MODEÐWS asserted low selects Port X data to be passed to Ports A, B, C, and D. With MODEÐWS asserted high, Port X data is passed to Ports A and C with Port Y data passed to Ports B and D. Pin Descriptions Pin Name 2 Description Operation OEa Output Enable Inputs (Active Low) Sync/Async LDaI Load Enable Inputs for the Input Registers Sync/Async LDaO Load Enable Inputs for the Output Registers Sync/Async ASEL(0,1) A-Side Data Path Select Inputs Sync/Async SA2X(0,1) X-Side Data Path Select Inputs Sync/Async XSEL(0,1) X-Port Data Path Select Inputs Sync/Async YSEL Y-Port Data Path Select Input Sync/Async MODEÐW Word Mode Select Input for the X/Y to A-Side Direction Sync/Async MODEÐSO Enable Input for Synchronous Output Enable Control Async MODEÐSC Enable Input for Synchronous Data Path Control Async CPÐIN Clock Input for Synchronous Control (Positive Edge Trigger) CPÐAX Clock Input for Input Registers (Positive Edge Trigger) CPÐXA Clock Input for Output Registers (Positive Edge Trigger) Function Tables Output Enable Control Table Inputs Outputs Control Mode Function OE (A, B, C, D, X, Y) MODEÐSO CPÐIN Port A, B, C, D, X, Y L L X ENABLE ASYNC ENABLED OUTPUT, I/O input always active DISABLED OUTPUT, I/O input always active H L X DISABLE ASYNC (Notes 2, 3) H (Note 1) L (Note 3) SYNC (Note 3) Note 1: Low to High transitions of MODEÐSO must be immediately preceeded by a low to high transition (clock edge) on CPÐIN while holding Synchronous Control Inputs OE (A, B, C, D, X, Y) steady to preset internal registers and assure predictable operation during the control mode change from asynchronous to synchronous. Note 2: OE (A, B, C, D, X, Y) levels are synchronously asserted by the positive transition of CPÐIN when MODEÐSO is high. Note 3: Synchronous Control Mode Functions are same as Asynchronous at time T a 1 of CPÐIN. A Side Data Path Select Function Table Inputs Data Path Function ASEL(0) MODEÐSC CPÐIN L L L X (A, B, C, D) IR A, B, C, D ASYNC Readback; Contents of Input Register (A, B, C, D) IR to Port (A, B, C, D) L H L X (A, B, C, D) OR A, B, C, D ASYNC Clocked Path; Contents of Output Register (A, B, C, D) OR to Port (A, B, C, D) H L L X Port X A, B, C, & D ASYNC Transparent Path; Port X to Port A, B, C, & D H H L X Port X A&C ASYNC Port Y B&D Transparent Path; Port X to Port A & C Transparent Path; Port Y to Port B & D (Note 3) (Note 3) (Notes 2, 3) (Notes 2, 3) H (Note 1) L To Port Control Mode ASEL(1) From Reg/Port SYNC (Note 3) Note 1: Low to High transitions of MODEÐSC must be immediately preceeded by a low to high transition (clock edge) on CPÐIN while holding Synchronous Control Inputs ASEL(0) and ASEL(1) steady to preset internal registers and assure predictable operation during the control mode change from asynchronous to synchronous. Note 2: ASEL(0) and ASEL(1) levels are synchronously asserted by the positive transition of CPÐIN when MODEÐSC is high. Note 3: Synchronous Control Mode Functions are same as Asynchronous at time T a 1 of CPÐIN. Input Register Control Table Inputs Register Control Mode Function Port (A, B, C, D) LD(A, B, C, D) I MODEÐSC CPÐIN X L L X L HOLD ASYNC HOLD; Input Register holds previous state. L (H) H L X L L (H) ASYNC LOAD; Port A, B, C, D clocked to Input Register (A, B, C, D) IR via CPÐAX positive edge (Note 3) (Notes 2, 3) H (Note 1) L (Note 3) (Note 3) SYNC CPÐXA (A, B, C, D) IR (Note 3) Note 1: Low to High transitions of MODEÐSO must be immediately preceeded by a low to high transition (clock edge) on CPÐIN while holding Synchronous Control Inputs LDAI, LDBI, LDCI, and LDDI steady to preset internal registers and assure predictable operation during the control mode change from asynchronous to synchronous. Note 2: LDAI, LDBI, LDCI and LDDI levels are synchronously asserted by the positive transition of CPÐIN when MODEÐSC is high. Note 3: Synchronous Control Mode Functions are same as Asynchronous at time T a 1 of CPÐIN. 3 Function Tables (Continued) Output Register Control Table Inputs Output Register Port Y LD(A, B, C, D) O MODEÐW X X L X L X L HOLD HOLD ASYNC HOLD OR L (H) X H L L X L L (H) L (H) ASYNC LOAD OR Port X to OR (A, B, C, D) L (H) L (H) H H L X L L (H) L (H) ASYNC LOAD OR Port X to OR (A, C) Port Y to OR (B, D) (Notes 2, 3) (Notes 2, 3) H (Note 1) L (Note 3) (Note 3) (Note 3) SYNC (Note 3) (Note 3) (Note 3) MODEÐSC CPÐIN CPÐXA (A, C) OR (B, D) OR Control Function Mode Port X Note 1: Low to High transitions of MODEÐSC must be immediately preceeded by a low to high transition (clock edge) on CPÐIN while holding Synchronous Control Inputs LDAO, LDBO, LDCO, LDDO and MODEÐW steady to preset internal registers and assure predictable operation during the control mode change from asynchronous to synchronous. Note 2: LDAO, LDBO, LDCO, LDDO and MODEÐW levels are synchronously asserted by the positive transition of CPÐIN when MODEÐSC is high. Note 3: Synchronous Control Mode Functions are same as Asynchronous at time T a 1 of CPÐIN. 4 Function Tables (Continued) 1st Level X Side Data Path Select Function Table Inputs Data Path To Internal Node Control Mode Function SA2X(1) SA2X(0) MODEÐSC CPÐIN From Reg/Port L L L X A, B, C, D (A, B, C, D) X ASYNC Transparent datapath from Port (A, B, C, D) to internal node (A, B, C, D) X L H L X (A, B, C, D) IR (A, B, C, D) X ASYNC Clocked Path; Contents of Input Register (A, B, C, D) IR to internal node (A, B, C, D) X H L L X (A, B, C, D) OR (A, B, C, D) X ASYNC Readback; contents of Output register (A, B, C, D) OR to internal node (A, B, C, D) X H H L X GND (A, B, C, D) X ASYNC Diagnostic; Select all 36 bits as low and pass to the internal node (A, B, C, D) X (Notes 2, 3) (Notes 2, 3) H (Note 1) L (Note 3) (Note 3) SYNC (Note 3) Note 1: Low to High transitions of MODEÐSC must be immediately preceeded by a low to high transition (clock edge) on CPÐIN while holding Synchronous Control Inputs SA2X(0) and SA2X(1) steady to preset internal sync registers and assure predictable operation during the control mode change from asynchronous to synchronous. Note 2: SA2X(0) and SA2X(1) levels are synchronously asserted by the positive transition of CPÐIN when MODEÐSC is high. Note 3: Synchronous Control Mode Functions are same as Asynchronous at time T a 1 of CPÐIN. 2nd Level X Side Data Path Select Function Table for Port X Inputs Data Path Control Mode Function X ASYNC Internal Node AX to Port X X ASYNC Internal Node BX to Port X Internal Node CX to Port X XSEL(0) MODEÐSC CPÐIN From Internal Node To Port L L L X AX L H L X BX XSEL(1) H L L X CX X ASYNC H H L X DX X ASYNC (Notes 2, 3) (Notes 2, 3) H (Note 1) L (Note 3) (Note 3) SYNC Internal Node DX to Port X (Note 3) Note 1: Low to High transitions of MODEÐSC must be immediately preceeded by a low to high transition (clock edge) on CPÐIN while holding Synchronous Control Inputs XSEL(0) and XSEL(1) steady to preset internal sync registers and assure predictable operation during the control mode change from asynchronous to synchronous. Note 2: XSEL(0) and XSEL(1) levels are synchronously asserted by the positive transition of CPÐIN when MODEÐSC is high. Note 3: Synchronous Control Mode Functions are same as Asynchronous at time T a 1 of CPÐIN. 2nd Level X Side Data Path Select Function Table for Port Y Inputs YSEL MODEÐSC Data Path CPÐIN From Internal Node To Port Control Mode Function L L X BX Y ASYNC Internal Node BX to Port Y H L X DX Y ASYNC Internal Node DX to Port Y (Notes 2, 3) H (Note 1) L (Note 3) (Note 3) SYNC (Note 3) Note 1: Low to High transitions of MODEÐSC must be immediately preceeded by a low to high transition (clock edge) on CPÐIN while holding Synchronous Control Inputs YSEL steady to preset internal registers and assure predictable operation during the control mode change from asynchronous to synchronous. Note 2: YSEL levels are synchronously asserted by the positive transition of CPÐIN when MODEÐSC is high. Note 3: Synchronous Control Mode Functions are same as Asynchronous at time T a 1 of CPÐIN. 5 Logic Diagrams TL/F/11582 – 2 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. FIGURE 1. 18-Bit Synchronous Datapath Multiplexer 6 Logic Diagrams (Continued) Note: Port C configured identical to Port A. TL/F/11582 – 3 FIGURE 2. Synchronous Bus Multiplexer A-X Datapath Note: Port D configured identical to Port B. TL/F/11582 – 4 FIGURE 3. Synchronous Bus Multiplexer B PORT Datapath 7 Absolute Maximum Ratings (Note 1) Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias b 55§ C to a 125§ C Junction Temperature under Bias Ceramic Plastic b 0.5V to a 7.0V Input Voltage (Note 2) b 0.5V to a 7.0V Input Current (Note 2) b 30 mA to a 5.0 mA Voltage Applied to Any Output in the Disabled or Power-off State in the HIGH STATE Current Applied to Output in LOW State (Max) 10V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. b 55§ C to a 175§ C b 55§ C to a 150§ C VCC Pin Potential to Ground Pin b 300 mA DC Latchup Source Current Over Voltage Latchup (I/O) Note 2: Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions b 0.5V to a 5.5V b 0.5V to VCC Free Air Ambient Temperature Commercial b 40§ C to a 85§ C Supply Voltage Commercial a 4.5V to a 5.5V Minimum Input Edge Rate Data Input Enable Input Clock Input twice the rated IOL (mA) (DV/Dt) 50 mV/ns 20 mV/ns 100 mV/ns DC Electrical Characteristics Symbol Parameter ABT3284 Min Typ Units Max 2.0 VCC V Conditions VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Voltage VOH Output HIGH Voltage VOL Output LOW Voltage 0.55 V Min IIH Input HIGH Current 5 mA Max IOL e 64 mA (Note 4) VIN e VCC IBVI Input HIGH Current Breakdown Test 7 mA Max VIN e 7.0V Control Inputs IBVIT Input HIGH Current Breakdown Test (I/O) 100 mA Max VIN e 5.5V (An, Bn, Cn, Dn, Xn, Yn) IIL Input LOW Current b5 mA Max VIN e 0.5V Control Inputs VID Input Leakage Test V 0.0 IID e 1.9 mA Control Inputs All Data Pins Grounded IIH a IOZH Output Leakage Current 50 mA 0 – 5.5 VOUT e 2.7V (An, Bn, Cn, Dn, Xn, Yn) All Output Enables e 2.0V IIL a IOZL Output Leakage Current b 50 mA 0 – 5.5 VOUT e 0.5V (An, Bn, Cn, Dn, Xn, Yn) All Output Enables e 2.0V IOS Output Short-Circuit Current b 275 mA Max ICEX Output High Leakage Current 50 mA Max IZZ Bus Drainage Test 100 mA 0.0 VOUT e 0.0V (An, Bn, Cn, Dn, Xn, Yn) (Note 5) VOUT e VCC (An, Bn, Cn, Dn, Xn, Yn) VOUT e 5.5V (An, Bn, Cn, Dn, Xn, Yn) ICCH Power Supply Current 2.5 mA Max All Outputs HIGH ICCL Power Supply Current 140 mA Max 36 Outputs LOW ICCZ Power Supply Current 2.5 mA Max Output Enables e VCC; All Others at GND ICCT Additional ICC/Input 2.5 mA Max VIN e VCC b 2.1V All Others at VCC or GND ICCD Dynamic ICC No Load 0.35 mA/ MHz Max Outputs Open, Transparent Mode Output Enables e GND One Bit Toggling, 50% Duty Cycle V b 1.2 V Min V Min 2.5 2.0 4.75 b 100 Recognized HIGH Signal 0.8 Recognized LOW Signal IIN e b18 mA IOH e b3 mA IOH e b32 mA (Note 3) Note 3: Up to 18 outputs can each source 32 mA continuously, or any combination of outputs can source up to a total of 324 mA. For example, 36 outputs can continuously each source 16 mA. Note 4: Up to 18 outputs can each sink 64 mA continuously, or any combination of outputs can sink up to a total of 648 mA. For example, 36 outputs can continuously each sink 32 mA. Note 5: One output at a time, duration 1 second maximum. 8 DC Electrical Characteristics Symbol (Continued) Parameter Min Typ Max 0.7 1.0 b 0.8 b 0.5 Units VCC Conditions CL e 50 pF, RL e 500X VOLP Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL VOHV Minimum High Level Dynamic Output Voltage 2.5 3.0 V 5.0 TA e 25§ C (Note 3) VIHD Minimum High Level Dynamic Input Voltage 2.0 1.7 V 5.0 TA e 25§ C (Note 2) VILD Maximum Low Level Dynamic Input Voltage V 5.0 TA e 25§ C (Note 2) 1.2 0.8 V 5.0 TA e 25§ C (Note 1) V 5.0 TA e 25§ C (Note 1) Note 1: Max number of outputs defined as (n). n b 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 2: Max number of data inputs (n) switching. n b 1 inputs switching 0V to 3V. Input-under-test switching: 3V to theshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested. Note 3: Max number of outputs defined as (n). n b 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. AC Electrical Characteristics Single Output Switching Symbol Parameter 74ABT 74ABT TA e 25§ C VCC e 5.0V CL e 50 pF TA e b40§ C to a 85§ C VCC e 4.5V to 5.5V CL e 50pF Min Units Max Min Max 1.5 5.5 1.5 5.5 ns Propagation Delay B, D or Y Inputs to Y or B, D Outputs. Transparent Mode 1.0 5.0 1.0 5.0 ns tPHL tPLH Propagation Delay CPÐXAu to A, B, C, or D. Registered Mode 1.5 6.0 1.5 6.0 ns tPHL tPLH Propagation Delay CPÐAXu to X. Registered Mode 1.5 7.0 1.5 7.0 ns tPHL tPLH Propagation Delay CPÐAXu to Y. Registered Mode 1.5 6.5 1.5 6.5 ns tPHL tPLH Propagation Delay ASELn to A, B, C or D. Asynchronous Mode 2.0 7.5 2.0 7.5 ns tPHL tPLH Propagation Delay CPÐINu to A, B, C or D. ASELn Synchronous Mode 2.5 8.5 2.5 8.5 ns tPHL tPLH Propagation Delay SA2Xn to X or Y. Asynchronous Mode 1.5 7.5 1.5 7.5 ns tPHL tPLH Propagation Delay CPÐINu to X or Y. SA2Xn Synchronous Mode 2.0 8.5 2.0 8.5 ns tPHL tPLH Propagation Delay XSELn to X. Asynchronous Mode 1.5 6.0 1.5 6.0 ns tPHL tPLH Propagation Delay CPÐINu to X. XSELn Synchronous Mode 2.0 7.5 2.0 7.5 ns tPHL tPLH Propagation Delay YSELn to Y. Asynchronous Mode 1.0 5.5 1.0 5.5 ns tPHL tPLH Propagation Delay CPÐINu to Y. YSELn Synchronous Mode 1.5 6.5 1.5 6.5 ns tPZH tPZL Asynchronous Enable Time 1.0 6.0 1.0 6.0 ns tPZH tPZL Synchronous Enable Time 1.5 7.0 1.5 7.0 ns tPHZ tPLZ Asynchronous Disable Time 1.0 7.5 1.0 7.5 ns tPHZ tPLZ Synchronous Disable Time 1.5 8.5 1.5 8.5 ns fMAX Max Operating Frequency 150 tPHL tPLH Propagation Delay A, B, C, D or X Inputs to X or A, B, C, D Outputs. Transparent Mode tPHL tPLH 9 AC Operating Requirements Single Output Switching Symbol Parameter 74ABT 74ABT TA e 25§ C VCC e 5.0V CL e 50 pF TA e b40§ C to a 85§ C VCC e 4.5V to 5.5V CL e 50 pF Units Min Max ts(H) ts(L) Setup Time High or Low A, B, C, D X or Y. Data to CPÐAXu or CPÐXAu (Registered Mode) 4.0 4.0 ns th(H) th(L) Hold Time High or Low A, B, C, D X or Y. Data to CPÐAXu or CPÐXAu (Registered Mode) 0.0 0.0 ns ts(H) ts(L) Setup Time High or Low Control Inputs to CPÐINu. (Synchronous Mode) 3.0 3.0 ns th(H) th(L) Hold Time High or Low Control Inputs to CPÐINu. (Synchronous Mode) 0.0 0.0 ns ts(H) Setup Time High, CPÐINu to CPÐAXu or CPÐXAu. 5.0 5.0 ns th(L) Hold Time Low, CPÐINu to CPÐAXu or CPÐXAu. 0.0 0.0 ns tw(H) tw (L) CLK Pulsewidth High CLK Pulsewidth Low 3.0 4.0 3.0 4.0 ns Capacitance Parameter Typ Units Conditions TA e 25§ C CIN Input Capacitance 5 pF VCC e 0V Control Inputs CI/O (Note 1) I/O Capacitance 11 pF VCC e 5.0V (An, Bn, Cn, Dn, Xn, Yn) Symbol Note 1: CI/O is measured at frequency f e 1 MHz, per MIL-STD-883B, Method 3012. 10 11 74ABT3284 18-Bit Synchronous Datapath Multiplexer Physical Dimensions inches (millimeters) 100-Lead Thin Quad Flatpak (TQFP) NS Package Number VJG100A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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