SEMICONDUCTOR TECHNICAL DATA ! " High–Performance Silicon–Gate CMOS The MC54/74HC646 is identical in pinout to the LS646. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These devices are bus transceivers with D flip–flops. Depending on the status of the Data–Source Selection pins, data may be routed to the outputs either from the flip–flops or transmitted real–time from the inputs (see Function Table and Application Information). The Output Enable and the Direction pins control the transceiver’s function. Bus A and Bus B cannot be routed as outputs to each other simultaneously, but can be routed as inputs to the A and B flip–flops. Also, the A and B flip–flops can be routed as outputs to Bus A and Bus B. Additionally, when either or both of the ports are in the high–impedance state, these I/O pins may be used as inputs to the D flip–flops for data storage. The user should note that because the clocks are not gated with the Direction and Output Enable pins, data at the A and B ports may be clocked into the storage flip–flops at any time. • • • • • • Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 µA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A • Chip Complexity: 780 FETs or 195 Equivalent Gates 1 A DATA PORT 4 5 6 7 8 9 10 11 OUTPUT ENABLE DIRECTION FLIP–FLOP CLOCKS DATA SOURCE SELECTION INPUTS A–TO–B CLOCK B–TO–A CLOCK A–TO–B SOURCE B–TO–A SOURCE 20 19 18 17 16 15 14 13 B0 B1 B2 B3 B4 B5 B6 B7 1 1 ORDERING INFORMATION MC54HCXXXJ MC74HCXXXN MC74HCXXXDW A–TO–B CLOCK A–TO–B SOURCE DIRECTION B DATA PORT 3 1 23 2 PIN 24 = VCC PIN 12 = GND 3–1 Ceramic Plastic SOIC PIN ASSIGNMENT 10/95 Motorola, Inc. 1995 DW SUFFIX SOIC PACKAGE CASE 751E–04 24 21 22 N SUFFIX PLASTIC PACKAGE CASE 724–03 24 LOGIC DIAGRAM A0 A1 A2 A3 A4 A5 A6 A7 J SUFFIX CERAMIC PACKAGE CASE 758–02 24 REV 6 1 24 2 23 3 22 A0 4 21 VCC B–TO–A CLOCK B–TO–A SOURCE OUTPUT ENABLE A1 5 20 B0 A2 6 19 B1 A3 7 18 B2 A4 8 17 B3 A5 9 16 B4 A6 10 15 B5 A7 11 14 B6 GND 12 13 B7 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MC54/74HC646 MAXIMUM RATINGS* Symbol VCC Parameter DC Supply Voltage (Referenced to GND) Value Unit – 0.5 to + 7.0 V V Vin DC Input Voltage (Referenced to GND) – 1.5 to VCC + 1.5 VI/O DC I/O Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V Iin DC Input Current, per Pin ± 20 mA II/O DC I/O Current, per Pin ± 35 mA ICC DC Supply Current, VCC and GND Pins ± 75 mA PD Power Dissipation in Still Air, Plastic or Ceramic DIP† SOIC Package† 750 500 mW Tstg Storage Temperature – 65 to + 150 _C TL This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. v _C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) (Ceramic DIP) 260 300 v * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C Ceramic DIP: – 10 mW/_C from 100_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ v v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ v ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter Min Max Unit 2.0 6.0 V DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) 0 VCC V – 55 + 125 _C 0 0 0 1000 500 400 ns VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V – 55 to 25_C 85_C 125_C Unit VIH Minimum High–Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low–Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| 20 µA 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V Minimum High–Level Output Voltage Vin = VIH or VIL |Iout| 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.70 5.20 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 4.5 6.0 0.26 0.26 0.33 0.33 0.40 0.40 6.0 ± 0.1 ± 1.0 ± 1.0 VOH Vin = VIH or VIL |Iout| |Iout| VOL Maximum Low–Level Output Voltage Vin = VIH or VIL |Iout| 20 µA Vin = VIH or VIL |Iout| |Iout| Iin MOTOROLA Maximum Input Leakage Current 6.0 mA 7.8 mA 6.0 mA 7.8 mA Vin = VCC or GND (Pins 1, 2, 3, 21, 22, and 23) 3–2 V µA High–Speed CMOS Logic Data DL129 — Rev 6 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ v v ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MC54/74HC646 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC V – 55 to 25_C Output in High–Impedance State Vin = VIL or VIH Vout = VCC or GND, I/O Pins 6.0 ± 0.5 ± 5.0 ± 10 µA Vin = VCC or GND Iout = 0 µA 6.0 8 80 160 µA Symbol Parameter Test Conditions IOZ Maximum Three–State Leakage Current ICC Maximum Quiescent Supply Current (per Package) 85_C 125_C Unit NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). High–Speed CMOS Logic Data DL129 — Rev 6 3–3 MOTOROLA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ v ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MC54/74HC646 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit VCC V – 55 to 25_C 85_C 125_C Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 3, 4 and 9) 2.0 4.5 6.0 6.0 30 35 4.8 24 28 4.0 20 24 MHz tPLH, tPHL Maximum Propagation Delay, Input A to Output B (or Input B to Output A) (Figures 1, 2 and 9) 2.0 4.5 6.0 170 34 29 215 43 37 255 51 43 ns tPLH, tPHL Maximum Propagation Delay, A–to–B Clock to Output B (or B–to–A Clock to Output A) (Figures 3, 4 and 9) 2.0 4.5 6.0 220 44 37 275 55 47 330 66 56 ns tPLH, tPHL Maximum Propagation Delay, A–to–B Source to Output B (or B–to–A Source to Output A) (Figures 5, 6 and 9) 2.0 4.5 6.0 170 34 29 215 43 37 255 51 43 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to Output A or B (Figures 7, 8 and 10) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 ns tPZL, tPZH Maximum Propagation Delay, Direction or Output Enable to Output A or B (Figures 7, 8 and 10) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 9) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns Maximum Input Capacitance — 10 10 10 pF Maximum Three–State Output Capacitance (Output in High–Impedance State) — 15 15 15 pF Symbol Cin Cout Parameter NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Channel)* pF 60 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ v ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ * Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). TIMING REQUIREMENTS (Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V – 55 to 25_C 85_C 125_C Unit tsu Minimum Setup Time, Input A to A–to–B Clock (or Input B to B–to–A Clock) (Figures 3 and 4) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns th Minimum Hold Time, A–to–B Clock to Input A (or B–to–A Clock to Input B) (Figures 3 and 4) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns tw Minimum Pulse Width, A–to–B Clock (or B–to–A Clock) (Figures 3 and 4) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns Maximum Input Rise and Fall Times (Figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns tr, tf NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). MOTOROLA 3–4 High–Speed CMOS Logic Data DL129 — Rev 6 MC54/74HC646 FUNCTION TABLE — HC646 Control Inputs Output Enable Direc– tion H X A–to–B Clock H, L, B–to–A Clock H, L, Data Port Status A–to–B Source X X L X* X* L B–to–A Source A B X Input: X Input: X no change no change The output functions of the A and B ports are disabled L H X X X X L H L H X X X X L H The ports may be used as inputs to the storage flip–flops. Data at the inputs are clocked into the flip–flops with the rising edge of the Clocks. Input: Output: X H H, L, H, L, X* QA QB Description of Operation The output mode of the B data port is enabled and behaves according to the following logic equation: B = [A • (A–to–B Source)] + [QA • (A–to–B Source)] L X L H L H no change no change no change no change 1.) When A–to–B Source is low, the data at the A data port are displayed at the B data port. The states of the storage flip–flops are not affected. H X X QA no change no change 2.) When A–to–B Source is high, the states of the A storage flip–flops are displayed at the B data port. L X L H L H L H no change no change 3.) When A–to–B Source is low, the data at the A data port are clocked into the A storage flip–flops by a rising–edge signal on the A–to–B Clock. H X L H QA QA L H no change no change 4.) When A–to–B Source is high, the data at the A data port are clocked into the A storage flip–flops by a rising–edge signal on the A–to–B Clock. The states, QA, of the storage flip–flops propagate directly to the B data port. Output: Input: L X* Storage Flip– Flop States The output mode of the A data port is enabled and behaves according to the following logic equation: A = [B • (B–to–A Source)] + [QB • (B–to–A Source)] X L L H L H no change no change no change no change 1.) When B–to–A Source is low, the data at the B data port are displayed at the A data port. The states of the storage flip–flops are not affected. X H QB X no change no change 2.) When B–to–A Source is high, the states of the B storage flip–flops are displayed at the A data port. X L L H L H no change no change L H 3.) When B–to–A Source is low, the data at the B data port are clocked into the B storage flip–flops by a rising–edge signal on the B–to–A Clock. X H QB QB L H no change no change L H 4.) When B–to–A Source is high, the data at the B data port are clocked into the B storage flip–flops by a rising–edge signal on the B–to–A Clock. The states, QB, of the storage flip–flops propagate directly to the A data port. * The clocks are not internally gated with either the Output Enables or the Source inputs. Therefore, data at the A and B ports may be clocked into the storage flip–flops at any time. High–Speed CMOS Logic Data DL129 — Rev 6 3–5 MOTOROLA MC54/74HC646 TYPICAL APPLICATIONS A FLIP– FLOPS BUS A B FLIP– FLOPS BUS B A FLIP– FLOPS BUS A CONTROL LOGIC (3) CONTROL PINS (21) (1) BUS B CONTROL LOGIC (23) DIRECTION OUTPUT A–TO–B B–TO–A ENABLE CLOCK CLOCK X B FLIP– FLOPS (2) (22) CONTROL A–TO–B B–TO–A PINS SOURCE SOURCE H X X Data Storage From A and/or B Bus BUS A (3) (21) (1) (23) DIRECTION OUTPUT ENABLE A–TO–B CLOCK H L X (2) (22) B–TO–A A–TO–B B–TO–A CLOCK SOURCE SOURCE X L X Real–Time Transfer From Bus A to Bus B A FLIP– FLOPS B FLIP– FLOPS BUS B CONTROL LOGIC (3) CONTROL PINS (21) DIRECTION OUTPUT ENABLE L L (1) (23) A–TO–B B–TO–A CLOCK CLOCK X X (2) (22) A–TO–B B–TO–A SOURCE SOURCE X L Real–Time Transfer From Bus B to Bus A MOTOROLA 3–6 High–Speed CMOS Logic Data DL129 — Rev 6 MC54/74HC646 TIMING DIAGRAMS AND SWITCHING DIAGRAMS — HC646 VCC OUTPUT ENABLE GND VCC DIRECTION GND VCC A–TO–B SOURCE GND VCC B–TO–A SOURCE GND tr tf VCC 90% 50% 10% A DATA PORT GND tPLH 90% 50% 10% B DATA PORT tPHL tTLH tTHL Figure 1. A Data Port = Input, B Data Port = Output VCC OUTPUT ENABLE GND VCC DIRECTION GND VCC B–TO–A SOURCE GND VCC A–TO–B SOURCE GND tr tf 90% 50% 10% B DATA PORT VCC GND tPLH tPHL 50% A DATA PORT Figure 2. A Data Port = Output, B Data Port = Input NOTE: = Don’t Care State High–Speed CMOS Logic Data DL129 — Rev 6 3–7 MOTOROLA MC54/74HC646 VCC OUTPUT ENABLE GND VCC DIRECTION GND VCC B–TO–A SOURCE GND VCC A–TO–B SOURCE GND VCC B–TO–A CLOCK GND VCC 50% A DATA PORT GND tsu th VCC 50% A–TO–B CLOCK tw GND 1/fmax tPLH tPHL 50% B DATA PORT Figure 3. A Data Port = Input, B Data Port = Output VCC OUTPUT ENABLE GND VCC DIRECTION GND VCC A–TO–B SOURCE GND VCC B–TO–A SOURCE GND VCC A–TO–B CLOCK GND VCC 50% B DATA PORT GND tsu th VCC 50% B–TO–A CLOCK tw A DATA PORT GND 1/fmax tPLH tPHL 50% Figure 4. B Data Port = Input, A Data Port = Output MOTOROLA 3–8 High–Speed CMOS Logic Data DL129 — Rev 6 MC54/74HC646 VCC OUTPUT ENABLE GND VCC DIRECTION GND VCC INTERNAL QA (FLIP–FLOP A) GND VCC INTERNAL QB (FLIP–FLOP B) GND VCC A–TO–B SOURCE 50% GND VCC B–TO–A SOURCE GND VCC A DATA PORT tPLH GND tPHL 3 tPLH tPHL 50% B DATA PORT 1 2 NOTES: 1. B Data Port (output) changes from the level of the storage flip–flop, QA, to the level of A Data Port (input). 2. B Data Port (output) changes from the level of the A Data Port (input) to the level of the storage flip–flop, QA. 3. The A storage flip–flop, A–to–B Source, and A Data Port (input) have simultaneously changed states. Figure 5. A Data Port = Input, B Data Port = Output High–Speed CMOS Logic Data DL129 — Rev 6 3–9 MOTOROLA MC54/74HC646 VCC OUTPUT ENABLE GND VCC DIRECTION GND VCC INTERNAL QA (FLIP–FLOP A) GND INTERNAL QB (FLIP–FLOP B) VCC A–TO–B SOURCE VCC GND GND VCC B–TO–A SOURCE 50% GND tPLH A DATA PORT tPHL tPLH tPHL 50% 1 2 VCC B DATA PORT GND 3 NOTES: 1. A Data Port (output) changes from the level of the storage flip–flop, QB, to the level of B Data Port (input). 2. A Data Port (output) changes from the level of the B Data Port (input) to the level of the storage flip–flop, QB. 3. The B storage flip–flop, B–to–A Source, and B Data Port (input) have simultaneously changed states for the purpose of this 3. example. A Data Port (output) is now displaying the voltage level of B Data Port (input). Figure 6. A Data Port = Output, B Data Port = Input PIN DESCRIPTIONS INPUTS/OUTPUTS Direction is high, the A data ports are inputs and the B data ports are outputs. When Direction is low, the A data ports are outputs and the B data ports are inputs. A0 – A7 (Pins 4 – 11) and B0 – B7 (Pins 20 – 13) A and B data ports. These pins may function either as inputs to or outputs from the transceivers. A–to–B Clock, B–to–A Clock (Pins 1, 23) Clocks for the internal D flip–flops. With a low–to–high transition on the appropriate Clock pin, data on the A (or B) inputs are clocked into the internal A (or B) flip–flops. These clocks are not internally gated with the Output Enable or the Direction pins, therefore data at the A and B pins may be clocked into the storage flip–flops at any time. CONTROL INPUTS Output Enable (Pin 21) Active–low output enable. When this pin is low, the outputs are enabled and function normally. When this pin is high, the A and B data ports are in high–impedance states. See the Function Table. A–to–B Source, B–to–A Source (Pins 2, 22) Direction (Pin 3) Data–source selection pins. Depending upon the states of these pins (see the Function Table), data at the outputs may come either from the inputs or from the D flip–flops. Data direction control. When the Output Enable pin is low, this control pin determines the direction of data flow. When MOTOROLA 3–10 High–Speed CMOS Logic Data DL129 — Rev 6 MC54/74HC646 VCC OUTPUT ENABLE GND VCC 50% DIRECTION GND tPZH tPHZ 90% VOH 50% DATA PORT A HIGH IMPEDANCE tPZL tPLZ HIGH IMPEDANCE DATA PORT A 50% 10% VOL tPHZ tPZH VOH 90% 50% DATA PORT B HIGH IMPEDANCE tPLZ tPZL HIGH IMPEDANCE DATA PORT B 50% 10% DATA PORT A = INPUT DATA PORT B = OUTPUT VOL DATA PORT A = OUTPUT DATA PORT B = INPUT Figure 7. VCC OUTPUT ENABLE 50% GND tPLZ tPZL OUTPUT A OR B tPZH OUTPUT A OR B HIGH IMPEDANCE 50% tPHZ 10% VOL 90% VOH 50% HIGH IMPEDANCE Figure 8. TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST OUTPUT DEVICE UNDER TEST CL* * Includes all probe and jig capacitance CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. * Includes all probe and jig capacitance Figure 9. Test Circuit High–Speed CMOS Logic Data DL129 — Rev 6 1 kΩ Figure 10. Test Circuit 3–11 MOTOROLA MC54/74HC646 LOGIC DETAIL D C C Q VCC HC648 A Q HC646 HC646 20 A0 4 VCC B0 TAB TAB SAB CAB CAB HC648 Q HC648 D B HC646 Q C C HC646 A1 A2 A3 A4 A5 A6 A7 CBA CBA SBA TBA TBA HC648 5 19 6 18 7 17 8 16 9 15 10 14 11 13 TBA SBA SAB DIRECTION OUTPUT ENABLE 22 2 B1 B2 B3 B4 B5 B6 B7 B–TO–A SOURCE A–TO–B SOURCE 3 21 TBA TAB CBA CBA 23 B–TO–A CLOCK CAB TAB MOTOROLA 3–12 CAB 1 A–TO–B CLOCK High–Speed CMOS Logic Data DL129 — Rev 6 MC54/74HC646 OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 758–02 ISSUE A L B 24 13 1 12 P NOTES: 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 4. CONTROLLING DIMENSION: INCH. 5. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. J –A– DIM A B C D F G J K L N P N C –T– K SEATING PLANE G INCHES MIN MAX 1.240 1.285 0.285 0.305 0.160 0.200 0.015 0.021 0.045 0.062 0.100 BSC 0.008 0.013 0.100 0.165 0.300 0.310 0.020 0.050 0.360 0.400 MILLIMETERS MIN MAX 31.50 32.64 7.24 7.75 4.07 5.08 0.38 0.53 1.14 1.57 2.54 BSC 0.20 0.33 2.54 4.19 7.62 7.87 0.51 1.27 9.14 10.16 F D 24 PL 0.25 (0.010) M T A M N SUFFIX PLASTIC PACKAGE CASE 724–03 ISSUE D –A– 24 13 1 12 NOTES: 1. CHAMFERED CONTOUR OPTIONAL. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 4. CONTROLLING DIMENSION: INCH. –B– L C –T– NOTE 1 K SEATING PLANE N E G M J F D High–Speed CMOS Logic Data DL129 — Rev 6 0.25 (0.010) 24 PL 0.25 (0.010) 24 PL M T A M 3–13 M T B M DIM A B C D E F G J K L M N INCHES MIN MAX 1.230 1.265 0.250 0.270 0.145 0.175 0.015 0.020 0.050 BSC 0.040 0.060 0.100 BSC 0.007 0.012 0.110 0.140 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 31.25 32.13 6.35 6.85 3.69 4.44 0.38 0.51 1.27 BSC 1.02 1.52 2.54 BSC 0.18 0.30 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 MOTOROLA MC54/74HC646 OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751E–04 ISSUE E –A– 24 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. 13 –B– 12X P 0.010 (0.25) 1 M B M 12 24X D J 0.010 (0.25) M T A S B S F R C –T– SEATING PLANE M 22X K G X 45 _ DIM A B C D F G J K M P R MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029 Motorola reserves the right to make changes without further notice to any products herein. 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Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 MFAX: [email protected] –TOUCHTONE (602) 244–6609 INTERNET: http://Design–NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MOTOROLA ◊ CODELINE 3–14 *MC54/74HC646/D* MC54/74HC646/D High–Speed CMOS Logic Data DL129 — Rev 6