Order this document by MMBFU310LT1/D SEMICONDUCTOR TECHNICAL DATA N–Channel 2 SOURCE Motorola Preferred Device 3 GATE 1 DRAIN 3 MAXIMUM RATINGS Rating 1 Symbol Value Unit Drain–Source Voltage VDS 25 Vdc Gate–Source Voltage VGS 25 Vdc IG 10 mAdc Symbol Max Unit Total Device Dissipation FR– 5 Board(1) TA = 25°C Derate above 25°C PD 225 mW 1.8 mW/°C Thermal Resistance, Junction to Ambient RqJA 556 °C/W TJ, Tstg – 55 to +150 °C Gate Current 2 CASE 318 – 08, STYLE 10 SOT– 23 (TO – 236AB) THERMAL CHARACTERISTICS Characteristic Junction and Storage Temperature DEVICE MARKING MMBFU310LT1 = 6C ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Max Unit V(BR)GSS – 25 — Vdc Gate 1 Leakage Current (VGS = –15 Vdc, VDS = 0) IG1SS — – 150 pA Gate 2 Leakage Current (VGS = –15 Vdc, VDS = 0, TA = 125°C) IG2SS — – 150 nAdc VGS(off) – 2.5 – 6.0 Vdc IDSS 24 60 mAdc VGS(f) — 1.0 Vdc Forward Transfer Admittance (VDS = 10 Vdc, ID = 10 mAdc, f = 1.0 kHz) |Yfs| 10 18 mmhos Output Admittance (VDS = 10 Vdc, ID = 10 mAdc, f = 1.0 kHz) |yos| — 250 µmhos Input Capacitance (VGS = –10 Vdc, VDS = 0 Vdc, f = 1.0 MHz) Ciss — 5.0 pF Reverse Transfer Capacitance (VGS = –10 Vdc, VDS = 0 Vdc, f = 1.0 MHz) Crss — 2.5 pF OFF CHARACTERISTICS Gate–Source Breakdown Voltage (IG = –1.0 µAdc, VDS = 0) Gate Source Cutoff Voltage (VDS = 10 Vdc, ID = 1.0 nAdc) ON CHARACTERISTICS Zero–Gate–Voltage Drain Current (VDS = 10 Vdc, VGS = 0) Gate–Source Forward Voltage (IG = 10 mAdc, VDS = 0) SMALL–SIGNAL CHARACTERISTICS 1. FR– 5 = 1.0 0.75 0.062 in. Thermal Clad is a trademark of the Bergquist Company Preferred devices are Motorola recommended choices for future use and best overall value. Motorola Small–Signal Transistors, FETs and Diodes Device Data Motorola, Inc. 1996 1 MMBFU310LT1 50 Ω SOURCE 50 Ω LOAD U310 C3 L2P L1 L2S C2 C1 C4 C6 C5 C7 1.0 k RFC +VDD C1 = C2 = 0.8 – 10 pF, JFD #MVM010W. C3 = C4 = 8.35 pF Erie #539–002D. C5 = C6 = 5000 pF Erie (2443–000). C7 = 1000 pF, Allen Bradley #FA5C. RFC = 0.33 µH Miller #9230–30. L1 = One Turn #16 Cu, 1/4″ I.D. (Air Core). L2P = One Turn #16 Cu, 1/4″ I.D. (Air Core). L2S = One Turn #16 Cu, 1/4″ I.D. (Air Core). 60 VDS = 10 V TA = – 55°C 50 50 + 25°C IDSS + 25°C 40 40 30 30 +150°C 20 20 + 25°C – 55°C 10 –5.0 +150°C 10 0 0 –1.0 –4.0 –3.0 –2.0 ID – VGS, GATE–SOURCE VOLTAGE (VOLTS) IDSS – VGS, GATE–SOURCE CUTOFF VOLTAGE (VOLTS) 35 30 20 +150°C 15 + 25°C – 55°C 10 +150°C 5.0 0 5.0 4.0 0 10 10 120 RDS CAPACITANCE (pF) Yos VGS(off) = – 2.3 V = VGS(off) = – 5.7 V = 96 7.0 72 Cgs 4.0 48 24 Cgd 1.0 100 0.01 1.0 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 ID, DRAIN CURRENT (mA) Figure 4. Common–Source Output Admittance and Forward Transconductance versus Drain Current 2 Yos, OUTPUT ADMITTANCE (µ mhos) Yfs , FORWARD TRANSCONDUCTANCE (µmhos) 100 1.0 k 1.0 2.0 Figure 3. Forward Transconductance versus Gate–Source Voltage Yfs 10 k 3.0 VGS, GATE–SOURCE VOLTAGE (VOLTS) 1.0 k Yfs + 25°C 25 Figure 2. Drain Current and Transfer Characteristics versus Gate–Source Voltage 100 k TA = – 55°C VDS = 10 V f = 1.0 MHz R DS , ON RESISTANCE (OHMS) I D , DRAIN CURRENT (mA) 60 IDSS, SATURATION DRAIN CURRENT (mA) 70 70 Yfs , FORWARD TRANSCONDUCTANCE (mmhos) Figure 1. 450 MHz Common–Gate Amplifier Test Circuit 0 10 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 0 VGS, GATE SOURCE VOLTAGE (VOLTS) Figure 5. On Resistance and Junction Capacitance versus Gate–Source Voltage Motorola Small–Signal Transistors, FETs and Diodes Device Data MMBFU310LT1 |S21|, |S11| 0.85 0.45 2.4 0.79 0.39 |S12|, |S22| 0.060 1.00 S22 VDS = 10 V ID = 10 mA TA = 25°C 24 3.0 0.048 0.98 S21 Y11 18 1.8 Y21 12 1.2 0.73 0.33 VDS = 10 V ID = 10 mA TA = 25°C 0.67 0.27 0.024 0.94 0.61 0.21 0.6 0.012 0.92 S12 Y12 0 100 200 300 500 f, FREQUENCY (MHz) 700 0.55 0.15 100 1000 Figure 6. Common–Gate Y Parameter Magnitude versus Frequency θ22 160° 40° 200 300 500 f, FREQUENCY (MHz) – 40° 0.90 θ21, θ22 θ11, θ12 – 20° 120° 86° – 40° 100° 85° – 60° 80° – 120° 84° – 80° 60° – 100° 40° – 120° 20° 100 0 θ11 – 20° θ21 700 1000 Figure 7. Common–Gate S Parameter Magnitude versus Frequency θ12, θ22 – 20° 87° θ21, θ11 180° 50° 170° 0.036 0.96 S11 Y22 6.0 Y12 (mmhos) |Y11|, |Y21 |, |Y22 | (mmhos) 30 θ21 θ22 – 20° – 60° 30° – 80° – 40° – 100° 20° 140° 10° θ12 θ11 130° 0° 100 – 140° VDS = 10 V ID = 10 mA TA = 25°C 200 300 500 f, FREQUENCY (MHz) – 180° – 200° 82° 1000 Figure 8. Common–Gate Y Parameter Phase–Angle versus Frequency 8.0 24 7.0 21 6.0 18 15 5.0 Gpg 12 4.0 NF 9.0 3.0 6.0 2.0 3.0 1.0 0 4.0 6.0 8.0 θ11 200 300 500 f, FREQUENCY (MHz) 700 – 80° – 100° 1000 26 VDD = 20 V f = 450 MHz BW ≈ 10 MHz CIRCUIT IN FIGURE 1 NF, NOISE FIGURE (dB) 6.0 VDS = 10 V ID = 10 mA TA = 25°C Figure 9. S Parameter Phase–Angle versus Frequency G pg , POWER GAIN (dB) NF, NOISE FIGURE (dB) 7.0 – 60° θ12 – 160° 83° 700 θ21 10 12 14 16 18 ID, DRAIN CURRENT (mA) 20 22 0 24 Figure 10. Noise Figure and Power Gain versus Drain Current Motorola Small–Signal Transistors, FETs and Diodes Device Data 22 5.0 4.0 3.0 2.0 18 Gpg VDS = 10 V ID = 10 mA TA = 25°C CIRCUIT IN FIGURE 1 14 10 NF G pg , POWER GAIN (dB) 150° 6.0 1.0 2.0 0 50 100 200 300 f, FREQUENCY (MHz) 500 700 1000 Figure 11. Noise Figure and Power Gain versus Frequency 3 MMBFU310LT1 C1 C6 U310 S D G C3 L1 INPUT RS = 50 Ω C4 L3 OUTPUT RL = 50 Ω C5 C2 L2 C1 = 1–10 pF Johanson Air variable trimmer. C2, C5 = 100 pF feed thru button capacitor. C3, C4, C6 = 0.5–6 pF Johanson Air variable trimmer. L4 VS L1 = 1/8″ x 1/32″ x 1–5/8″ copper bar. L2, L4 = Ferroxcube Vk200 choke. L3 = 1/8″ x 1/32″ x 1–7/8″ copper bar. VD SHIELD BW (3 dB) – 36.5 MHz ID – 10 mAdc VDS – 20 Vdc Device case grounded IM test tones – f1 = 449.5 MHz, f2 = 450.5 MHz Figure 12. 450 MHz IMD Evaluation Amplifier Amplifier power gain and IMD products are a function of the load impedance. For the amplifier design shown above with C4 and C6 adjusted to reflect a load to the drain resulting in a nominal power gain of 9 dB, the 3rd order intercept point (IP) value is 29 dBm. Adjusting C4, C6 to provide larger load values will result in higher gain, smaller bandwidth and lower IP values. For example, a nominal gain of 13 dB can be achieved with an intercept point of 19 dBm. OUTPUT POWER PER TONE (dBm) +40 +20 0 –20 –40 U310 JFET VDS = 20 Vdc ID = 10 mAdc F1 = 449.5 MHz F2 = 450.5 MHz 3RD ORDER INTERCEPT POINT FUNDAMENTAL OUTPUT Example of intercept point plot use: Assume two in–band signals of –20 dBm at the amplifier input. They will result in a 3rd order IMD signal at the output of –90 dBm. Also, each signal level at the output will be –11 dBm, showing an amplifier gain of 9.0 dB and an intermodulation ratio (IMR) capability of 79 dB. The gain and IMR values apply only for signal levels below comparison. –60 –80 3RD ORDER IMD OUTPUT –100 –120 –120 –100 –40 –20 –60 –80 INPUT POWER PER TONE (dBm) 0 +20 Figure 13. Two Tone 3rd Order Intercept Point 4 Motorola Small–Signal Transistors, FETs and Diodes Device Data MMBFU310LT1 INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.037 0.95 0.037 0.95 0.079 2.0 0.035 0.9 0.031 0.8 inches mm SOT–23 SOT–23 POWER DISSIPATION The power dissipation of the SOT–23 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA . Using the values provided on the data sheet for the SOT–23 package, PD can be calculated as follows: PD = TJ(max) – TA RθJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 225 milliwatts. PD = 150°C – 25°C 556°C/W = 225 milliwatts The 556°C/W for the SOT–23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT–23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. Motorola Small–Signal Transistors, FETs and Diodes Device Data 5 MMBFU310LT1 PACKAGE DIMENSIONS NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. A L 3 B S 1 V STYLE 10: PIN 1. DRAIN 2. SOURCE 3. GATE 2 DIM A B C D G H J K L S V G C D H K J INCHES MIN MAX 0.1102 0.1197 0.0472 0.0551 0.0350 0.0440 0.0150 0.0200 0.0701 0.0807 0.0005 0.0040 0.0034 0.0070 0.0180 0.0236 0.0350 0.0401 0.0830 0.0984 0.0177 0.0236 MILLIMETERS MIN MAX 2.80 3.04 1.20 1.40 0.89 1.11 0.37 0.50 1.78 2.04 0.013 0.100 0.085 0.177 0.45 0.60 0.89 1.02 2.10 2.50 0.45 0.60 CASE 318–08 ISSUE AE SOT–23 (TO–236AB) Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. 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Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 6 ◊ *MMBFU310LT1/D* MMBFU310LT1/D Motorola Small–Signal Transistors, FETs and Diodes Device Data