SAMSUNG S3C7414

S3C7414/P7414/C7424/P7424/C7434/P7434
1
PRODUCT OVERVIEW
PRODUCT OVERVIEW
OVERVIEW
The S3C7414/C7424/C7434 single-chip CMOS microcontroller has been designed for very high performance
using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontroller).
With an A/D converter, LED direct drive pins, an 8-bit serial I/O interface, and an 8-bit timer/counter, the
S3C7414/C7424/C7434 offers you an excellent design solution for a wide variety of home appliance applications
— electric fans, cookers, boilers, and air conditioners, for example.
Up to 35 pins of the 42-pin SDIP or 44-pin QFP package can be dedicated to I/O. Seven vectored interrupts
provide fast response to internal and external events.
In addition, the S3C7414/C7424/C7434's advanced CMOS technology provides for low power consumption and a
wide operating voltage range.
OTP
The S3C7414/C7424/C7434 microcontroller is also available in OTP (One Time Programmable) version,
S3P7414/P7424/P7434. S3P7414/P7424/P7434 microcontroller has an on-chip 4-Kbyte one-time-programmable
EPROM instead of masked ROM. The S3P7414/P7424/P7434 is comparable to S3C7414/C7424/C7434, in
function, in D.C. electrical characteristics and in pin configuration.
DEVELOPMENT SUPPORT
The Samsung Microcontroller Development System, SMDS, provides you with a complete PC-based development environment for S3C7-series microcontrollers that is powerful, reliable, and portable. In addition to its
window-based program development structure, the SMDS toolset includes versatile debugging, trace, instruction
timing, and performance measurement applications.
The Samsung Generalized Assembler (SAMA) has been designed specifically for the SMDS environment and
accepts assembly language sources in a variety of microprocessor formats. SAMA generates industry-standard
hex files that also contain program control data for SMDS compatibility.
1-1
PRODUCT OVERVIEW
S3C7414/P7414/C7424/P7424/C7434/P7434
FEATURES SUMMARY
Memory
•
256 × 4-bit RAM
•
4,096 × 8-bit ROM
35 I/O Pins
•
•
I/O: 31 pins including 8 LED direct drive pins
(S3C7414/C7434)
18 pins including 8 LED direct drive pins
(S3C7424)
Built-in reset circuit (S3C7434 only)
•
Built-in power-on reset circuit
Interrupts
•
Five internal vectored interrupts
(INTB, INTT0, INTT1, INTS, INTAD)
•
Three external vectored interrupts
(INT0, INT1, INT4)
•
Two quasi-interrupts (INT2, INTW)
Input only: 4 pins
Bit Sequential Carrier
A/D Converter
•
6-channel with 8-bit resolution
•
22.89 µs conversion speed at 4.19 MHz
Basic Timer
•
One 8-bit basic timer
•
Watchdog timer functions
•
Four interval clock selection
Timer/Counters
•
Two 8-bit timer/counter (TC0, TC1)
•
Programmable 8-bit timer
•
External event counter
•
Arbitrary clock frequency output
•
PWM output mode (TC1)
•
Supports 16-bit serial data transfer in
arbitrary format
Memory-Mapped I/O Structure
•
Data memory bank 15
Two Power-Down Modes
•
Idle mode (only CPU clock stops)
•
Stop mode (system oscillation stops)
Oscillation Sources
•
Crystal, Ceramic, or RC for system clock
•
Crystal, Ceramic: 0.4–6.0 MHz
•
RC: 4 MHz (typ)
•
CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
Watch Timer
•
0.95, 1.91, 15.3 µs at 4.19 MHz
•
0.67, 1.33, 10.7 µs at 6.0 MHz
•
One watch timer 8-bit
•
Time interval generation: 0.5 s, 3.9 ms at
4.19 MHz
Operating Temperature
Four frequency outputs to BUZ pin
•
•
– 40 °C to 85 °C
8-bit Serial I/O Interface
Operating Voltage Range
•
8-bit transmit/receive mode
•
1.8 V to 5.5 V (S3C7414/C7424)
•
8-bit receive mode
•
2.5 V to 5.5 V (S3C7434)
•
LSB-first or MSB-first transmission selectable
•
Internal or external clock source
Package Type
•
1-2
42-pin SDIP, 44-pin QFP (S3C7414/C7434)
30-pin SDIP, 28-pin SOP (S3C7424)
S3C7414/P7414/C7424/P7424/C7434/P7434
PRODUCT OVERVIEW
Table 1-1. Comparision Table
Feature
S3C7414
S3C7424
S3C7434
Core
SAM47
SAM47
SAM47
ROM
4 K bytes
Same
Same
RAM
256 nibbles
Same
Same
I/O
35 (4 input only)
21 (3 input only)
35 (4 input only)
POR (1)
None
None
Built in/ Typ: 2.0 V
SIO
8-bit SIO x 1
Same
Same
Timer0
8-bit timer/counter
Same
Same
Timer1(PWM)
8-bit timer/counter
(8-bit PWM x 1)
Same
Same
Watchdog timer
Watch-dog
4 selectable interval
Same
Same
ADC
8-bit x 6
8-bit x 4
8-bit x 6
Same
Same
(2)
AVSS
None
Interrupt
External x 3
Internal x 5
Quasi x 2 (KS0–KS3)
External x 2
Internal x 5
Quasi x 1 ( – )
External x 3
Internal x 5
Quasi x 2 (KS0–KS3)
Power down
Stop/Idle
Same
Same
Oscillator
Crystal, Ceramic, RC
Same
Same
Operating frequency
0.4–6 MHz
Same
Same
Operating voltage
1.8–5.5 V
1.8–5.5 V
2.5–5.5 V
OTP/MTP
OTP
Same
Same
Package
42SDIP/44QFP
30SDIP/28SOP
42SDIP/44QFP
NOTES
1. POR (power on reset)/Typ 2.0 V low voltage detector.
2. Internal A/D converter ground (bonded to VSS internally)
1-3
PRODUCT OVERVIEW
S3C7414/P7414/C7424/P7424/C7434/P7434
BLOCK DIAGRAM
BASIC
TIMER
INT0, INT1, INT2,INT4
8-BIT
TIMER/
COUNTER 0
8-BIT
TIMER/
COUNTER 1
RESET
INTERRUPT
CONTROL
BLOCK
XIN
WATCH
TIMER
XOUT
CLOCK
INTERNAL
INTERRUPTS
INSTRUCTION
REGISTER
PROGRAM
COUNTER
I/O PORT 2
0
SERIAL
I/O
INPUT
PORT 1
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
I/O PORT 2
P2.0-P2.3/
AD0-AD3
P4.0-4.3
I/O PORT 4
P5.0-5.3
I/O PORT 5
P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3
I/O PORT 6
P7.0-7.3
I/O PORT 7
A/D
CONVERTER
P8.0/TCL0
P8.1/TCLO0
P8.2
I/O PORT 8
I/O PORT 3
INSTRUCTION DECODER
ARITHMETIC
AND
LOGIC UNIT
256 x 4-BIT
DATA
MEMORY
PROGRAM
STATUS WORD
STACK
POINTER
4 K BYTE
PROGRAM
MEMORY
Figure 1-1. S3C7414/C7424/C7434Simplified Block Diagram
1-4
P0.0/ SCK
P0.1/SO
P0.2/SI
P0.3/BUZ
AVREF
P3.0/AD4
P3.1/AD5
P3.2/CLO/TCL1
P3.3/PWM / TCLO1
S3C7414/P7414/C7424/P7424/C7434/P7434
PRODUCT OVERVIEW
PIN ASSIGNMENTS
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P3.0/AD4
P3.1/AD5
AVREF
P3.2/CLO/TCL1
P3.3/PWM/TCLO1
P4.0
VDD
VSS
XOUT
XIN
TEST
P4.1
P4.2
RESET
P4.3
P5.0
P5.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
S3C7414
(42-SDIP)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P8.2
P8.1/TCLO0
P8.0/TCL0
P7.3
P7.2
P7.1
P7.0
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI
P0.1/SO
P0.0/SCK
P5.3
P5.2
Figure 1-2. S3C7414 Pin Assignment (42-SDIP)
1-5
S3C7414/P7414/C7424/P7424/C7434/P7434
44
43
42
41
40
39
38
37
36
35
34
NC
P3.1/AD5
P3.0/AD4
P2.3/AD3
P2.2/AD2
P2.1/AD1
P2.0/AD0
P8.2
P8.1/TCLO0
P8.0/TCL0
P7.3
PRODUCT OVERVIEW
1
2
3
4
5
6
7
8
9
10
11
S3C7414
(44-QFP)
33
32
31
30
29
28
27
26
25
24
23
RESET
P4.3
P5.0
P5.1
P5.2
P5.3
P0.0/SCK
P0.1/SO
P0.2/SI
P0.3/BUZ
NC
12
13
14
15
16
17
18
19
20
21
22
AVREF
P3.2/CLO/TCL1
P3.3/PWM/TCLO1
P4.0
VDD
VSS
XOUT
XIN
TEST
P4.1
P4.2
Figure 1-3. S3C7414 Pin Assignment (44-QFP)
1-6
P7.2
P7.1
P7.0
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
S3C7414/P7414/C7424/P7424/C7434/P7434
VSS
XOUT
XIN
TEST
P4.1
P4.2
RESET
NC
P4.3
P5.0
P5.1
P5.2
P5.3
P0.0/SCK
P0.1/SO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PRODUCT OVERVIEW
S3C7424
(30-SDIP)
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VDD
P4.0
P3.3/PWM/TCLO1
P3.2/CLO/TCL1
AVREF
NC
P2.3/AD3
P2.2/AD2
P2.1/AD1
P2.0/AD0
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI
Figure 1-4. S3C7424 Pin Assignment (30-SDIP)
VSS
XOUT
XIN
TEST
P4.1
P4.2
RESET
P4.3
P5.0
P5.1
P5.2
P5.3
P0.0/SCK
P0.1/SO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
S3C7424
(28-SOP)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
P4.0
P3.3/PWM/TCLO1
P3.2/CLO/TCL1
AVREF
P2.3/AD3
P2.2/AD2
P2.1/AD1
P2.0/AD0
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI
Figure 1-5. S3C7424 Pin Assignment (28-SOP)
1-7
PRODUCT OVERVIEW
S3C7414/P7414/C7424/P7424/C7434/P7434
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P3.0/AD4
P3.1/AD5
AVREF
P3.2/CLO/TCL1
P3.3/PWM/TCLO1
P4.0
VDD
VSS
XOUT
XIN
TEST
P4.1
P4.2
RESET
P4.3
P5.0
P5.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
S3C7434
(42-SDIP)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P8.2
P8.1/TCLO0
P8.0/TCL0
P7.3
P7.2
P7.1
P7.0
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI
P0.1/SO
P0.0/SCK
P5.3
P5.2
Figure 1-6. S3C7434 Pin Assignment (42-SDIP)
1-8
PRODUCT OVERVIEW
44
43
42
41
40
39
38
37
36
35
34
NC
P3.1/AD5
P3.0/AD4
P2.3/AD3
P2.2/AD2
P2.1/AD1
P2.0/AD0
P8.2
P8.1/TCLO0
P8.0/TCL0
P7.3
S3C7414/P7414/C7424/P7424/C7434/P7434
1
2
3
4
5
6
7
8
9
10
11
S3C7434
(44-QFP)
33
32
31
30
29
28
27
26
25
24
23
P7.2
P7.1
P7.0
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
RESET
P4.3
P5.0
P5.1
P5.2
P5.3
P0.0/SCK
P0.1/SO
P0.2/SI
P0.3/BUZ
NC
12
13
14
15
16
17
18
19
20
21
22
AVREF
P3.2/CLO/TCL1
P3.3/PWM/TCLO1
P4.0
VDD
VSS
XOUT
XIN
TEST
P4.1
P4.2
Figure 1-7. S3C7434 Pin Assignment (44-QFP)
1-9
PRODUCT OVERVIEW
S3C7414/P7414/C7424/P7424/C7434/P7434
PIN DESCRIPTIONS
Table 1-2. S3C7414/C7434 Pin Descriptions
Pin Name
Pin Type
Description
Number
Share Pin
4-bit I/O port.
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
24 (18)
25 (19)
26 (20)
27 (21)
SCK
SO
SI
BUZ
4-bit input port.
1-bit and 4-bit read and test is possible.
3-bit pull-up resistors are individually assignable by
software to pins P1.0, P1.1, and P1.2.
28 (23)
29 (24)
30 (25)
31 (26)
INT0
INT1
INT2
INT4
P0.0
P0.1
P0.2
P0.3
I/O
P1.0
P1.1
P1.2
P1.3
I
P2.0
P2.1
P2.2
P2.3
I/O
4-bit I/O port.
N-channel open-drain output.
1-bit or 4-bit write and test is possible.
Individual pins are software configurable as AD input
or output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
1 (38)
2 (39)
3 (40)
4 (41)
AD0
AD1
AD2
AD3
P3.0
P3.1
P3.2
P3.3
I/O
Same as Port 0 (P0.0–P0.3)
5 (42)
6 (43)
8 (2)
9 (3)
AD4
AD5
CLO/TCL1
PWM/TCLO1
P4.0
P4.1
P4.2
P4.3
P5.0–P5.3
I/O
4-bit I/O ports.
Ports 4 and 5 can be configured individually as nchannel open-drain or as CMOS push-pull output by
software.
1-bit and 4-bit read/write and test is possible.
Ports 4 and 5 can be paired to enable 8-bit data
transfer.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
10 (4)
16 (10)
17 (11)
19 (13)
20–23
(14–17)
–
P6.0–P6.3
I/O
Same as Port 0 except port 8 is a 3-bit I/O port
32–35
(27–30)
36–39
(31–34)
40 (35)
41 (36)
42 (37)
KS0–KS3
P7.0–P7.3
P8.0
P8.1
P8.2
1-10
–
TCL0
TCLO0
–
S3C7414/P7414/C7424/P7424/C7434/P7434
PRODUCT OVERVIEW
Table 1-2. S3C7414/C7434 Pin Descriptions (Continued)
Pin Name
Pin Type
Description
Number
Share Pin
SCK
I/O
Serial I/O interface clock signal
24 (18)
P0.0
SO
I/O
Serial data output
25 (19)
P0.1
SI
I/O
Serial data input
26 (20)
P0.2
BUZ
I/O
2 kHz, 4kHz, 8kHz, or 16 kHz frequency output at the
watch timer clock frequency of 32.768 kHz
27 (21)
P0.3
INT0, INT1
I
External interrupts. The triggering edge for INT0 and
INT1 is selectable. Only INT0 is synchronized with the
system clock.
28–29
(23–24)
P1.0, P1.1
INT2
I
Quasi-interrupt input with rising edge detection
30 (25)
P1.2
INT4
I
External interrupts with detection of rising and falling
edges
31 (26)
P1.3
A/D converter analog inputs
1–4
(38–41)
5–6
(42–43)
P2.0–P2.3
AD0–AD3
I/O
AD4–AD5
P3.0–P3.1
TCL0
I/O
External clock input for timer/counter0
40 (35)
P8.0
TCLO0
I/O
Timer/counter clock output
41 (36)
P8.1
CLO
I/O
Clock output
8 (2)
P3.2
TCL1
I/O
External clock input for timer/counter1
8 (2)
P3.2
PWM
I/O
PWM output
9 (3)
P3.3
TCLO1
I/O
Timer/counter clock output1
9 (3)
P3.3
KS0–KS3
I/O
Quasi-interrupt input with falling edge detection
32–35
(27–30)
P6.0–P6.3
VDD
–
Main power supply
11 (5)
–
VSS
–
Ground
12 (6)
–
RESET
I
Reset signal
18 (12)
–
XIN, Xout
–
Crystal, ceramic, or RC oscillator signal for system
clock.
14, 13
(8, 7)
–
AVREF
–
A/D converter analog reference voltage
7 (1)
–
TEST
I
Test signal input (must be connected to VSS)
15 (9)
–
NC
–
No connection (no bonding pin)
(22, 44)
–
NOTE: Parentheses indicate 44-QFP pin number.
1-11
PRODUCT OVERVIEW
S3C7414/P7414/C7424/P7424/C7434/P7434
Table 1-3. S3C7424 Pin Descriptions
Pin Name
Pin Type
Description
Number
Share Pin
4-bit I/O port.
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
14 (13)
15 (14)
16 (15)
17 (16)
SCK
SO
SI
BUZ
4-bit input port.
1-bit and 4-bit read and test is possible.
3-bit pull-up resistors are individually assignable by
software to pins P1.0, P1.1, and P1.2.
18 (17)
19 (18)
20 (19)
INT0
INT1
INT2
P0.0
P0.1
P0.2
P0.3
I/O
P1.0
P1.1
P1.2
I
P2.0
P2.1
P2.2
P2.3
I/O
4-bit I/O port.
N-channel open-drain output.
1-bit or 4-bit write and test is possible.
Individual pins are software configurable as AD input
or output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
21 (20)
22 (21)
23 (22)
24 (23)
AD0
AD1
AD2
AD3
P3.2
P3.3
I/O
Same as Port 0 (P0.0–P0.3)
27 (25)
28 (26)
CLO/TCL1
PWM/TCLO1
P4.0
P4.1
P4.2
P4.3
I/O
4-bit I/O ports.
Ports 4 and 5 can be configured individually as nchannel open-drain or as CMOS push-pull output by
software.
1-bit and 4-bit read/write and test is possible.
Ports 4 and 5 can be paired to enable 8-bit data
transfer.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
29 (27)
5 (5)
6 (6)
9 (8)
–
P5.0–P5.3
1-12
10–13
(9–12)
S3C7414/P7414/C7424/P7424/C7434/P7434
PRODUCT OVERVIEW
Table 1-3. S3C7424 Pin Descriptions (Continued)
Pin Name
Pin Type
Description
Number
Share Pin
SCK
I/O
Serial I/O interface clock signal
14 (13)
P0.0
SO
I/O
Serial data output
15 (14)
P0.1
SI
I/O
Serial data input
16 (15)
P0.2
BUZ
I/O
2 kHz, 4kHz, 8kHz, or 16 kHz frequency output at the
watch timer clock frequency of 32.768 kHz
17 (16)
P0.3
INT0, INT1
I
External interrupts. The triggering edge for INT0 and
INT1 is selectable. Only INT0 is synchronized with the
system clock.
18, 19
(17, 18)
P1.0, P1.1
INT2
I
Quasi-interrupt input with rising edge detection
20 (19)
P1.2
AD0–AD3
I/O
A/D converter analog inputs
21–24
(20–23)
P2.0–P2.3
CLO
I/O
Clock output
27 (25)
P3.2
TCL1
I/O
External clock input for timer/counter1
27 (25)
P3.2
PWM
I/O
PWM output
28 (26)
P3.3
TCLO1
I/O
Timer/counter clock output1
28 (26)
P3.3
30 (28)
–
VDD
–
Main power supply
VSS
–
Ground
1 (1)
–
RESET
I
Reset signal
7 (7)
–
XIN, XOUT
–
Crystal, ceramic, or RC oscillator signal for system
clock.
3, 2
(3, 2)
–
AVREF
–
Internal A/D converter analog reference voltage
26 (24)
–
TEST
I
Test signal input (must be connected to VSS)
4 (4)
–
NC
–
No connection (no bonding pin)
8, 25
–
NOTE: Parentheses indicate 28-SOP pin number.
1-13
PRODUCT OVERVIEW
S3C7414/P7414/C7424/P7424/C7434/P7434
Table 1-4. Overview of S3C7414/C7424/C7434Pin Data
Pin Names
Share Pins
I/O Type
Reset Value
Circuit Type
SCK, SO, SI, BUZ
I/O
Input
Type D
P1.0
P1.1
P1.2
INT0 (note)
INT1 (note)
INT2 (note)
I
Input
Type A-1
P1.3
INT4
I
Input
Type A
AD0–AD3
I/O
AD input
Type F-3
AD4
AD5
CLO/TCL1
TCLO1/PWM
I/O
Input
Type F
Type F
Type D
Type D
–
I/O
Input
Type E
KS0 (note)
KS1 (note)
KS2 (note)
KS3 (note)
I/O
Input
Type D
–
I/O
Input
Type D
TCL0 (note)
TCLO0
–
I/O
Input
Type D
VDD, VSS
–
–
–
–
XIN, XOUT
–
–
–
–
RESET
–
I
–
Type B-2 (note)
AVREF
–
–
–
–
TEST
–
I
–
–
NC
–
–
–
–
P0.0–P0.3
P2.0–P2.3
P3.0
P3.1
P3.2
P3.3
P4.0–P4.3
P5.0–P5.3
P6.0
P6.1
P6.2
P6.3
P7.0–P7.3
P8.0
P8.1
P8.2
NOTE: A noise filter circuit is built-in.
1-14
S3C7414/P7414/C7424/P7424/C7434/P7434
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
VDD
P-CHANNEL
1MΩ
IN
RESET
7pF
N -CHANNEL
Figure 1-10. Pin Circuit Type B-2
Figure 1-8. Pin Circuit Type A
VDD
VDD
PULL-UP
RESISTOR
ENABLE
P-CHANNEL
DATA
OUT
N -CHANNEL
OUTPUT
DISABLE
IN
CIRCUIT TYPE A
Figure 1-9. Pin Circuit Type A-1
Figure 1-11. Pin Circuit Type C
1-15
PRODUCT OVERVIEW
KS57C4104/P4104/C4204/P4204 MICROCONTROLLER (Preliminary Spec)
VDD
VDD
PULL-UP
RESISTOR
ENABLE
PULL-UP
RESISTOR
ENABLE
DATA
DATA
OUTPUT
DISABLE
OUTPUT
DISABLE
CIRCUIT
TYPE C
I/O
CIRCUIT
TYPE C
IN/OUT
DATA
CIRCUIT TYPE A
TO ADC
ADC INPUT SELECT
Figure 1-12. Pin Circuit Type D
Figure 1-14. Pin Circuit Type F
VDD
VDD
VDD
PNE
PULL-UP
RESISTOR
ENABLE
IN/OUT
DATA
OUTPUT
DISABLE
PULL-UP
RESISTOR
ENABLE
DATA
IN/OUT
OUTPUT
DISABLE
DATA
TO ADC
INPUT
ADC INPUT SELECT
Figure 1-13. Pin Circuit Type E
1-16
Figure 1-15. Pin Circuit Type F-3
S3C7414/P7414/C7424/P7424/C7434/P7434
14
ELECTRICAL DATA
ELECTRICAL DATA
OVERVIEW
In this section, information on S3C7414/C7424/C7434 electrical characteristics is presented as tables and
graphics. The information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— System clock oscillator characteristics
— Operating voltage range
— A.C. electrical characteristics
— A/D converter electrical characteristics
— I/O capacitance
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
Miscellaneous Timing Waveforms
— A.C timing measurement points (except for XIN)
— Clock timing measurement at XIN
— TCL0/1 timing
— Input timing for RESET signal
— Input timing for external interrupts and quasi-interrupts
— S3C7434 power-on RESET timing
— Serial data transfer timing
14-1
ELECTRICAL DATA
S3C7414/P7414/C7424/P7424/C7434/P7434
Table 14-1. S3C7414/C7424 Absolute Maximum Ratings
(TA = 25 °C)
Parameter
Supply Voltage
Symbol
Conditions
Rating
Units
VDD
–
– 0.3 to + 6.5
V
– 0.3 to VDD + 0.3
V
– 0.3 to VDD + 0.3
V
– 15
mA
Input Voltage
VI
Output Voltage
VO
Output Current High
I OH
All I/O ports
–
One pin
All output pins
Output Current Low
I OL
One pin
– 35
peak value
(note)
+ 30
rms value
All pins
peak value
mA
+ 15
(note)
+ 100
rms value
+ 60
Operating Temperature
TA
–
– 40 to + 85
°C
Storage Temperature
Tstg
–
– 65 to + 150
°C
NOTE: The values for Output Current Low (IOL) are calculated as Peak Value ×
14-2
Duty .
S3C7414/P7414/C7424/P7424/C7434/P7434
ELECTRICAL DATA
Table 14-2. S3C7414/C7424 D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Input High
Voltage
Symbol
Conditions
Min
Typ
Max
Units
VIH1
All input pins except those specified
below for VIH2–VIH3
0.7 VDD
–
VDD
V
VIH2
Ports 0, 1, 3, 6 and RESET
XIN, XOUT
0.8 VDD
VDD
VDD – 0.1
VDD
VIH3
Input Low
Voltage
VIL1
All input pins except those specified
below for VIL2–VIL3
VIL2
Ports 0, 1, 3, 6 and RESET
XIN, XOUT
VIL3
Output High
Voltage
VOH
Output Low
Voltage
VOL
Input High
Leakage Current
Input Low
Leakage Current
ILIH1
ILIH2
VI = VDD
XIN and XOUT only
ILIL1
VI = 0 V
All input pins except XIN and XOUT,
ILIL2
Output High
Leakage Current
ILOH
Output Low
Leakage Current
ILOL
Pull-up Resistor
RL1
Pull-up Resistor
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
Ports 0, 2–8
VDD = 4.5 V to 5.5 V
IOL = 15 mA
Ports 4 and 5 only
IOL = 4 mA
All output ports except ports 4 and 5
VI = VDD
All input pins except those specified
below for ILIH2
RL2
–
–
0.3 VDD
V
0.2 VDD
0.1
VDD – 1.0
–
–
V
–
0.4
2
V
3
µA
0.2
–
–
20
–
–
RESET
VI = 0 V
XIN and XOUT only
–3
µA
– 20
VO = VDD
All output pins
VO = 0 V
All output pins
–
–
3
µA
–
–
–3
µA
VI = 0 V; VDD = 5 V except RESET
25
50
100
kΩ
VI = 0 V; VDD = 3 V except RESET
50
100
200
VI = 0 V; VDD = 5 V; RESET
100
250
400
VI = 0 V; VDD = 3 V; RESET
200
500
800
kΩ
14-3
ELECTRICAL DATA
S3C7414/P7414/C7424/P7424/C7434/P7434
Table 14-2. S3C7414/C7424 D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
IDD1
Supply
Current
Symbol
(1)
Conditions
Max
–
3.0
8.0
6.0MHz
Crystal oscillator; C1=C2=22pF
4.19MHz
2.3
5.5
6.0MHz
1.4
4.0
4.19MHz
1.1
3.0
1.1
2.5
Idle mode; VDD = 5.0 V ± 10%
6.0MHz
Crystal oscillator; C1=C2=22pF
4.19MHz
1.0
1.8
6.0MHz
0.5
1.5
4.19MHz
0.4
1.0
0.1
5.0
0.1
3.0
VDD = 3 V ± 10%
IDD3
Typ
Run mode; VDD = 5.0 V ± 10%
VDD = 3 V ± 10%
IDD2
Min
Stop mode; VDD = 5.0 V ± 10%
Stop mode; VDD = 3.0 V ± 10%
–
–
Units
mA
mA
µA
NOTES:
1. D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up registers,
2.
output port drive currents and ADC.
The supply current assumes a CPU clock of fx/4.
14-4
S3C7414/P7414/C7424/P7424/C7434/P7434
ELECTRICAL DATA
Table 14-3. S3C7414/C7424 System Clock Oscillator Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Ceramic
Oscillator
Clock
Configuration
Xin
Xout
C1
Parameter
Oscillation frequency (1)
Xin
Xout
C1
Xin
(2)
Oscillation frequency (1)
Typ
Max
Units
VDD = 2.7 V to 5.5 V
0.4
–
6.0
MHz
VDD = 2.0 V to 5.5 V
0.4
–
4.2
VDD = 1.8 V to 5.5 V
0.4
–
3.0
–
–
4
ms
VDD = 2.7 V to 5.5 V
0.4
–
6.0
MHz
VDD = 2.0 V to 5.5 V
0.4
–
4.2
VDD = 1.8 V to 5.5 V
0.4
–
3.0
–
–
10
ms
VDD = 2.7 V to 5.5 V
0.4
–
6.0
MHz
VDD = 2.0 V to 5.5 V
0.4
–
4.2
VDD = 1.8 V to 5.5 V
0.4
–
3.0
83.3
–
1250
ns
–
4
–
MHz
VDD = 3.0 V
C2
Stabilization time
External
Clock
Min
C2
Stabilization time
Crystal
Oscillator
Test Condition
Xout
(2)
XIN input frequency (1)
VDD = 3.0 V
XIN input high and low
level width (tXH, tXL)
RC
Oscillator
Xin
Xout
R
Oscillation frequency
limitation
–
VDD = 5 V
R = 8.2 KΩ
NOTES:
1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
14-5
ELECTRICAL DATA
S3C7414/P7414/C7424/P7424/C7434/P7434
Main Oscillator Frequency
(Divided by 4)
CPU CLOCK
1.5 MHz
6 MHz
1.05 MHz
4.2 MHz
0.75 MHz
3 MHz
15.6 kHz
1
2
1.8
3
4
5
2.7
6
5.5
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 14-1. S3C7414/C7424 Standard Operating Voltage Range
Table 14-4. S3C7414/C7424 A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Instruction Cycle
Symbol
tCY
Time
TCL0/1 Input
f TI
tTIH, tTIL
Low Width
SCK Cycle Time
Min
Typ
Max
Units
VDD = 2.7 V to 5.5 V
0.67
–
64
µs
VDD = 1.8 V to 5.5 V
1.33
VDD = 2.7 V to 5.5 V
0
–
1.5
MHz
0.75
MHz
–
–
µs
–
–
ns
VDD = 1.8 V to 5.5 V
Frequency
TCL0/1 Input High,
Conditions
tKCY
VDD = 2.7 V to 5.5 V
0.48
VDD = 1.8 V to 5.5 V
1.8
VDD = 2.7 V to 5.5 V
800
External SCK source
Internal SCK source
670
VDD = 1.8 V to 5.5 V
3200
External SCK source
Internal SCK source
14-6
3800
S3C7414/P7414/C7424/P7424/C7434/P7434
ELECTRICAL DATA
Table 14-4. S3C7414/C7424 A.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
SCK High, Low
Width
Symbol
tKH, tKL
Conditions
VDD = 2.7 V to 5.5 V
Min
Typ
Max
Units
335
–
–
ns
–
–
ns
–
–
ns
–
300
ns
External SCK source
Internal SCK source
VDD = 1.8 V to 5.5 V
tKCY/2 – 50
1600
External SCK source
Internal SCK source
SI Setup Time to
SCK High
tSIK
VDD = 2.7 V to 5.5 V
tKCY/2 – 150
100
External SCK source
Internal SCK source
150
VDD = 1.8 V to 5.5 V
150
External SCK source
SI Hold Time to
SCK High
tKSI
Internal SCK source
500
VDD = 2.7 V to 5.5 V
400
External SCK source
Internal SCK source
400
VDD = 1.8 V to 5.5 V
600
External SCK source
Internal SCK source
Output Delay for
SCK to SO
tKSO (1)
VDD = 2.7 V to 5.5 V
500
–
External SCK source
Internal SCK source
250
VDD = 1.8 V to 5.5 V
1000
External SCK source
Internal SCK source
Interrupt Input
High, Low Width
RESET Input
Low Width
tINTH,
tINTL
tRSL
1000
INT0
(2)
INT1, INT2, INT4, KS0–KS3
10
Input
10
–
–
µs
–
–
µs
NOTES:
1. R(1KΩ) and C (100pF) are the load resistance and load capacitance of the SO output line.
2. Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting.
14-7
ELECTRICAL DATA
S3C7414/P7414/C7424/P7424/C7434/P7434
Table 14-5. S3C7434 Absolute Maximum Ratings
(TA = 25 °C)
Parameter
Supply Voltage
Symbol
Conditions
Rating
Units
VDD
–
– 0.3 to + 6.5
V
– 0.3 to VDD + 0.3
V
– 0.3 to VDD + 0.3
V
– 15
mA
Input Voltage
VI
Output Voltage
VO
Output Current High
I OH
All I/O ports
–
One pin
All output pins
Output Current Low
I OL
One pin
– 35
peak value
(note)
+ 30
rms value
All pins
peak value
mA
+ 15
(note)
+ 100
rms value
+ 60
Operating Temperature
TA
–
– 40 to + 85
°C
Storage Temperature
Tstg
–
– 65 to + 150
°C
NOTE: The values for Output Current Low (IOL) are calculated as Peak Value ×
14-8
Duty .
S3C7414/P7414/C7424/P7424/C7434/P7434
ELECTRICAL DATA
Table 14-6. S3C7434 D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 2.5 V to 5.5 V)
Parameter
Input High
Voltage
Symbol
Conditions
Min
Typ
Max
Units
VIH1
All input pins except those specified
below for VIH2–VIH3
0.7 VDD
–
VDD
V
VIH2
Ports 0, 1, 3, 6 and RESET
XIN, XOUT
0.8 VDD
VDD
VDD – 0.1
VDD
VIH3
Input Low
Voltage
VIL1
All input pins except those specified
below for VIL2–VIL3
VIL2
Ports 0, 1, 3, 6 and RESET
XIN, XOUT
VIL3
Output High
Voltage
VOH
Output Low
Voltage
VOL
Input High
Leakage Current
Input Low
Leakage Current
ILIH1
VI = VDD
XIN and XOUT only
ILIL1
VI = 0 V
All input pins except XIN and XOUT,
Output High
Leakage Current
ILOH
Output Low
Leakage Current
ILOL
Pull-Up Resistor
RL1
Pull-Up Resistor
RL2
–
0.3 VDD
V
0.2 VDD
0.1
VDD = 4.5 V to 5.5 V
VDD – 1.0
IOH = – 1 mA
Ports 0, 2–8
VDD = 3.5 V
–
IOL = 15 mA
Ports 4 and 5 only
IOL = 4 mA
All output ports except ports 4 and 5
VI = VDD
–
All input pins except those specified
below for ILIH2
ILIH2
ILIL2
–
–
–
V
0.4
2
V
3
µA
0.2
–
20
–
–
RESET
VI = 0 V
XIN and XOUT only
–3
µA
– 20
VO = VDD
All output pins
VO = 0 V
All output pins
–
–
3
µA
–
–
–3
µA
VI = 0 V; VDD = 5 V except RESET
25
50
100
kΩ
VI = 0 V; VDD = 3 V except RESET
50
100
200
VI = 0 V; VDD = 5 V; RESET
100
250
400
VI = 0 V; VDD = 3 V; RESET
200
500
800
kΩ
14-9
ELECTRICAL DATA
S3C7414/P7414/C7424/P7424/C7434/P7434
Table 14-6. S3C7434 D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 2.5 V to 5.5 V)
Parameter
Symbol
Min
Typ
Max
–
3.1
8.0
4.19MHz
2.4
5.5
6.0MHz
1.5
4.0
4.19MHz
1.2
3.0
1.2
2.5
4.19MHz
1.1
1.8
6.0MHz
0.6
1.5
4.19MHz
0.5
1.0
120
200
100
150
Run mode; VDD = 5.0 V ± 10%
IDD1
Supply
Current
Conditions
(1)
Crystal oscillator; C1 = C2 = 22pF
6.0MHz
VDD = 3 V ± 10%
Idle mode; VDD = 5.0 V ± 10%
IDD2
Crystal oscillator; C1 = C2 = 22pF
6.0MHz
VDD = 3 V ± 10%
Stop mode; VDD = 5.0 V ± 10%
IDD3
–
–
Stop mode; VDD = 3.0 V ± 10%
Units
mA
mA
µA
NOTES:
1. D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up registers,
2.
output port drive currents and ADC.
The supply current assumes a CPU clock of fx/4.
Table 14-7. S3C7434 Power-On Reset Circuit Characteristics
(TA = – 40 °C to + 85 °C, VDD = 2.5 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Power-On Reset
Voltage High
VDDH
2.5
Power-On Reset
Voltage Low
VDDL
0
Power Supply
Voltage Rise Time
tr
10
Power Supply
Voltage Off Time
toff
0.5
Power-On Reset Circuit
Cunsumption Current (2)
IDDPR
2.0
Max
Units
5.5
V
2.2
V
(1)
us
s
VDD = 5 V ± 10%
120
200
uA
VDD = 3 V ± 10%
100
150
uA
NOTES:
1. 217/fx (= 31.3 ms at fx = 4.19 MHz)
2. Current consumed when power-on reset circuit is provided internally.
14-10
Typ
S3C7414/P7414/C7424/P7424/C7434/P7434
ELECTRICAL DATA
Table 14-8. S3C7434 System Clock Oscillator Characteristics
(TA = – 40 °C to + 85 °C, VDD = 2.5 V to 5.5 V)
Oscillator
Ceramic
Oscillator
Clock
Configuration
Xin
Xout
C1
Parameter
Test Condition
Oscillation frequency (1)
Xin
Xout
C1
Oscillation frequency
Xin
Max
Units
VDD = 2.7 V to 5.5 V
0.4
–
6.0
MHz
VDD = 2.5 V to 5.5 V
0.4
–
4.2
–
–
4
ms
VDD = 2.7 V to 5.5 V
0.4
–
6.0
MHz
VDD = 2.5 V to 5.5 V
0.4
–
4.2
–
–
10
ms
VDD = 2.7 V to 5.5 V
0.4
–
6.0
MHz
VDD = 2.5 V to 5.5 V
0.4
–
4.2
83.3
–
1250
ns
–
4
–
MHz
VDD = 3.0 V
(1)
C2
Stabilization time
External
Clock
Typ
C2
Stabilization time (2)
Crystal
Oscillator
Min
Xout
(2)
XIN input frequency (1)
VDD = 3.0 V
XIN input high and low
level width (tXH, tXL)
RC
Oscillator
Xin
Xout
R
Oscillation frequency
limitation
–
VDD = 5 V
R = 8.2 KΩ
NOTES:
1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
14-11
ELECTRICAL DATA
S3C7414/P7414/C7424/P7424/C7434/P7434
Main Oscillator Frequency
(Divided by 4)
CPU CLOCK
1.5 MHz
6 MHz
1.05 MHz
4.2 MHz
0.75 MHz
3 MHz
15.6 kHz
1
2
1.8
3
4
5
2.7
6
5.5
2.5
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 14-2. S3C7434 Standard Operating Voltage Range
14-12
S3C7414/P7414/C7424/P7424/C7434/P7434
ELECTRICAL DATA
Table 14-9. S3C7434 A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 2.5 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Instruction Cycle
Time
tCY
VDD = 2.7 V to 5.5 V
0.67
–
64
µs
TCL0/1 Input
Frequency
f TI0
VDD = 2.7 V to 5.5 V
0
–
1.5
MHz
TCL0/1 Input
High, Low Width
tTIH0, tTIL0
VDD = 2.7 V to 5.5 V
0.48
–
–
µs
SCK Cycle Time
tKCY
VDD = 2.7 V to 5.5 V
800
–
–
ns
–
–
ns
–
–
ns
–
–
ns
–
300
ns
External SCK source
SCK High, Low
Width
tKH, tKL
Internal SCK source
670
VDD = 2.7 V to 5.5 V
325
External SCK source
Internal SCK source
SI Setup Time to
SCK High
SI Hold Time to
SCK High
tSIK
VDD = 2.7 V to 5.5 V
100
External SCK source
tKSI
Internal SCK source
150
VDD = 2.7 V to 5.5 V
400
External SCK source
Internal SCK source
Output Delay for
SCK to SO
tKCY/2 – 50
tKSO
VDD = 2.7 V to 5.5 V
400
–
External SCK source
Internal SCK source
250
Interrupt Input
tINTH,
INT0
High, Low Width
tINTL
INT1, INT2, INT4, KS0–KS3
10
RESET Input
Low Width
tRSL
Input
10
(NOTE)
–
–
µs
–
–
µs
NOTE: Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting.
14-13
ELECTRICAL DATA
S3C7414/P7414/C7424/P7424/C7434/P7434
Table 14-10. A/D Converter Electrical Characteristics
(TA = – 10 °C to + 70 °C, VDD = 3.5 V to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Condition
Min
Typ
Max
Units
Resolution
–
–
8
8
8
bit
Absolute accuracy (1)
–
2.5 V < AVREF < VDD
–
–
± 1.5
LSB
Conversion time (2)
tCON
–
–
96/fx
–
µs
Analog input voltage
VIAN
–
AVSS
–
AVREF
V
Analog input impedance
RAN
–
–
1000
–
MΩ
(3)
NOTES:
1. Absolute accuracy does not include the quantization error (± 1/2 LSB).
2. Conversion time is the time required from the moment a conversion operation starts until it ends (EOC = 0).
3. 'fx' is the abbreviation for system clock.
Table 14-11. Input/Output Capacitance
(TA = 25 °C, VDD = 0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
Capacitance
CIN
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
pF
Output
Capacitance
COUT
–
–
15
pF
CIO
–
–
15
pF
I/O Capacitance
Table 14-12. RAM Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply voltage
VDDDR
–
1.8
–
5.5
V
Data retention supply current
IDDDR
–
–
0.1
10
µA
Release signal set time
tSREL
–
0
–
–
ms
Oscillation stabilization time (1)
tWAIT
When released by
RESET
–
217/fx
–
ms
When released by
interrupt
–
(2)
–
ms
NOTES:
1. During oscillation stabilization time, CPU operation must be stopped to avoid unstable operation upon oscillation start.
2. The basic timer causes a delay of 217/fx after a reset.
14-14
S3C7414/P7414/C7424/P7424/C7434/P7434
ELECTRICAL DATA
TIMING WAVEFORMS
~
INTERNAL RESET
OPERATION
IDLE MODE
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
~
VDD
V DDDR
RESET
EXECUTION OF
STOP INSTRUCTION
tWAIT
t SREL
Figure 14-3. Stop Mode Release Timing When Initiated By RESET
~
IDLE MODE
NORMAL
OPERATING
MODE
STOP MODE
~
DATA RETENTION
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
POWER-DOWN MODE TERMINATING
(INTERRUPT REQUEST)
tSREL
t WAIT
Figure 14-4. Stop Mode Release Timing When Initiated By Interrupt Request
14-15
ELECTRICAL DATA
S3C7414/P7414/C7424/P7424/C7434/P7434
0.8 V DD
0.2 V DD
MEASUREMENT
POINTS
0.8 VDD
0.2 VDD
Figure 14-5. A.C. Timing Measurement Points (Except for XIN)
1/f x
tXL
t XH
XIN
VDD – 0.5 V
0.4 V
Figure 14-6. Clock Timing Measurement at XIN
1 / f TI0
t TIL0
TCL0
t TIH0
0.8 V DD
0.2 V DD
Figure 14-7. TCL0/1 Timing
14-16
S3C7414/P7414/C7424/P7424/C7434/P7434
ELECTRICAL DATA
tRSL
RESET
0.2 V DD
Figure 14-8. Input Timing for RESET Signal
tINTL
INT0, 1, 2, 4
KS0 to KS3
t INTH
0.8 VDD
0.2 V DD
Figure 14-9. Input Timing for External Interrupts and Quasi-Interrupts
14-17
ELECTRICAL DATA
S3C7414/P7414/C7424/P7424/C7434/P7434
toff
tr
VDD
VDDH
VDDL
Figure 14-10. S3C7434 Power-On RESET Timing
t KCY
t KL
t KH
0.8 V DD
0.2 V DD
SCK
t SIK
SI
t KSI
INPUT DATA
0.8 VDD
0.2 V DD
t KSO
SO
OUTPUT DATA
Figure 14-11. Serial Data Transfer Timing
14-18
S3C7414/P7414/C7424/P7424/C7434/P7434
15
MECHANICAL DATA
MECHANICAL DATA
This section contains the following information about the device package:
— Package dimensions in millimeters
— Pad diagram
#22
0.25 +0.1
–
0.05
15.24
42-SDIP-600
39.10 ± 0.2
0.50 ± 0.1
1.00 ± 0.1
1.778
5.08MAX
39.50 MAX
3.30 ± 0.3
#21
3.50 ± 0.2
#1
(1.77)
0-15 °
0.51MIN
14.00 ± 0.2
#42
NOTE: Dimensions are in millimeters.
Figure 15-1. 42-SDIP-600 Package Dimensions
15-1
MECHANICAL DATA
S3C7414/P7414/C7424/P7424/C7434/P7434
13.20 ± 0.3
0-8°
+0.10
0.15 - 0.05
10.00 ± 0.2
13.20 ± 0.3
0.80 ±0.20
10.00 ± 0.2
44-QFP-1010
0.10 MAX
#44
0.05 MIN
2.05 ± 0.10
#1
0.35
+0.10
- 0.05
(1.00)
0.80
NOTE: Dimensions are in millimeters.
Figure 15-2. 44-QFP-1010 Package Dimensions
15-2
2.30 MAX
S3C7414/P7414/C7424/P7424/C7434/P7434
MECHANICAL DATA
#16
– 0.05
0.25 +0.1
30-SDIP-400
0.56 ± 0.1
(1.30)
1.12 ± 0.1
1.778
5.08MAX
27.48 ± 0.2
3.30 ± 0.3
27.88 MAX
3.81 ± 0.2
#15
0.51MIN
#1
0-15 °
10.16
8.94 ± 0.2
#30
NOTE: Dimensions are in millimeters.
Figure 15-3. 30-SDIP-400 Package Dimensions
15-3
MECHANICAL DATA
S3C7414/P7414/C7424/P7424/C7434/P7434
0-8°
#1
#14
2.15 ± 0.2
18.02 MAX
17.62 ± 0.2
(0.56)
0.41 ± 0.1
1.27
NOTE: Dimensions are in millimeters.
Figure 15-4. 28-SOP-375 Package Dimensions
15-4
0.60 ± 0.20
+0.10
0.15 - 0.05
2.55MAX
28-SOP-375
9.53
7.70 ± 0.2
#15
0.05MIN
10.45 ± 0.3
#28
0.10 MAX
S3C7414/P7414/C7424/P7424/C7434/P7434
16
S3P7414/P7424/P7434 OTP
S3P7414/P7424/P7434 OTP
OVERVIEW
The S3P7414/P7424/P7434 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of
the S3C7414/C7424/C7434 microcontroller. It has an on-chip OTP ROM instead of masked ROM. Samsung′s
own serial protocol used for OTP program pin information regarding OTP program can be referred OTP pin
description.
The S3P7414/P7424/P7434 is fully compatible with the S3C7414/C7424/C7434, in function, in D.C. electrical
characteristics and in pin configuration. Because of its simple programming requirements, the
S3P7414/P7424/P7434 is ideal for use as an evaluation chip for the S3C7414/C7424/C7434.
16-1
S3P7414/P7424/P7434 OTP
S3C7414/P7414/C7424/P7424/C7434/P7434
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P3.0/AD4
P3.1/AD5
AVREF
P3.2/CLO/TCL1
SDAT/P3.3/PWM/TCLO1
SCLK/P4.0
VDD/VDD
VSS/VSS
XOUT
XIN
VPP/TEST
P4.1
P4.2
RESET/RESET
RESET
P4.3
P5.0
P5.1
NOTE:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
S3P7414
(42-SDIP)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
The bolds indicate an OTP pin name.
Figure 16-1. S3P7414 Pin Assignments (42-SDIP)
16-2
P8.2
P8.1/TCLO0
P8.0/TCL0
P7.3
P7.2
P7.1
P7.0
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI
P0.1/SO
P0.0/SCK
P5.3
P5.2
S3P7414/P7424/P7434 OTP
44
43
42
41
40
39
38
37
36
35
34
NC
P3.1/AD5
P3.0/AD4
P2.3/AD3
P2.2/AD2
P2.1/AD1
P2.0/AD0
P8.2
P8.1/TCLO0
P8.0/TCL0
P7.3
S3C7414/P7414/C7424/P7424/C7434/P7434
1
2
3
4
5
6
7
8
9
10
11
S3P7414
(44-QFP)
33
32
31
30
29
28
27
26
25
24
23
P7.2
P7.1
P7.0
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
RESET
P4.3
P5.0
P5.1
P5.2
P5.3
P0.0/SCK
P0.1/SO
P0.2/SI
P0.3/BUZ
NC
12
13
14
15
16
17
18
19
20
21
22
AVREF
P3.2/CLO/TCL1
SDAT/P3.3/PWM/TCLO1
SCLK/P4.0
VDD/VDD
VSS/VSS
XOUT
XIN
VPP/TEST
P4.1
P4.2
NOTE:
The bolds indicate an OTP pin name.
Figure 16-2. S3P7414 Pin Assignments (44-QFP)
16-3
S3P7414/P7424/P7434 OTP
S3C7414/P7414/C7424/P7424/C7434/P7434
VSS/VSS
XOUT
XIN
VPP/TEST
P4.1
P4.2
RESET/RESET
RESET
NC
P4.3
P5.0
P5.1
P5.2
P5.3
P0.0/SCK
P0.1/SO
NOTE:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
S3P7424
(30-SDIP)
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VDD/VDD
P4.0/SCLK
P3.3/PWM/TCLO1/SDAT
P3.2/CLO/TCL1
AVREF
NC
P2.3/AD3
P2.2/AD2
P2.1/AD1
P2.0/AD0
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI
The bolds indicate an OTP pin name.
Figure 16-3. S3P7424 Pin Assignments (30-SDIP)
VSS/VSS
XOUT
XIN
VPP/TEST
P4.1
P4.2
RESET/RESET
RESET
P4.3
P5.0
P5.1
P5.2
P5.3
P0.0/SCK
P0.1/SO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NOTE:
S3P7424
(28-SOP)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD/VDD
P4.0/SCLK
P3.3/PWM/TCLO1/SDAT
P3.2/CLO/TCL1
AVREF
P2.3/AD3
P2.2/AD2
P2.1/AD1
P2.0/AD0
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI
The bolds indicate an OTP pin name.
Figure 16-4. S3P7424 Pin Assignments (28-SOP)
16-4
S3C7414/P7414/C7424/P7424/C7434/P7434
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P3.0/AD4
P3.1/AD5
AVREF
P3.2/CLO/TCL1
SDAT/P3.3/PWM/TCLO1
SCLK/P4.0
VDD/VDD
VSS/VSS
XOUT
XIN
VPP/TEST
P4.1
P4.2
RESET/RESET
RESET
P4.3
P5.0
P5.1
NOTE:
S3P7414/P7424/P7434 OTP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
S3P7434
(42-SDIP)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P8.2
P8.1/TCLO0
P8.0/TCL0
P7.3
P7.2
P7.1
P7.0
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ
P0.2/SI
P0.1/SO
P0.0/SCK
P5.3
P5.2
The bolds indicate an OTP pin name.
Figure 16-5. S3P7434 Pin Assignments (42-SDIP)
16-5
S3C7414/P7414/C7424/P7424/C7434/P7434
44
43
42
41
40
39
38
37
36
35
34
NC
P3.1/AD5
P3.0/AD4
P2.3/AD3
P2.2/AD2
P2.1/AD1
P2.0/AD0
P8.2
P8.1/TCLO0
P8.0/TCL0
P7.3
S3P7414/P7424/P7434 OTP
1
2
3
4
5
6
7
8
9
10
11
S3P7434
(44-QFP)
33
32
31
30
29
28
27
26
25
24
23
P7.2
P7.1
P7.0
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
RESET
P4.3
P5.0
P5.1
P5.2
P5.3
P0.0/SCK
P0.1/SO
P0.2/SI
P0.3/BUZ
NC
12
13
14
15
16
17
18
19
20
21
22
AVREF
P3.2/CLO/TCL1
SDAT/P3.3/PWM/TCLO1
SCLK/P4.0
VDD/VDD
VSS/VSS
XOUT
XIN
VPP/TEST
P4.1
P4.2
NOTE:
The bolds indicate an OTP pin name.
Figure 16-6. S3P7434 Pin Assignments (44-QFP)
16-6
S3C7414/P7414/C7424/P7424/C7434/P7434
S3P7414/P7424/P7434 OTP
Table 16-1. Pin Descriptions of S3P7414/P7434 Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P3.3
SDAT
9 (3)
I/O
Serial data pin. Output port when reading and input
port when writing. Can be assigned as a Input /
push-pull output port.
P4.0
SCLK
10 (4)
I/O
Serial clock pin. Input only pin.
TEST
VPP (TEST)
15 (9)
I
Power supply pin for EPROM cell writing (indicates
that OTP enters into the writing mode). When 12.5
V is applied, OTP is in writing mode and when 5 V
is applied, OTP is in reading mode. (Option)
RESET
RESET
18 (12)
I
Chip initialization
VDD/VSS
VDD/VSS
11/12 (5/6)
I
Logic power supply pin. VDD should be tied to +5 V
during programming.
NOTE: Parentheses indicate 44-QFP pin number.
Table 16-2. Pin Descriptions of S3P7424 Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P3.3
SDAT
28 (26)
I/O
Serial data pin. Output port when reading and input
port when writing. Can be assigned as a Input /
push-pull output port.
P4.0
SCLK
29 (27)
I/O
Serial clock pin. Input only pin.
TEST
VPP (TEST)
4 (4)
I
Power supply pin for EPROM cell writing (indicates
that OTP enters into the writing mode). When 12.5
V is applied, OTP is in writing mode and when 5 V
is applied, OTP is in reading mode. (Option)
RESET
RESET
7 (7)
I
Chip initialization
VDD/VSS
VDD/VSS
30/1 (28/1)
I
Logic power supply pin. VDD should be tied to +5 V
during programming.
NOTE: Parentheses indicate 28-SOP pin number.
16-7
S3P7414/P7424/P7434 OTP
S3C7414/P7414/C7424/P7424/C7434/P7434
Table 16-3. Comparison of S3P7414/P7424 and S3C7414/C7424 Features
Characteristic
S3P7414/P7424
S3C7414/C7424
Program Memory
4 K byte EPROM
4 K byte mask ROM
Operating Voltage (VDD)
1.8 V to 5.5 V
1.8 V to 5.5 V
OTP Programming Mode
VDD = 5 V, VPP(TEST)=12.5V
Pin Configuration
42 SDIP, 44 QFP, 30 SDIP, 28 SOP
42 SDIP, 44 QFP, 30 SDIP, 28 SOP
EPROM Programmability
User Program 1 time
Programmed at the factory
Table 16-4. Comparison of S3P7434 and S3C7434 Features
Characteristic
S3P7434
S3C7434
Program Memory
4 K byte EPROM
4 K byte mask ROM
Operating Voltage (VDD)
2.5 V to 5.5 V
2.5 V to 5.5 V
OTP Programming Mode
VDD = 5 V, VPP(TEST)=12.5V
Pin Configuration
42 SDIP, 44 QFP
42 SDIP, 44 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP(TEST) pin of the S3P7414/P7424/P7434, the EPROM programming mode is
entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins
listed in Table 16-4 below.
Table 16-5. Operating Mode Selection Criteria
VDD
VPP
(TEST)
REG/
MEM
Address
(A15-A0)
R/W
5V
5V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
16-8
Mode
S3C7414/P7414/C7424/P7424/C7434/P7434
S3P7414/P7424/P7434 OTP
START
Address= First Location
VDD =5V, V PP=12.5V
x=0
Program One 1ms Pulse
Increment X
YES
x = 10
NO
FAIL
Verify Byte
Verify 1 Byte
Last Address
FAIL
NO
Increment Address
VDD = VPP= 5 V
FAIL
Compare All Byte
PASS
Device Failed
Device Passed
Figure 16-7. OTP Programming Algorithm
16-9
S3P7414/P7424/P7434 OTP
S3C7414/P7414/C7424/P7424/C7434/P7434
Table 16-6. S3P7414/P7424 D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Conditions
IDD1
Supply
Current
Symbol
(1)
Max
–
3.0
8.0
6.0MHz
Crystal oscillator; C1=C2=22pF
4.19MHz
2.3
5.5
6.0MHz
1.4
4.0
4.19MHz
1.1
3.0
1.1
2.5
Idle mode; VDD = 5.0 V ± 10%
6.0MHz
Crystal oscillator; C1=C2=22pF
4.19MHz
1.0
1.8
6.0MHz
0.5
1.5
4.19MHz
0.4
1.0
0.1
5.0
0.1
3.0
VDD = 3 V ± 10%
Stop mode; VDD = 5.0 V ± 10%
IDD3
Typ
Run mode; VDD = 5.0 V ± 10%
VDD = 3 V ± 10%
IDD2
Min
–
–
Stop mode; VDD = 3.0 V ± 10%
Units
mA
mA
µA
NOTES:
1. D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up registers,
2.
output port drive currents and ADC.
The supply current assumes a CPU clock of fx/4.
Main Oscillator Frequency
(Divided by 4)
CPU CLOCK
1.5 MHz
6 MHz
1.05 MHz
4.2 MHz
0.75 MHz
3 MHz
15.6 kHz
1
2
1.8
3
4
5
2.7
6
5.5
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 16-8. S3P7414/P7424 Standard Operating Voltage Range
16-10
S3C7414/P7414/C7424/P7424/C7434/P7434
S3P7414/P7424/P7434 OTP
Table 16-7. S3P7434 D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 2.5 V to 5.5 V)
Parameter
Conditions
IDD1
Supply
Current
Symbol
(1)
Typ
Max
–
3.1
8.0
Run mode; VDD = 5.0 V ± 10%
6.0MHz
Crystal oscillator; C1=C2=22pF
4.19MHz
2.4
5.5
6.0MHz
1.5
4.0
4.19MHz
1.2
3.0
1.2
2.5
VDD = 3 V ± 10%
IDD2
Min
Idle mode; VDD = 5.0 V ± 10%
6.0MHz
Crystal oscillator; C1=C2=22pF
4.19MHz
1.1
1.8
6.0MHz
0.6
1.5
4.19MHz
0.5
1.0
120
200
100
150
VDD = 3 V ± 10%
–
Stop mode; VDD = 5.0 V ± 10%
IDD3
–
Stop mode; VDD = 3.0 V ± 10%
Units
mA
mA
µA
NOTES:
1. D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up registers,
2.
output port drive currents and ADC.
The supply current assumes a CPU clock of fx/4.
Main Oscillator Frequency
(Divided by 4)
CPU CLOCK
1.5 MHz
6 MHz
1.05 MHz
4.2 MHz
15.6 kHz
1
2
3
4
5
2.5
6
5.5
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 16-9. S3P7434 Standard Operating Voltage Range
16-11
S3P7414/P7424/P7434 OTP
S3C7414/P7414/C7424/P7424/C7434/P7434
NOTES
16-12