SAMSUNG KS57P21832

KS57C21832/P21832
1
PRODUCT OVERVIEW
PRODUCT OVERVIEW
OVERVIEW
The KS57C21832 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With an up-to-896-dot LCD direct drive capability, 8-bit timer/counter 0, 16-bit timer/counter 1, and serial I/O, the
KS57C21832 offers an excellent design solution for a wide variety of applications which require LCD functions.
Up to 39 pins of the 100-pin QFP package can be dedicated to I/O. Eight vectored interrupts provide fast
response to internal and external events. In addition, the KS57C21832's advanced CMOS technology provides for
low power consumption and a wide operating voltage range.
OTP
The KS57C21832 microcontroller is also available in OTP (One Time Programmable) version, KS57P21832.
KS57P21832 microcontroller has an on-chip 32 K-byte one-time-programable EPROM instead of masked ROM.
The KS57P21832 is comparable to KS57C21832, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
KS57C21832/P21832
FEATURES SUMMARY
Memory
•
8,192 × 4-bit RAM (excluding LCD display RAM)
•
32,768 × 8-bit ROM
39 I/O Pins
•
I/O: 35 pins
•
Input only: 4 pins
Watch Timer
•
Time interval generation: 0.5 s, 3.9 ms
at 32768 Hz
•
4 frequency outputs to BUZ pin
•
Clock source generation for LCD
Interrupts
•
Four internal vectored interrupts
LCD Controller/Driver
•
Four external vectored interrupts
•
56 segments and 16 common terminals
•
Two quasi-interrupts
•
8 and 16 common selectable
•
Internal resistor circuit for LCD bias
•
All dot can be switched on/off
8-bit Basic Timer
•
4 interval timer functions
•
Watchdog timer
Bit Sequential Carrier
•
Supports 16-bit serial data transfer in arbitrary
format
Power-Down Modes
•
Idle mode (only CPU clock stops)
•
Stop mode (main system clock and CPU clock
stop)
•
Sub-system clock stop mode
8-bit Timer/Counter 0
•
Programmable 8-bit timer
•
External event counter
Oscillation Sources
•
Arbitrary clock frequency output
•
Crystal, ceramic, or RC for main system clock
•
External clock signal divider
•
Crystal oscillator for subsystem clock
•
Serial I/O interface clock generator
•
Main system clock frequency: 0.4 - 6 MHz
•
Subsystem clock frequency: 32.768 kHz
•
CPU clock divider circuit (by 4, 8, or 64)
16-Bit Timer/Counter 1
•
Programmable 16-bit timer
•
External event counter
Instruction Execution Times
•
Arbitrary clock frequency output
•
0.67, 1.33, 10.7 µs at 6 MHz
•
External clock signal divider
•
0.95, 1.91, 15.3 µs at 4.19 MHz
•
122 µs at 32.768 kHz
8-bit Serial I/O Interface
•
8-bit transmit/receive mode
Operating Temperature
•
8-bit receive mode
•
•
LSB-first or MSB-first transmission selectable
•
Internal or external clock source
- 40 °C to 85 °C
Operating Voltage Range
•
1.8 V to 5.5 V (3.0 MHz @ 1.8 V)
Memory-Mapped I/O Structure
•
Data memory bank 15
Package Type
•
1-2
100-pin QFP
KS57C21832/P21832
PRODUCT OVERVIEW
BLOCK DIAGRAM
XIN
RESET
P1.0-P1.3/
INT0-INT4
P2.0/CLO
P2.1/LCDCK
P2.2/LCDSY
Basic
Timer
Watch
Timer
XTIN XTOUT
VLC1-VLC5
Input Port 1
I/O Port 2
Interrupt
Control
Block
COM0-COM7
Clock
Instruction
Register
LCD
Driver/
Controller
P4.0-P5.3/
COM8-COM15
SEG0-SEG39
P3.0/TCLO0
P3.1/TCLO1
P3.2/TCL0
P3.3/TCL1
I/O Port 3
P4.0-P4.3/
COM8-COM11
I/O Port 4
P5.0-P5.3/
COM12-COM15
I/O Port 5
P6.0-P6.3
SEG55-SEG52
KS4-KS7
XOUT
P9.3-P6.0/
SEG40-SEG55
Internal
Interrupts
Serial I/O
Instruction
I/O Port 6
P7.0-P7.3
SEG51-SEG48
I/O Port 7
P8.0-P8.3
SEG47-SEG44
I/O Port 8
P9.0-P9.3
SEG43-SEG40
I/O Port 9
Arithmetic
and
Logic Unit
8192 x 4-Bit
Data
Memory
Program
Status Word
Stack
Pointer
32 K Byte
Program
Memory
I/O
Port 0
P0.0/SCK/KO
P0.1/SO/K1
P0.2/SI/K2
P0.3/BUZ/K3
8-Bit
Timer/
Counter 0
16-Bit
TImer/
Counter 1
Figure 1-1. KS57C21832 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
KS57C21832/P21832
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
PIN ASSIGNMENTS
SEG4
SEG3
SEG2
SEG1
SEG0
VLC5
VLC4
VLC3
VLC2
VLC1
P0.0/SCK/K0
P0.1/SO/K1
P0.2/SI/K2
P0.3/BUZ/K3
VDD
VSS
XOUT
XIN
TEST
XTIN
XTOUT
RESET
KS57C21832
(100-QFP-1420C)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P3.1/TCLO1
P3.2/TCL0
P3.3/TCL1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
P4.0/COM8
P4.1/COM9
P4.2/COM10
P4.3/COM11
P5.0/COM12
P5.1/COM13
P5.2/COM14
P5.3/COM15
P6.0/SEG55/K4
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P2.0/CLO
P2.1/LCDCK
P2.2/LCDSY
P3.0/TCLO0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Figure 1-2. KS57C21832 100-QFP Pin Assignment Diagram
1-4
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
P9.3/SEG40
P9.2/SEG41
P9.1/SEG42
P9.0/SEG43
P8.3/SEG44
P8.2/SEG45
P8.1/SEG46
P8.0/SEG47
P7.3/SEG48
P7.2/SEG49
P7.1/SEG50
P7.0/SEG51
P6.3/SEG52/K7
P6.2/SEG53/K6
P6.1/SEG54/K5
KS57C21832/P21832
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. KS57C21832 Pin Descriptions
Pin Type
Description
Number
Share Pin
P0.0
P0.1
P0.2
P0.3
Pin Name
I/O
4-bit I/O port.
1-bit and 4-bit read/write and test are possible.
Individual pins are software configurable as input or
output.
Individual pins are software configurable as opendrain or push-pull output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
11
12
13
14
SCK/K0
SO/K1
SI/K2
BUZ/K3
P1.0
P1.1
P1.2
P1.3
I
4-bit input port.
1-bit and 4-bit read and test are possible.
4-bit pull-up resistors are assignable by software.
23
24
25
26
INT0
INT1
INT2
INT4
P2.0
P2.1
P2.2
I/O
Same as port 0 except that port 2 is 3-bit I/O port.
27
28
29
CLO
LCDCK
LCDSY
P3.0
P3.1
P3.2
P3.3
I/O
Same as port 0.
30
31
32
33
TCLO0
TCLO1
TCL0
TCL1
P4.0-P4.3
I/O
4-bit I/O ports.
1-, 4-bit or 8-bit read/write and test are possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
42-45
COM8COM11
COM12COM15
Same as P4, P5.
50-53
SEG55/K4SEG52/K7
54-57
SEG51SEG48
58-61
SEG47SEG44
SEG43SEG40
P5.0-P5.3
P6.0-P6.3
I/O
P7.0-P7.3
P8.0-P8.3
I/O
Same as P4, P5.
P9.0-P9.3
46-49
62-65
SCK
I/O
Serial I/O interface clock signal.
11
P0.0/K0
SO
I/O
Serial data output.
12
P0.1/K1
SI
I/O
Serial data input.
13
P0.2/K2
BUZ
I/O
2 kHz, 4 kHz, 8 kHz or 16 kHz frequency output for
buzzer signal.
14
P0.3/K3
23, 24
P1.0, P1.1
INT0, INT1
I
External interrupts. The triggering edge for INT0 and
INT1 is selectable.
1-5
PRODUCT OVERVIEW
KS57C21832/P21832
Table 1-1. KS57C21832 Pin Descriptions (Continued)
Pin Name
Pin Type
Description
Number
Share Pin
INT2
I
Quasi-interrupt with detection of rising or falling
edges.
25
P1.2
INT4
I
External interrupt with detection of rising or
falling edges.
26
P1.3
CLO
I/O
Clock output .
27
P2.0
LCDCK
I/O
LCD clock output for display expansion.
28
P2.1
LCDSY
I/O
LCD synchronization clock output for display
expansion.
29
P2.2
TCLO0
I/O
Timer/counter 0 clock output.
30
P3.0
TCLO1
I/O
Timer/counter 1 clock output.
31
P3.1
TCL0
I/O
External clock input for timer/counter 0.
32
P3.2
TCL1
I/O
External clock input for timer/counter 1.
COM0-COM7
O
LCD common signal output.
COM8-COM11
I/O
COM12-COM15
SEG0-SEG39
O
SEG40-SEG43
I/O
LCD segment signal output.
33
P3.3
34-41
–
42-45
P4.0-P4.3
46-49
P5.0-P5.3
5-1,
100-66
–
65-62
P9.3-P9.0
SEG44-SEG47
61-58
P8.3-P8.0
SEG48-SEG51
57-54
P7.3-P7.0
SEG52-SEG55
53-50
P6.3/K7-P6.0/K4
11-14
P0.0-P0.3
50-53
P6.0-P6.3
K0-K3
I/O
External interrupt. The triggering edge is
selectable.
K4-K7
VDD
–
Main power supply.
15
–
VSS
–
Ground.
16
–
RESET
I
Reset signal.
VLC1-VLC5
–
LCD power supply.
Xin, Xout
–
XTin, XTout
TEST
22
–
10-6
–
Crystal, Ceramic or RC oscillator pins for
system clock.
18, 17
–
–
Crystal oscillator pins for subsystem clock.
20, 21
–
I
Test signal input. (must be connected to VSS)
19
–
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
1-6
KS57C21832/P21832
PRODUCT OVERVIEW
Table 1-2. Overview of KS57C21832 Pin Data
Pin Names
Share Pins
I/O Type
Reset Value
Circuit Type
P0.1, P0.3
SO/K1, BUZ/K3
I/O
Input
E-1
P0.0, P0.2
SCK/K0, SI/K2
I/O
Input
E-2
P1.0-P1.3
INT0-INT2, INT4
I
Input
A-3
P2.0-P2.2
CLO, LCDCK, LCDSY
I/O
Input
E
P3.0-P3.1
TCLO0, TCLO1
I/O
Input
E
P3.2-P3.3
TCL0, TCL1
I/O
Input
E-1
P4.0-P4.3
P5.0-P5.3
COM8-COM11
COM12-COM15
I/O
Input
H-13
P6.0-P6.3
SEG55/K4-SEG52/K7
I/O
Input
H-16
P7.0-P7.3
SEG51-SEG48
I/O
Input
H-13
P8.0-P8.3
P9.0-P9.3
SEG47-SEG44
SEG43-SEG40
I/O
Input
H-13
COM0-COM7
–
O
High
H-3
SEG0-SEG39
–
O
High
H-15
VDD
–
–
–
–
VSS
–
–
–
–
RESET
–
I
–
B
VLC1-VLC5
–
–
–
–
XIN, XOUT
–
–
–
–
XTIN, XTOUT
–
–
–
–
TEST
–
I
–
–
1-7
PRODUCT OVERVIEW
KS57C21832/P21832
PIN CIRCUIT DIAGRAMS
VDD
VDD
Pull-Up
Resistor
P-Channel
In
In
N-Channel
Schmitt Trigger
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type B
VDD
VDD
Pull-Up
Resistor
Pull-Up
Resistor
Enable
P-Channel
Data
Out
Output
DIsable
In
P-Channel
N-Channel
Schmitt Trigger
Figure 1-4. Pin Circuit Type A-3
1-8
Figure 1-6. Pin Circuit Type C
KS57C21832/P21832
PRODUCT OVERVIEW
VDD
PNE
Pull-up
Resistor
VDD
Pull-up
Resistor
Enable
P-CH
I/O
Data
N-CH
Output
DIsable
Figure 1-7. Pin Circuit Type E
VDD
PNE
Pull-up
Resistor
VDD
P-CH
Pull-up
Resistor
Enable
I/O
Data
N-CH
Output
DIsable
Schmitt Trigger
Figure 1-8. Pin Circuit Type E-1
1-9
PRODUCT OVERVIEW
KS57C21832/P21832
VDD
PNE
Pull-up
Resistor
VDD
P-CH
I/O
Data
N-CH
Output
DIsable
Schmitt Trigger
Figure 1-9. Pin Circuit Type E-2
1-10
Pull-up
Resistor
Enable
KS57C21832/P21832
PRODUCT OVERVIEW
VDD
VLC1
Out
COM
VLC4
VLC5
Figure 1-10. Pin Circuit Type H-3
VDD
VLC2
Out
SEG
VLC3
VLC5
Figure 1-11. Pin Circuit Type H-15
1-11
PRODUCT OVERVIEW
KS57C21832/P21832
VDD
Pull-up
Resistor
Pull-up
Resistor
Enable
COM/SEG
Output
Disable
Data
P-CH
Type H-3
Type C
I/O
Figure 1-12. Pin Circuit Type H-13
VDD
Pull-up
Resistor
Pull-up
Resistor
Enable
SEG
Output
Disable
Data
P-CH
Type H-15
Type C
Schmitt Trigger
Figure 1-13. Pin Circuit Type H-16
1-12
I/O
KS57C21832/P21832
14
ELECTRICAL DATA
ELECTRICAL DATA
OVERVIEW
In this section, information on KS57C21832 electrical characteristics is presented as tables and graphics.
The information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at XIN
— Clock timing measurement at XTIN
— TCL timing
— Input timing for RESET
— Input timing for external interrupts
— Serial data transfer timing
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
14-1
ELECTRICAL DATA
KS57C21832/P21832
Table 14-1. Absolute Maximum Ratings
(TA = 25 °C)
Parameter
Supply Voltage
Symbol
Conditions
Rating
Units
VDD
–
- 0.3 to + 6.5
V
- 0.3 to VDD + 0.3
V
- 0.3 to VDD + 0.3
V
mA
Input Voltage
VI
Output Voltage
VO
–
Output Current High
I OH
One I/O pin active
- 15
All I/O pins active
- 35
One I/O pin active
+ 30 (Peak value)
Output Current Low
Ports 0-9
I OL
mA
+ 15 (note)
Total for ports 0, 2-9
+ 100 (Peak value)
+ 60 (note)
Operating Temperature
TA
–
- 40 to + 85
°C
Storage Temperature
Tstg
–
- 65 to + 150
°C
NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value ×
Duty .
Table 14-2. D.C. Electrical Characteristics
(TA = - 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
–
VDD
V
VIH1
All input pins except those
specified below for VIH2-VIH3
0.7 VDD
VIH2
Ports 0, 1, 6, P3.2, P3.3, and
RESET
0.8 VDD
VDD
VIH3
XIN, XOUT, and XTIN
VDD - 0.1
VDD
VIL1
All input pins except those
specified below for VIL2-VIL3
VIL2
Ports 0, 1, 6, P3.2, P3.3, and
RESET
VIL3
XIN, XOUT, and XTIN
Output High
Voltage
VOH
VDD = 4.5 V to 5.5 V
IOH = - 1 mA
Ports 0, 2-9
VDD - 1.0
–
–
V
Output Low
Voltage
VOL
VDD = 4.5 V to 5.5 V
IOL = 15 mA
–
–
2.0
V
Input High
Voltage
Input Low
Voltage
Ports 0, 2-9
14-2
–
–
0.3 VDD
V
0.2 VDD
0.1
KS57C21832/P21832
ELECTRICAL DATA
Table 14-2. D.C. Electrical Characteristics (Continued)
(TA = - 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
–
–
3
µA
ILIH1
VI = VDD
All input pins except those
specified below for ILIH2
ILIH2
VI = VDD
XIN, XOUT, XTIN, and RESET
Input Low
Leakage
ILIL1
VI = 0 V
All input pins except those
specified below for ILIH2
Current
ILIL2
VI = 0 V
XIN, XOUT, and XTIN
Output High
Leakage
Current
ILOH
VO = VDD
All output pins
–
–
3
µA
Output Low
Leakage
Current
ILOL
VO = 0 V
All output pins
–
–
-3
µA
Pull-Up
Resistor
RLI
VI = 0 V; VDD = 5 V
Port 0-9
25
47
100
kΩ
VDD = 3 V
50
95
200
VI = 0 V; VDD = 5 V, RESET
100
220
400
VDD = 3 V
200
450
800
Input High
Leakage
Current
RL2
20
–
–
-3
µA
- 20
LCD Voltage
Dividing
Resistor
RLCD
TA = 25 °C
25
55
80
kΩ
|VDD-COMi|
Voltage Drop
(i = 0-15)
VDC
- 15 µA per common pin
–
–
120
mV
|VDD-SEGx|
Voltage Drop
(x = 0-55)
VDS
- 15 µA per segment pin
–
–
120
VLC1 Output
Voltage
VLC1
LCD clock = 0 Hz, VLC5 = 0 V
0.8 VDD - 0.2
0.8 VDD
0.8 VDD + 0.2
VLC2 Output
Voltage
VLC2
0.6 VDD - 0.2
0.6 VDD
0.6 VDD+ 0.2
VLC3 Output
Voltage
VLC3
0.4 VDD - 0.2
0.4 VDD
0.4 VDD + 0.2
VLC4 Output
Voltage
VLC4
0.2 VDD - 0.2
0.2 VDD
0.2 VDD + 0.2
V
14-3
ELECTRICAL DATA
KS57C21832/P21832
Table 14-2. D.C. Electrical Characteristics (Concluded)
(TA = - 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Supply
Current
Symbol
IDD1
(2)
IDD2 (2)
Conditions
Min
Typ
Max
Units
–
5.1
3.9
10.0
7.5
mA
6.0 MHz
4.19 MHz
2.5
1.8
4.0
3.0
Idle mode;
VDD = 5 V ± 10%
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
4.19 MHz
1.3
1.2
2.5
1.8
VDD = 3 V ± 10%
6.0 MHz
4.19 MHz
0.5
0.44
1.5
1.0
22.8
35
VDD = 5 V ± 10%
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
4.19 MHz
VDD = 3 V ± 10%
IDD3 (3)
VDD = 3 V ± 10%
32 kHz crystal oscillator
IDD4 (3)
Idle mode; VDD = 3 V ± 10%
32 kHz crystal oscillator
6.4
15
Stop mode;
VDD = 5 V ± 10%
SCMOD =
0000B
2.5
5
Stop mode;
VDD = 3 V ± 10%
XT = 0V
0.5
3
Stop mode;
VDD = 5 V ± 10%
SCMOD =
0100B
0.2
3
0.1
2
IDD5
Stop mode;
VDD = 3 V ± 10%
–
NOTES:
1. Data includes power consumption for subsystem clock oscillation.
2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
3. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
output port drive currents.
14-4
µA
KS57C21832/P21832
ELECTRICAL DATA
Table 14-3. Main System Clock Oscillator Characteristics
(TA = - 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Ceramic
Oscillator
Clock
Configuration
XIN
XOUT
C1
Parameter
Test Condition
Min
Typ
Max
Units
Oscillation frequency (1)
–
0.4
–
6.0
MHz
Stabilization occurs
when VDD is equal
to the minimum
oscillator voltage
range; VDD = 3.0 V.
–
–
4
ms
–
0.4
–
6.0
MHz
VDD = 3.0 V
–
–
10
ms
C2
Stabilization time (2)
Crystal
Oscillator
XIN
XOUT
C1
Oscillation frequency (1)
C2
Stabilization time (2)
External
Clock
RC
Oscillator
XIN
XOUT
XIN
XOUT
VDD = 2.0 V to 5.5 V
–
–
30
(1)
–
0.4
–
6.0
MHz
XIN input high and low
level width (tXH, tXL)
–
83.3
–
1250
ns
R = 20 kΩ,
VDD = 5 V
–
2
–
MHz
R = 39 kΩ,
VDD = 3 V
–
1
–
XIN input frequency
Frequency
R
NOTES:
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
14-5
ELECTRICAL DATA
KS57C21832/P21832
Table 14-4. Recommended Oscillator Constants
(TA = - 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Manufacturer
TDK
Series
Number (1)
Frequency Range
Oscillator Voltage
Range (V)
C1
C2
MIN
MAX
Remarks
FCR
M5
3.58 MHz-6.0 MHz
33
33
2.0
5.5
Leaded Type
FCR
MC5
3.58 MHz-6.0 MHz
(2)
(2)
2.0
5.5
On-chip C
Leaded Type
CCR
MC3
3.58 MHz-6.0 MHz
(3)
(3)
2.0
5.5
On-chip C
SMD Type
NOTES:
1. Please specify normal oscillator frequency.
2. On-chip C: 30pF built in.
3. On-chip C: 38pF built in.
14-6
Load Cap (pF)
KS57C21832/P21832
ELECTRICAL DATA
Table 14-5. Subsystem Clock Oscillator Characteristics
(TA = - 40 °C + 85 °C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock
Configuration
Crystal
Oscillator
XTIN XTOUT
C1
Parameter
Test Condition
Min
Typ
Max
Units
–
32
32.768
35
kHz
VDD = 2.7 V to 5.5 V
–
1.0
2
s
VDD = 2.0 V to 5.5 V
–
–
10
XTIN input
frequency (1)
–
32
–
100
kHz
XTIN input high and
low level width
(tXTL, tXTH)
–
5
–
15
µs
Oscillation
frequency (1)
C2
Stabilization time (2)
External
Clock
XTIN XTOUT
NOTES:
1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
Table 14-6. Input/Output Capacitance
(TA = 25 °C, VDD = 0 V )
Symbol
Condition
Min
Typ
Max
Units
Input
Capacitance
Parameter
CIN
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
pF
Output
Capacitance
COUT
–
–
15
pF
CIO
–
–
15
pF
I/O Capacitance
14-7
ELECTRICAL DATA
KS57C21832/P21832
Table 14-7. A.C. Electrical Characteristics
(TA = - 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Instruction Cycle
Time (note)
TCL0, TCL1 Input
Frequency
Symbol
tCY
fTI0, fTI1
Conditions
Min
Typ
Max
Units
VDD = 2.7 V to 5.5 V
0.67
–
64
µs
VDD = 2.0 V to 5.5 V
0.95
VDD = 2.7 V to 5.5 V
0
64
–
VDD = 2.0 V to 5.5 V
TCL0, TCL1 Input
High, Low Width
SCK Cycle Time
SCK High, Low
Width
SI Setup Time to
SCK High
SI Hold Time to
SCK High
tTIH0, tTIL0
tTIH1, tTIL1
tKCY
tKH, tKL
tSIK
tKSI
1.5
MHz
1
VDD = 2.7 V to 5.5 V
0.48
VDD = 2.0 V to 5.5 V
1.8
VDD = 2.7 V to 5.5 V; Input
800
Internal SCK source; Output
650
VDD = 2.0 V to 5.5 V; Input
3200
Internal SCK source; Output
3800
VDD = 2.7 V to 5.5 V; Input
325
Internal SCK source; Output
tKCY/250
VDD = 2.0 V to 5.5 V; Input
1600
Internal SCK source; Output
tKCY/2150
VDD = 2.7 V to 5.5 V; Input
100
VDD = 2.7 V to 5.5 V; Output
150
VDD = 2.0 V to 5.5 V; Input
150
VDD = 2.0 V to 5.5 V; Output
500
VDD = 2.7 V to 5.5 V; Input
400
VDD = 2.7 V to 5.5 V; Output
400
VDD = 2.0 V to 5.5 V; Input
600
VDD = 2.0 V to 5.5 V; Output
500
–
–
µs
–
–
ns
–
–
ns
–
–
ns
–
–
ns
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.
14-8
KS57C21832/P21832
ELECTRICAL DATA
Table 14-7. A.C. Electrical Characteristics (Continued)
(TA = - 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Output Delay for
SCK to SO
Symbol
Conditions
tKSO
VDD = 2.7 V to 5.5 V; Input
Interrupt Input
High, Low Width
tINTH, tINTL
RESET Input Low
Width
tRSL
Min
Typ
Max
Units
–
–
300
ns
VDD = 2.7 V to 5.5 V; Output
250
VDD = 2.0 V to 5.5 V; Input
1000
VDD = 2.0 V to 5.5 V; Output
1000
INT0, INT1, INT2, INT4,
K0-K7
10
–
–
µs
Input
10
–
–
µs
NOTE: Minimum value for INT0 is based on a clock of 2tCY or 128/fx as assigned by the IMOD0 register setting.
Main Oscillator Frequency
(Divided by 4)
CPU Clock
6 MHz
1.5 MHz
4.2 MHz
1.05 MHz
3 MHz
750 kHz
15.6 kHz
1
2
3
4
5
6
7
1.8 V
Supply Voltage (V)
CPU clock = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 14-1. Standard Operating Voltage Range
14-9
ELECTRICAL DATA
KS57C21832/P21832
Table 14-8. RAM Data Retention Supply Voltage in Stop Mode
(TA = - 40 °C to + 85 °C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply voltage
VDDDR
–
1.8
–
5.5
V
Data retention supply current
IDDDR
–
0.1
10
µA
Release signal set time
tSREL
0
–
–
µs
Oscillator stabilization wait
time (1)
tWAIT
Released by RESET
–
217/fx
–
ms
Released by interrupt
–
(2)
–
VDDDR = 1.8 V
–
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
14-10
KS57C21832/P21832
ELECTRICAL DATA
TIMING WAVEFORMS
Internal RESET
Operation
~
~
Idle Mode
Stop Mode
Data Retention Mode
Normal Mode
~
~
VDD
VDDDR
Execution of
STOP Instrction
RESET
tWAIT
tSREL
Figure 14-2. Stop Mode Release Timing When Initiated by RESET
Idle Mode
~
~
Normal Mode
Stop Mode
Data Retention Mode
~
~
VDD
VDDDR
Execution of
STOP Instrction
tSREL
tWAIT
Power-down Mode Terminating Signal
(Interrupt Request)
Figure 14-3. Stop Mode Release Timing When Initiated by Interrupt Request
14-11
ELECTRICAL DATA
KS57C21832/P21832
0.8 VDD
0.8 VDD
Measurement
Points
0.2 VDD
0.2 VDD
Figure 14-4. A.C. Timing Measurement Points (Except for XIN and XTIN)
1/fx
tXL
tXH
XIN
VDD - 0.1 V
0.1 V
Figure 14-5. Clock Timing Measurement at XIN
1/fxt
tXTL
tXTH
XTIN
VDD - 0.1 V
0.1 V
Figure 14-6. Clock Timing Measurement at XTIN
14-12
KS57C21832/P21832
ELECTRICAL DATA
1/fTI
tTIL
tTIH
TCL0
0.8 VDD
0.2 VDD
Figure 14-7. TCL Timing
tRSL
RESET
0.2 VDD
Figure 14-8. Input Timing for RESET Signal
tINTL
INT0, 1, 2, 4,
K0 to K7
tINTH
0.8 VDD
0.2 VDD
Figure 14-9. Input Timing for External Interrupts and Quasi-Interrupts
14-13
ELECTRICAL DATA
KS57C21832/P21832
tKCY
tKL
tKH
SCK
0.8 VDD
0.2 VDD
tSIK
tKSI
0.8 VDD
SI
Input Data
0.2 VDD
tKSO
SO
Output Data
Figure 14-10. Serial Data Transfer Timing
14-14
KS57C21832/P21832
15
MICHANICAL DATA
MICHANICAL DATA
OVERVIEW
The KS57C21832 microcontrollers are available in a 100-QFP-1420C package.
23.90 ± 0.3
0-8
14.00 ± 0.2
± 0.2
0.15
#1
0.65
0.80 ± 0.20
#100
0.3 ± 0.1
+0.10
-0.05
0.10 MAX
100-QFP-1420C
(0.83)
17.90 ± 0.3
20.00
(0.58)
0.05 MIN
0.10 MAX
2.65 ± 0.10
3.00 MAX
0.80 ± 0.20
NOTE : Dimensions are in millimeters.
Figure 15-1. 100-QFP Package Dimension
15-1
MICHANICAL DATA
KS57C21832/P21832
NOTES
15-2
KS57C21832/P21832
16
KS57P21832 OTP
KS57P21832 OTP
OVERVIEW
The KS57P21832 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
KS57C21832 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by
serial data format.
The KS57P21832 is fully compatible with the KS57C21832, both in function and in pin configuration. Because of
its simple programming requirements, the KS57P21832 is ideal for use as an evaluation chip for the
KS57C21832.
16-1
KS57C21832/P21832
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
KS57P21832 OTP
SEG4
SEG3
SEG2
SEG1
SEG0
VLC5
VLC4
VLC3
VLC2
VLC1
P0.0/SCK/K0
P0.1/SO/K1
SDAT /P0.2/SI/K2
SCLK /P0.3/BUZ/K3
VDD/VDD
VSS/VSS
XOUT
XIN
VPP/TEST
XTIN
XTOUT
RESET/RESET
KS57P21832
(100-QFP-1420C)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
P9.3/SEG40
P9.2/SEG41
P9.1/SEG42
P9.0/SEG43
P8.3/SEG44
P8.2/SEG45
P8.1/SEG46
P8.0/SEG47
P7.3/SEG48
P7.2/SEG49
P7.1/SEG50
P7.0/SEG51
P6.3/SEG52/K7
P6.2/SEG53/K6
P6.1/SEG54/K5
P3.1/TCLO1
P3.2/TCL0
P3.3/TCL1
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
P4.0/COM8
P4.1/COM9
P4.2/COM10
P4.3/COM11
P5.0/COM12
P5.1/COM13
P5.2/COM14
P5.3/COM15
P6.0/SEG55/K4
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P2.0/CLO
P2.1/LCDCK
P2.2/LCDSY
P3.0/TCLO0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NOTE:
The bolds indicate an OTP pin name.
Figure 16-1. KS57P21832 Pin Assignments (100-QFP Package)
16-2
KS57C21832/P21832
KS57P21832 OTP
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P0.2
SDAT
13
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input / push-pull output port.
P0.3
SCLK
14
I/O
Serial clock pin. Input only pin.
TEST
VPP (TEST)
19
I
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading
mode. (Option)
RESET
RESET
22
I
Chip initialization
VDD/VSS
VDD/VSS
15/16
I
Logic power supply pin. VDD should be tied to
+ 5 V during programming.
Table 16-2. Comparison of KS57P21832 and KS57C21832 Features
Characteristic
KS57P21832
KS57C21832
Program Memory
32 Kbyte EPROM
32 Kbyte mask ROM
Operating Voltage (VDD)
1.8 V to 5.5 V
1.8 V to 5.5 V
OTP Programming Mode
VDD = 5 V, VPP (TEST) = 12.5 V
Pin Configuration
100 QFP
100 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP(TEST) pin of the KS57P21832, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 16-3 below.
Table 16-3. Operating Mode Selection Criteria
VDD
VPP
(TEST)
REG/
MEM
Address
(A15-A0)
R/W
5V
5V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
Mode
NOTE: "0" means Low level; "1" means High level.
16-3
KS57P21832 OTP
KS57C21832/P21832
Table 16-4. D.C. Electrical Characteristics
(TA = - 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Supply
Current
Symbol
IDD1
(2)
IDD2 (2)
Conditions
Min
Typ
Max
Units
–
5.1
3.9
10.0
7.5
mA
6.0 MHz
4.19 MHz
2.5
1.8
4.0
3.0
Idle mode;
VDD = 5 V ± 10%
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
4.19 MHz
1.3
1.2
2.5
1.8
VDD = 3 V ± 10%
6.0 MHz
4.19 MHz
0.5
0.44
1.5
1.0
22.8
35
VDD = 5 V ± 10%
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
4.19 MHz
VDD = 3 V ± 10%
IDD3 (3)
VDD = 3 V ± 10%
32 kHz crystal oscillator
IDD4 (3)
Idle mode; VDD = 3 V ± 10%
32 kHz crystal oscillator
6.4
15
Stop mode;
VDD = 5 V ± 10%
SCMOD =
0000B
2.5
5
Stop mode;
VDD = 3 V ± 10%
XT = 0V
0.5
3
Stop mode;
VDD = 5 V ± 10%
SCMOD =
0100B
0.2
3
0.1
2
IDD5
Stop mode;
VDD = 3 V ± 10%
–
NOTES:
1. Data includes power consumption for subsystem clock oscillation.
2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
3. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
output port drive currents.
16-4
µA
KS57C21832/P21832
KS57P21832 OTP
Main Oscillator Frequency
(Divided by 4)
CPU Clock
1.5 MHz
6 MHz
1.05 MHz
4.2 MHz
750 kHz
3 MHz
15.6 kHz
1
2
3
4
5
6
7
1.8 V
Supply Voltage (V)
CPU clock = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 16-2. Standard Operating Voltage Range
16-5
KS57P21832 OTP
KS57C21832/P21832
NOTES
16-6