S3C8248/C8245/P8245/C8247/C8249/P8249 1 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8-SERIES MICROCONTROLLERS Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are: — Efficient register-oriented architecture — Selectable CPU clock sources — Idle and Stop power-down mode release by interrupt — Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned to specific interrupt levels. S3C8248/C8245/P8245/C8247/C8249/P8249 MICROCONTROLLER The S3C8248/C8245/P8245/C8247/C8249/P8249 single-chip CMOS microcontroller are fabricated using the highly advanced CMOS process, based on Samsung’s newest CPU architecture. — Six programmable I/O ports, including five 8-bit ports and one 5-bit port, for a total of 45 pins. The S3C8248, S3C8245, S3C8247, S3C8249 are a microcontroller with a 8K-byte, 16K-byte, 24K-byte. 32K-byte mask-programmable ROM embedded respectively. — One 8-bit basic timer for oscillation stabilization and watchdog functions (system reset). The S3P8245 is a microcontroller with a 16K-byte one-time-programmable ROM embedded. The S3P8249 is a microcontroller with a 32K-byte one-time-programmable ROM embedded. — Watch timer for real time. Using a proven modular design approach, Samsung engineers have successfully developed the S3C8248/C8245/P8245/C8247/C8249/P8249 by integrating the following peripheral modules with the powerful SAM8 core: The S3C8248/C8245/P8245/C8247/C8249/P8249 is versatile microcontroller for camera, LCD and ADC application, etc. They are currently available in 80-pin TQFP and 80-pin QFP package — Eight bit-programmable pins for external interrupts. — Two 8-bit timer/counter and two 16-bit timer/counter with selectable operating modes. — 8-input A/D converter — Serial I/O interface OTP The S3P8245/P8249 are OTP (One Time Programmable) version of the S3C8245/C8249 microcontroller. The S3P8245 microcontroller has an on-chip 16K-byte one-time-programmable EPROM instead of a masked ROM. The S3P8249 microcontroller has an on-chip 32K-byte one-time-programmable EPROM instead of a masked ROM. The S3P8245 is comparable to the S3P8245, both in function and in pin configuration. The S3P8249 is comparable to the S3P8249, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C8248/C8245/P8245/C8247/C8249/P8249 FEATURES Memory 45 I/O Pins • • • • • • ROM: 32K-byte (S3C8249/P8249) ROM: 16K-byte (S3C8245/P8245) RAM: 1056-Byte (S3C8249/P8249, S3C8247) RAM: 544-Byte (S3C8245/P8245, S3C8248) Data memory mapped I/O Oscillation Sources • • • • • Crystal, ceramic, RC (main) Crystal for subsystem clock Main system clock frequency 1-10 MHz (3 MHz at 1.8 V, 10 MHz at 2.7 V) Subsystem clock frequency: 32.768 kHz CPU clock divider (1/1, 1/2, 1/8, 1/16) 45 configurable I/O pins Basic Timer • • Overflow signal makes a system reset. Watchdog function 8-Bit Timer/Counter A • • • Programmable 8-bit timer Interval, capture, PWM mode Match/capture, overflow interrupt 8-Bit Timer/Counter B • • Programmable 8-bit timer Carrier frequency generator Two Power-Down Modes 16-Bit Timer/Counter 0 • • • • Idle (only CPU clock stops) Stop (System clock stops) Programmable 16-bit timer Match interrupt generates Interrupts 16-Bit Timer/Counter 1 • • • • • 6 level 8 vector 8 internal interrupt 2 level 8 vector 8 external interrupt Programmable 16-bit timer Interval, capture, PWM mode Match/capture, overflow interrupt Watch Timer Voltage Detector • • • • Real-time and interval time measurement Clock generation for LCD Four frequency outputs for buzzer sound • Programmable detection voltage (2.2 V, 2.4 V, 3.0 V, 4.0 V) En/Disable S/W selectable LCD Controller/Driver Instruction Execution Times • • • • • Maximum 16-digit LCD direct drive capability Display modes: static, 1/2 duty (1/2 bias) 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) 400 ns at 10 MHz (main) 122 us at 32.768 kHz (subsystem) Operating Temperature Range -40 °C to 85 °C A/D Converter • • • Eight analog input channels 50 µs conversion speed at 1 MHz fADC clock Operating Voltage Range • 10-bit conversion resolution 8-Bit Serial I/O Interface • • • • 8-bit transmit/receive mode 8-bit receive mode LSB-first/MSB-first transmission selectable Internal/external clock source • 1.8 V to 5.5 V Package Type • • 80-pin QFP 80-pin TQFP S3C8249’s ROM version device • S3C8247 (ROM 24K-byte) Voltage Booster S3C8245’s ROM version device • • • • 1-2 LCD display voltage supply S/W control en/disable 3.0 V drive S3C8248 (ROM 8K-byte) S3C8248/C8245/P8245/C8247/C8249/P8249 PRODUCT OVERVIEW BLOCK DIAGRAM XIN XTIN TAOUT/TAPWM/P3.1 TACLK/P3.2 TACAP/P3.3 8-Bit Timer/ Counter A TBPWM/P3.0 8-Bit Timer/ Counter B RESET XOUT XTOUT BUZ/P1.4 Voltage Detector OSC/ RESET Basic Timer Watch Timer Voltage Booster 16-Bit Timer/ Counter 0 T1CAP/P1.0 T1CLK/P1.1 T1OUT/T1PWM/P1.2 16-Bit Timer/ Counter 1 P0.0-P0.7/ INT0-INT7 I/O Port 0 P1.0-P1.7 I/O Port 1 AVREF AVSS A/D Converter P2.0-P2.7/ ADC0-ADC7 I/O Port 2 P3.0-P3.4 I/O Port 3 VVLDREF CB CA VLC0-VLC2 I/O Port and Interrupt Control LCD Driver COM0-COM3 SEG0-SEG15 SEG16-SEG31 SAM88 RC CPU 544/1056 Byte Register File Serial I/O Port SI/P1.7 SO/P1.5 SCK/P1.6 I/O Port 4 P4.0-P4.7 I/O Port 5 P5.0-P5.7 16/32-Kbyte ROM Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW S3C8248/C8245/P8245/C8247/C8249/P8249 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 SEG25/P5.1 SEG24/P5.0 SEG23/P4.7 SEG22/P4.6 SEG21/P4.5 SEG20/P4.4 SEG19/P4.3 SEG18/P4.2 SEG17/P4.1 SEG16/P4.0 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 PIN ASSIGNMENT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 S3C8248/C8245 /C8247/C8249 (80-QFP-1420C) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 VLC2 VLC1 VLC0 CA CB AVSS AVREF P2.7/ADC7/VVLDREF P2.6/ADC6 P2.5/ADC5 P0.5/INT5 P0.6/INT6 P0.7/INT7 P1.0/T1CAP P1.1/T1CLK P1.2/T1OUT/T1PWM P1.3 P1.4/BUZ P1.5/SO P1.6/SCK P1.7/SI P2.0/ADC0 P2.1/ADC1 P2.2/ADC3 P2.3/ADC4 P2.4/ADC4 25 26 27 28 28 30 31 32 33 34 35 36 37 38 39 40 SEG26/P5.2 SEG27/P5.3 SEG28/P5.4 SEG29/P5.5 SEG30/P5.6 SEG31/P5.7 P3.0/TBPWM P3.1/TAOUT/TAPWM P3.2/TACLK P3.3/TACAP/SDAT P3.4/SCLK VDD VSS XOUT XIN TEST XTIN XTOUT RESET P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3/INT3 P0.4/INT4 Figure 1-2. S3C8248/C8245/C8247/C8249 Pin Assignments (80-QFP) 1-4 PRODUCT OVERVIEW 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 SEG25/P5.1 SEG24/P5.0 SEG23/P4.7 SEG22/P4.6 SEG21/P4.5 SEG20/P4.4 SEG19/P4.3 SEG18/P4.2 SEG17/P4.1 SEG16/P4.0 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 S3C8248/C8245/P8245/C8247/C8249/P8249 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 S3C8248/C8245 /C8247/C8249 (80-TQFP-1212) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 VLC2 VLC1 VLC0 CA CB AVSS AVREF P2.7/ADC7/VVLDREF P2.6/ADC6 P2.5/ADC5 P0.1/INT1 P0.2/INT2 P0.3/INT3 P0.4/INT4 P0.5/INT5 P0.6/INT6 P0.7/INT7 P1.0/T1CAP P1.1/T1CLK P1.2/T1OUT/T1PWM P1.3 P1.4/BUZ P1.5/SO P1.6/SCK P1.7/SI P2.0/ADC0 P2.1/ADC1 P2.2/ADC3 P2.3/ADC4 P2.4/ADC4 21 22 23 24 25 26 27 28 28 30 31 32 33 34 35 36 37 38 39 40 SEG26/P5.2 SEG27/P5.3 SEG28/P5.4 SEG29/P5.5 SEG30/P5.6 SEG31/P5.7 P3.0/TBPWM P3.1/TAOUT/TAPWM P3.2/TACLK P3.3/TACAP/SDAT P3.4/SCLK VDD VSS XOUT XIN TEST XTIN XTOUT RESET P0.0/INT0 Figure 1-3. S3C8248/C8245/C8247/C8249 Pin Assignments (80-TQFP) 1-5 PRODUCT OVERVIEW S3C8248/C8245/P8245/C8247/C8249/P8249 PIN DESCRIPTIONS Table 1-1. S3C8248/C8245/C8247/C8249 Pin Descriptions Pin Names Pin Type Pin Description Circuit Type Pin Numbers (note) Share Pins P0.0–P0.7 I/O I/O port with bit programmable pins; Schmitt trigger input or output mode selected by software; software assignable pull-up. P0.0–P0.7 can be used as inputs for external interrupts INT0–INT7 (with noise filter and interrupt control). D–4 20–27 INT0–INT7 P1.0–1.7 I/O I/O port with bit programmable pins; Input or output mode selected by software; Open-drain output mode can be selected by software; software assignable pull-up. Alternately P1.0–P1.7 can be used as SI, SO, SCK, BUZ, T1CAP, T1CLK, T1OUT, T1PWM E–2 28-35 SI, SO, SCK, BUZ, T1CAP I/O port with bit programmable pins; normal input and AD input or output mode selected by software; software assignable pull-up. F–10 F–18 36–42, 43 ADC0–ADC6 I/O port with bit programmable pins. Input or push-pull output with software assignable pull-up. Alternately P3.0–P3.3 can be used as TACAP, TACLK, TAOUT, TAPWM, TBPWM D–2 7–11 TACAP P2.0–P2.7 P3.0–P3.4 I/O I/O T1CLK T1OUT T1PWM VVLDREF (ADC7) TACLK TAOUT TAPWM TBPWM P4.0–P4.7 I/O I/O port with bit programmable pins. Push-pull or open drain output and input with software assignable pull-up. P4.0–P4.7 can alternately be used as outputs for LCD SEG H–14 71–78 SEG16–SEG23 P5.0–P5.7 I/O Have the same characteristic as port 4 H–14 79–6 SEG24–SEG31 1-6 S3C8248/C8245/P8245/C8247/C8249/P8249 PRODUCT OVERVIEW Table 1-1. S3C8248/C8245/C8247/C8249 Pin Descriptions (Continued) Pin Names Pin Type Pin Description Circuit Type Pin Numbers (note) Share Pins F–10 F–18 36–42 43 P2.0–P2.6 P2.7 ADC0–ADC6 ADC7 I A/D converter analog input channels AVREF – A/D converter reference voltage – 44 – AVSS – A/D converter ground – 45 – INT0–INT7 I External interrupt input pins D–4 20–27 P0.0–P0.7 RESET I System reset pin (pull-up resistor: 250 kΩ) B 19 – TEST I 0 V: Normal MCU operating 5 V: Test mode 12 V: for OTP writing – 16 – SDAT, SCLK O Serial OTP interface pins; serial data and clock D–2 10, 11 P3.3, P3.4 VDD, VSS – Power input pins for CPU operation (internal) and Power input for OTP Writing – 12, 13 – XOUT, XIN – Main oscillator pins – 14, 15 – Serial I/O interface clock signal E–2 33–35 P1.5–P1.7 SCK, SO, SI I/O VVLDREF I Voltage detector reference voltage input F–18 43 P2.7 TACAP I Timer A Capture input D–2 10 P3.3 TACLK I Timer A External clock input D–2 9 P3.2 TAOUT/TAPWM O Timer A output and PWM output D–2 8 P3.1 TBPWM O Timer B PWM output D–2 7 P3.0 T1CAP I Timer 1 Capture input E–2 28 P1.0 T1CLK I Timer 1 External clock input E–2 29 P1.1 T1OUT/T1PWM O Timer 1 output and PWM output E–2 30 P1.2 COM0–COM3 O LCD common signal output H 51–54 – SEG0–SEG15 O LCD segment output H 55–70 – SEG16–SEG23 O LCD segment output H–14 71–78 P4.0–P4.7 SEG24–SEG31 O LCD Segment output H–14 79–6 P5.0–P5.7 VLC0–VLC2 O LCD power supply – 48–50 – BUZ O 0.5, 1, 2 or 4 kHz frequency output for buzzer sound with 4.19 MHz main system clock or 32768 Hz subsystem clock E–2 32 P1.4 CA, CB – Capacitor terminal for voltage booster – 46–47 – 1-7 PRODUCT OVERVIEW S3C8248/C8245/P8245/C8247/C8249/P8249 PIN CIRCUITS VDD VDD Pull-up Enable P-Channel Data Circuit Type C Output Disable In Figure 1-4. Pin Circuit Type B (RESET RESET) I/O Figure 1-6. Pin Circuit Type D-2 (P3) VDD V DD Data VDD P-Channel Out Output Disable Data Output Disable Pin Circuit Type C Pull-up Enable I/O N-Channel Ext.INT Noise Filter Input Normal Figure 1-5. Pin Circuit Type C 1-8 Figure 1-7. Pin Circuit Type D-4 (P0) S3C8248/C8245/P8245/C8247/C8249/P8249 PRODUCT OVERVIEW VDD VDD Open drain Enable VDD Pull-up Resistor P-CH Data I/O Pull-up Enable Data Output Disable Circuit Type C I/O N-CH ADC & VLD Enable Output Disable Data VLDREF Schmitt Trigger To ADC Figure 1-8. Pin Circuit Type E-2 (P1) Figure 1-10. Pin Circuit Type F-18 (P2.7/VLDREF) VDD VLC2 Pull-up Enable Data Output Disable VLC1 Circuit Type C I/O SEG/ COM Out ADCEN VLC0 Data To ADC Figure 1-9. Pin Circuit Type F-10 (P2.0–P2.6) Figure 1-11. Pin Circuit Type H (SEG/COM) 1-9 PRODUCT OVERVIEW S3C8248/C8245/P8245/C8247/C8249/P8249 VLC2 VLC1 SEG Output Disable VLC0 Figure 1-12. Pin Circuit Type H-4 VDD VDD Open Drain EN Pull-up Enable Data LCD Out EN SEG Circuit Type H-4 Output Disable Figure 1-13. Pin Circuit Type H-14 (P4, P5) 1-10 S3C8248/C8245/P8245/C8247/C8249/P8249 19 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this chapter, S3C8248/C8245/C8247/C8249 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — Input/output capacitance — D.C. electrical characteristics — A.C. electrical characteristics — Oscillation characteristics — Oscillation stabilization time — Data retention supply voltage in stop mode — Serial I/O timing characteristics — A/D converter electrical characteristics 19-1 ELECTRICAL DATA S3C8248/C8245/P8245/C8247/C8249/P8249 Table 19-1. Absolute Maximum Ratings (TA= 25 °C) Parameter Symbol Conditions Rating VDD Supply voltage Unit – 0.3 to +6.5 V Input voltage VI – 0.3 to VDD + 0.3 Output voltage VO – 0.3 to VDD + 0.3 Output current high IOH IOL Output current low Operating temperature Storage temperature One I/O pin active – 18 mA All I/O pins active – 60 One I/O pin active + 30 Total pin current for port + 100 TA – 40 to + 85 TSTG – 65 to + 150 °C Table 19-2. D.C. Electrical Characteristics (TA = -40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Operating voltage Input high voltage Input low voltage 19-2 Symbol VDD Conditions Min Typ Max Unit f CPU = 10 MHz 2.7 – 5.5 V f CPU = 3 MHz 1.8 – 5.5 VDD VIH1 All input pins except VIH2 0.8 VDD – VIH2 XIN, XTIN VDD-0.1 – VIL1 All input pins except VIL2 – – VIL2 XIN, XTIN 0.2 VDD 0.1 S3C8248/C8245/P8245/C8247/C8249/P8249 ELECTRICAL DATA Table 19-2. D.C. Electrical Characteristics (Continued) (TA = -40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Symbol Output high voltage VOH Output low voltage Input high leakage current Min Typ Max Unit VDD = 5 V; IOH = -1 mA All output pins VDD–1.0 – – V VOL VDD = 5 V; IOL = 2 mA All output pins – – 0.4 ILIH1 VIN = VDD All input pins except ILIH2 – – 3 ILIH2 VIN = VDD, XIN, XTIN ILIL1 VIN = 0 V All input pins except ILIL2 ILIL2 VIN = 0 V, XIN, XTIN, Output high leakage current ILOH VOUT = VDD All I/O pins and output pins – – 3 Output low leakage current ILOL VOUT = 0 V All I/O pins and output pins – – -3 Oscillator feed back resistors Rosc1 VDD = 5.0 V TA = 25 °C XIN = VDD, XOUT = 0 V 800 1000 1200 Pull-up resistor RL1 VIN = 0 V; VDD = 5 V ±10 % 25 50 100 VIN = 0 V; VDD = 5 V ±10% 110 210 310 TA = 25 °C, (1/3 bias mode) 0.9 1.0 1.1 TA = 25 °C, (1/2 bias mode) 1.4 1.5 1.7 Input low leakage current Conditions uA 20 – – -3 -20 RESET kΩ Port 0,1,2,3,4,5 TA = 25°C RL2 TA=25 °C, RESET only VLC0 out voltage (Booster run mode) VLC0 VLC1 out voltage (Booster run mode) VLC1 TA = 25 °C (1/2 and 1/3 bias mode) 2VLC0 - 0.1 – 2VLC0 + 0.1 VLC2 out voltage (Booster run mode) VLC2 TA = 25 °C (1/3 bias mode) 3VLC0 - 0.1 – 3VLC0 + 0.1 COM output voltage deviation VDC VDD = VLC2 = 3 V (VLCD-COMi) IO = ± 15 µA (i = 0-3) – ± 60 ± 120 SEG output voltage deviation VDs VDD = VLC2 = 3 V (VLCD-SEGi) IO = ± 15 µA (i = 0-31) – ± 60 ± 120 V mV 19-3 ELECTRICAL DATA S3C8248/C8245/P8245/C8247/C8249/P8249 Table 19-2. D.C. Electrical Characteristics (Concluded) (TA = -40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Supply current (1) Symbol IDD1 (2) IDD2 Conditions Min Typ Max Unit – 12 25 mA 3 MHz crystal oscillator 4 10 VDD = 3 V ± 10 % 10 MHz crystal oscillator 3 8 3 MHz crystal oscillator 1 5 3 10 3 MHz crystal oscillator 1.5 4 Idle mode: VDD = 3 V± 10 % 10 MHz crystal oscillator 1.2 3 3 MHz crystal oscillator 0.5 1.5 VDD = 5 V ± 10 % 10 MHz crystal oscillator Idle mode: VDD = 5 V ± 10 % 10 MHz crystal oscillator – IDD3 Sub operating: main-osc stop VDD = 3 V ± 10 % 32768 Hz crystal oscillator – 20 40 IDD4 Sub idle mode: main-osc stop VDD = 3 V ± 10 % 32768 Hz crystal oscillator – 7 14 IDD5 Main stop mode : sub-osc stop VDD = 5 V ± 10 % – 1 3 0.5 2 VDD = 3 V ± 10 % NOTES: 1. Supply current does not include current drawn through internal pull-up resistors or external output current loads. 2. IDD1 and IDD2 include a power consumption of subsystem oscillator. 3. IDD3 and IDD4 are the current when the main system clock oscillation stop and the subsystem clock is used. 4. 5. And does not include the LCD and Voltage booster and voltage level detector IDD5 is the current when the main and subsystem clock oscillation stop. Voltage booster’s operating voltage range is 2.0 V to 5.5 V. The range of 1.8 V to 2.0 V could be referenced in page 17-4. 19-4 uA S3C8248/C8245/P8245/C8247/C8249/P8249 ELECTRICAL DATA In case of S3C8248/C8245, the characteristic of VOH and VOL is differ with the characteristic of S3C8247/C8249 like as following. Other characteristics are same each other. Table 19-3. D.C Electrical Characteristics of S3C8248/C8245 (TA = -40 °C to +85 °C, VDD = 1.8 V to 5.5 V) Parameter Symbol Output high voltage VOH1 Output low voltage Conditions Min Typ Max Unit VDD = 5 V; IOH = -1 mA All output pins except VOH2 VDD-1.0 – – V VOH2 VDD = 5 V; IOH = -6 mA Port 3.0 only in S3C8248/C8245 VDD-0.7 VOL1 VDD = 5 V; IOL = 2 mA All output pins except VOL2 – 0.4 VOL2 VDD = 5 V; IOH = 12 mA Port 3.0 only in S3C8248/C8245 – 0.7 19-5 ELECTRICAL DATA S3C8248/C8245/P8245/C8247/C8249/P8249 Table 19-4. A.C. Electrical Characteristics (TA = -40 °C to +85 °C, VDD = 1.8 V to 5.5 V) Parameter Interrupt input high, low width (P0.0–P0.7) RESET input low width Symbol tINTH, tINTL tRSL Conditions P0.0–P0.7, VDD = 5 V VDD = 5 V Min Typ 200 – 1 – Max ns – NOTE: User must keep more large value then min value. tTIL tTIH 0.8 VDD 0.2 VDD 0.2 VDD Figure 19-1. Input Timing for External Interrupts (Ports 0) tRSL RESET 0.2 V DD Figure 19-2. Input Timing for RESET 19-6 Unit us S3C8248/C8245/P8245/C8247/C8249/P8249 ELECTRICAL DATA Table 19-5. Input/Output Capacitance (TA = -40 °C to +85 °C, VDD = 0 V ) Parameter Symbol Conditions Min Typ Max Unit Input capacitance CIN f = 1 MHz; unmeasured pins are returned to VSS – – 10 pF Output capacitance COUT CIO I/O capacitance Table 19-6. Data Retention Supply Voltage in Stop Mode (TA = -40 °C to + 85 °C) Parameter Symbol Data retention supply voltage VDDDR Data retention supply current IDDDR Conditions VDDDR = 2 V Min Typ Max Unit 2 – 5.5 V – – 3 uA RESET Occurs ~ ~ Stop Mode Oscillation Stabilization Time Normal Operating Mode Data Retention Mode ~ ~ VDD VDDDR Execution of STOP Instrction RESET 0.2 V DD NOTE: tWAIT tWAIT is the same as 4096 x 16 x 1/fxx Figure 19-3. Stop Mode Release Timing Initiated by RESET 19-7 ELECTRICAL DATA S3C8248/C8245/P8245/C8247/C8249/P8249 Oscillation Stabilization Time ~ ~ Idle Mode Stop Mode Data Retention Mode ~ ~ VDD VDDDR Normal Operating Mode Execution of STOP Instruction Interrupt 0.2 VDD NOTE: tWAIT tWAIT is the same as 4096 x 16 x BT clock Figure 19-4. Stop Mode (Main) Release Timing Initiated by Interrupts Oscillation Stabilization Time ~ ~ Idle Mode Stop Mode Data Retention Mode ~ ~ VDD VDDDR Normal Operating Mode Execution of STOP Instruction Interrupt 0.2 VDD tWAIT NOTE: When the case of select the fxx/128 for basic timer input clock before enter the stop mode. tWAIT = 128 x 16 x (1/32768) = 62.5 ms Figure 19-5. Stop Mode (Sub) Release Timing Initiated by Interrupts 19-8 S3C8248/C8245/P8245/C8247/C8249/P8249 ELECTRICAL DATA Table 19-7. A/D Converter Electrical Characteristics (TA = - 40 °C to +85 °C, VDD = 1.8 V to 5.5 V, VSS = 0 V) Parameter Symbol Conditions Min Typ Max Unit – 10 – bit – – ±3 LSB ILE – ±2 Differential Linearity Error DLE – ±1 Offset Error of Top EOT ±1 ±3 Offset Error of Bottom EOB ±0.5 ±2 Conversion time (1) tCON – – 40 – fxx Analog input voltage VIAN – AVSS – AVREF V Analog input impedance RAN – 2 1000 – Mohm Analog reference voltage AVREF – 2.5 – VDD V Analog ground AVSS – VSS – VSS + 0.3 Analog input current IADIN AVREF = VDD = 5 V – – 10 uA Analog block current (2) IADC AVREF = VDD = 5 V – 1 3 mA AVREF = VDD = 3 V 0.5 1.5 AVREF = VDD = 5 V When power down mode 100 500 Resolution VDD = 5 V Total accuracy AVREF = 5 V AVSS = 0 V Integral Error Linearity nA NOTES: 1. 'Conversion time' is the time required from the moment a conversion operation starts until it ends. 2. IADC is an operating current during A/D conversion. 19-9 ELECTRICAL DATA S3C8248/C8245/P8245/C8247/C8249/P8249 Table 19-8. Synchronous SIO Electrical Characteristics (TA = -40 °C to +85 °C, VDD = 1.8 V to 5.5 V, VSS = 0 V, fxx = 10 MHz oscillator) Parameter Symbol Conditions Min Typ Max Unit SCK Cycle time tCYC – 200 – – ns Serial Clock High Width tSCKH – 60 – – Serial Clock Low Width tSCKL – 60 – – Serial Output data delay time tOD – – – 50 Serial Input data setup time tID – 40 – – Serial Input data Hold time tIH – 100 – – tCYC tSCKL tSCKH SCK 0.8 VDD 0.2 VDD tID tIH 0.8 VDD SI Input Data 0.2 VDD tOD SO Output Data Figure 19-6. Serial Data Transfer Timing 19-10 S3C8248/C8245/P8245/C8247/C8249/P8249 ELECTRICAL DATA Table 19-9. Main Oscillator Frequency (fOSC1) (TA = -40 °C to +85 °C, VDD = 1.8 V to 5.5 V) Oscillator Crystal Clock Circuit XIN XOUT C1 Ceramic XIN Min Typ Max Unit Crystal oscillation frequency 1 – 10 MHz Ceramic oscillation frequency 1 – 10 MHz 1 – 10 MHz C2 XOUT C1 Test Condition C2 External clock XIN XOUT XIN input frequency RC XIN XOUT r = 35 kΩ, VDD = 5 V 2 MHz R Table 19-10. Main Oscillator Clock Stabilization Time (tST1) (TA = -40 °C to +85 °C, VDD = 4.5 V to 5.5 V) Oscillator Test Condition Min Typ Max Unit Crystal VDD = 4.5 V to 5.5 V – – 10 ms Ceramic Stabilization occurs when VDD is equal to the minimum oscillator voltage range. – – 4 ms External clock XIN input high and low level width (tXH, tXL) 50 – – ns NOTE: Oscillation stabilization time (tST1) is the time required for the CPU clock to return to its normal oscillation frequency after a power-on occurs, or when Stop mode is ended by a RESET signal. The RESET should therefore be held at low level until the tST1 time has elapsed 19-11 ELECTRICAL DATA S3C8248/C8245/P8245/C8247/C8249/P8249 1 / f OSC1 tXH tXL VDD – 0.5 V XIN 0.4 V Figure 19-7. Clock Timing Measurement at XIN Table 19-11. Sub Oscillator Frequency (fOSC2) (TA = -40 °C + 85 °C, VDD = 1.8 V to 5.5 V) Oscillator Crystal Clock Circuit XTIN Test Condition Crystal oscillation frequency XTOUT R C1 C2 Min Typ Max Unit 32 32.768 35 kHz C1 = 22 pF, C2 = 33 pF R = 39 KΩ XTIN and XTOUT are connected with R and C by soldering. Table 19-12. Sub Oscillator(crystal) Stabilization Time (tST2) (TA = 25 °C) Oscillator normal mode strong mode Test Condition Min Typ Max Unit VDD = 4.5 V to 5.5 V – 250 500 ms VDD = 1.8 V to 3.0 V – – 2 s VDD = 4.5 V to 5.5 V – – 2 s VDD = 1.8 V to 3.0 V – 250 500 ms NOTE: Oscillation stabilization time (tST2) is the time required for the oscillator to it’s normal oscillation when stop mode is released by interrupts. The value Typ and Max are measured by buzzer output signal after stop release. For example in voltage range of 4.5 V to 5.5 V of normal mode, we can see the buzzer output signal within 400 ms at our test condition. 19-12 S3C8248/C8245/P8245/C8247/C8249/P8249 ELECTRICAL DATA fCPU B 10 MHz 8 MHZ A 3 MHZ 1 MHz 1 2 3 1.8 2.7 4 5 6 7 5.5 Supply Voltage (V) Minimum instruction clock = 1/4 x oscillator frequency Figure 19-8. Operating Voltage Range 19-13 S3C8248/C8245/P8245/C8247/C8249/P8249 20 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C8248/C8245/C8247/C8249 microcontroller is currently available in 80-pin-QFP/TQFP package. 23.90 ± 0.30 20.00 ± 0.20 0-8 14.00 ± 0.20 + 0.10 - 0.05 0.10 MAX 80-QFP-1420C 0.80 ± 0.20 17.90 ± 0.30 0.15 #80 #1 0.80 0.35 + 0.10 0.05 MIN 0.15 MAX (0.80) 2.65 ± 0.10 3.00 MAX 0.80 ± 0.20 NOTE: Dimensions are in millimeters. Figure 20-1. Package Dimensions (80-QFP-1420C) 20-1 MECHANICAL DATA S3C8248/C8245/P8245/C8247/C8249/P8249 14.00 BSC 0-7 12.00 BSC 12.00 BSC 80-TQFP-1212 0.60 ± 0.15 14.00 BSC 0.09-0.20 #80 #1 0.50 0.17-0.27 0.08 MAX M 0.05-0.15 (1.25) 1.00 ± 0.05 1.20 MAX NOTE: Dimensions are in millimeters. Figure 20-2. Package Dimensions (80-TQFP-1212) 20-2 S3C8248/C8245/P8245/C8247/C8249/P8249 21 S3P8245/P8249 OTP S3P8245/P8249 OTP OVERVIEW The S3P8245/P8249 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C8248/C8245/C8247/C8249 microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is accessed by serial data format. The S3P8245/P8249 is fully compatible with the S3C8248/C8245/C8247/C8249, both in function and in pin configuration. Because of its simple programming requirements, the S3P8245/P8249 is ideal as an evaluation chip for the S3C8248/C8245/C8247/C8249. 21-1 S3C8248/C8245/P8245/C8247/C8249/P8249 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 SEG25/P5.1 SEG24/P5.0 SEG23/P4.7 SEG22/P4.6 SEG21/P4.5 SEG20/P4.4 SEG19/P4.3 SEG18/P4.2 SEG17/P4.1 SEG16/P4.0 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 S3P8245/P8249 OTP S3P8245/P8249 80-QFP (Top View) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 P0.5/INT5 P0.6/INT6 P0.7/INT7 P1.0/T1CAP P1.1/T1CLK P1.2//T1OUT/T1PWM P1.3 P1.4/BUZ P1.5/SIO P1.6/SCK P1.7/SI P2.0/ADC0 P2.1/ADC1 P2.2/ADC2 P2.3/ADC3 P2.4/ADC4 SEF26/P5.2 SEG27/P5.3 SEG28/P5.4 SEG29/P5.5 SEG30/P5.6 SEG31/P5.7 P3.0/TBPWM P3.1/TAOUT/TAPWM P3.2/TACLK P3.3/TACAP/SDAT P3.4/SCLK VDD VSS XOUT XIN VPP/TEST XTIN XTOUT RESET P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3/INT3 P0.4/INT4 Figure 21-1. Pin Assignments (80-QFP) 21-2 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 VLC2 VLC1 VLC0 CA CB AVSS AVREF P2.7/ADC7/VVLDREF P2.6/ADC6 P2.5/ADC5 S3C8248/C8245/P8245/C8247/C8249/P8249 S3P8245/P8249 OTP Table 21-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P2.0 SDAT 10 I/O P2.1 SCLK 11 I Serial clock pin. Input only pin. VPP TEST 16 I Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) RESET RESET 19 I Chip Initialization VDD/VSS VDD/VSS 12/13 – Logic power supply pin. VDD should be tied to +5 V during programming. Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. Table 21-2. Comparison of S3P8245/P8249 and S3C8248/C8245/C8247/C8249 Features Characteristic S3P8245/P8249 S3C8248/C8245/C8247/C8249 Program Memory 16K/32K-byte EPROM 16K/32K-byte mask ROM Operating Voltage (VDD) 1.8 V to 5.5 V 1.8 V to 5.5 V OTP Programming Mode VDD = 5 V, VPP (TEST) = 12.5 V Pin Configuration 80-QFP/80-TQFP 80-QFP/80-TQFP EPROM Programmability User Program 1 time Programmed at the factory 21-3 S3P8245/P8249 OTP S3C8248/C8245/P8245/C8247/C8249/P8249 OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of the S3P8245/P8249, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 21-3 below. Table 21-3. Operating Mode Selection Criteria VDD VPP (TEST) REG/MEM MEM Address(A15–A0) R/W 5V 5V 0 0000H 1 EPROM read 12.5 V 0 0000H 0 EPROM program 12.5 V 0 0000H 1 EPROM verify 12.5 V 1 0E3FH 0 EPROM read protection Mode NOTE: "0" means Low level; "1" means High level. Table 21-4. D.C Electrical Characteristics (TA = -40 °C to +85 °C, VDD = 1.8 V to 5.5 V) Parameter Operating voltage Symbol VDD Conditions Min Typ Max Unit f CPU = 10 MHz 2.7 – 5.5 V All input pins except VIH2, 3 1.8 – 5.5 0.8 VDD – VDD VLCD2 ≥ VDD Input high VIH1 Port 4,5 voltage VIH2 XIN, XTIN 0.8 VDD – VDD VIH3 All input pins except VIL2 VDD- 0.1 – VDD VIL1 XIN, XTIN – – 0.2 VDD VIL2 VDD = 5 V; IOH = -1 mA All output pins Output high voltage VOH VDD = 5 V; IOL = 2 mA All output pins Output low voltage VOL Input low voltage 21-4 0.1 VDD -1.0 – – – – 0.4 S3C8248/C8245/P8245/C8247/C8249/P8249 S3P8245/P8249 OTP Table 21-4. D.C. Electrical Characteristics (Continued) (TA = -40 °C to +85 °C, VDD = 1.8 V to 5.5 V) Parameter Symbol Input high leakage current ILIH1 VIN = VDD All input pins except ILIH2 ILIH2 VIN = VDD XIN, XTIN ILIL1 VIN = 0 V All input pins except ILIL2 ILIL2 VIN = 0 V XIN, XTIN, RESET Output high leakage current ILOH VOUT = VDD All I/O pins and Output pins – – 3 Output low leakage current ILOL VOUT = 0 V All I/O pins and Output pins – – -3 Oscillator feed back resistors Rosc1 VDD = 5.0 V TA = 25 °C XIN = VDD, XOUT = 0 V 800 1000 1200 Pull-up resistor RL1 VIN = 0 V; VDD = 5 V ±10 % 25 50 100 RL2 VIN = 0 V; VDD = 5 V ±10% TA=25 °C, RESET only 110 210 310 VLC0 TA = 25 °C (1/3 bias mode) 0.9 1.0 1.1 TA = 25 °C (1/2 bias mode) 1.4 1.5 1.7 Input low leakage current Conditions Min Typ Max – – 3 Unit 20 – – -3 -20 uA kΩ Port 0,1,2,3,4,5 TA = 25°C VLC0 out voltage (Booster run mode) VLC1 out voltage (Booster run mode) VLC1 TA = 25 °C 2VLC0 - 0.1 – 2VLC0 + 0.1 VLC2 out voltage (Booster run mode) VLC2 TA = 25 °C 3VLC0 - 0.1 – 3VLC0 + 0.1 COM output voltage deviation VDC VDD = VLC2 = 3 V (VLC-COMi) IO = ± 15 µA (1 = 0–3) – ± 60 ± 120 SEG output voltage deviation VDs VDD = VLC2 = 3 V (VLC-COMi) IO = ± 15 µA (1 = 0–3) – ± 60 ± 120 V mV 21-5 S3P8245/P8249 OTP S3C8248/C8245/P8245/C8247/C8249/P8249 Table 21-4. D.C. Electrical Characteristics (Concluded) (TA = -40 °C to + 85 °C, VDD = 1.8 V to 5.5 V) Parameter Supply current (1) Symbol IDD1 (2) IDD2 Conditions Min Typ Max Unit – 12 25 mA 3 MHz crystal oscillator 4 10 VDD = 3 V ± 10 % 10 MHz crystal oscillator 3 8 3 MHz crystal oscillator 1 5 Idle mode: VDD = 5 V ± 10 % 10 MHz crystal oscillator 3 10 3 MHz crystal oscillator 1.5 4 Idle mode: VDD = 3 V± 10 % 10 MHz crystal oscillator 1.2 3 3 MHz crystal oscillator 0.5 1.5 VDD = 5 V ± 10 % 10 MHz crystal oscillator IDD3 Sub operating: main-osc stop VDD = 3 V ± 10 % 32768 Hz crystal oscillator – 20 40 IDD4 Sub idle mode: main-osc stop VDD = 3 V ± 10 % 32768 Hz crystal oscillator – 7 14 IDD5 Main stop mode : sub-osc stop VDD = 5 V ± 10 % – 1 3 0.5 2 VDD = 3 V ± 10 % NOTES: 1. Supply current does not include current drawn through internal pull-up resistors or external output current loads. 2. IDD and IDD2 include a power consumption of subsystem oscillator. 3. IDD3 and IDD4 are the current when the main system clock oscillation stop and the subsystem clock is used. 4. IDD5 is the current when the main and subsystem clock oscillation stop. 21-6 uA S3C8248/C8245/P8245/C8247/C8249/P8249 S3P8245/P8249 OTP case of S3P8245, the characteristic of VOH and VOL is differ with the characteristic of S3P8249 like as bellow. Other characteristics are same each other. Table 21-5. D.C Electrical Characteristics of S3C8248/C8245 (TA = -40 °C to +85 °C, VDD = 1.8 V to 5.5 V) Parameter Symbol Output high voltage VOH1 Output low voltage Conditions Min Typ Max Unit VDD = 5 V; IOH = -1 mA All output pins except VOH2 VDD-1.0 – – V VOH2 VDD = 5 V; IOH = -6 mA Port 3.0 only in S3P8245 VDD-0.7 VOL1 VDD = 5 V; IOL = 2 Ma All output pins except VOL2 – 0.4 VOL2 VDD = 5 V; IOH = 12 mA Port 3.0 only in S3P8245 – 0.7 21-7 S3P8245/P8249 OTP S3C8248/C8245/P8245/C8247/C8249/P8249 fCPU B 10 MHz 8 MHZ A 3 MHZ 1 MHz 1 2 3 1.8 2.7 4 5 6 7 5.5 Supply Voltage (V) Minimum instruction clock = 1/4 x oscillator frequency Figure 21-2. Operating Voltage Range 21-8