SAMSUNG KS86C6308

KS86C6308/P6308
1
PRODUCT OVERVIEW
PRODUCT OVERVIEW
SAM88RCRI PRODUCT FAMILY
Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes.
A dual address/data bus architecture and a large number of bit- or nibble-configurable I/O ports provide a flexible
programming environment for applications with varied memory and I/O requirements. Timer/counters with
selectable operating modes are included to support real-time operations. Many SAM88RCRI microcontrollers
have an external interface that provides access to external memory and other peripheral devices.
KS86C6308/P6308 MICROCONTROLLER
The KS86C6308/P6308 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built
around the powerful SAM88RCRI CPU core.
Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register
space, the size of the internal register file was logically expanded. The KS86C6308 has 8 K bytes of program
memory on-chip.
Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core:
— Five configurable I/O ports (32 pins)
— 20 bit-programmable pins for external interrupts
— 8-bit timer/counter and 16-bit timwe/counter with three operating modes
— Full speed low speed USB function
The KS86C6308/P6308 is a versatile microcontroller that can be used in a wide range of full/low speed USB
support general purpose applications. It is especially suitable for use as a keyboard with hub controller and is
available in a 64-pin SDIP and a 64-pin QFP package.
OTP
The KS86C6308 microcontroller is also available in OTP (One Time Programmable) version, KS86P6308.
KS86P6308 microcontroller has an on-chip 8-Kbyte one-time-programmable EPROM instead of masked ROM.
The KS86P6308 is comparable to KS86C6308, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
KS86C6308/P6308 (Preliminary Spec)
FEATURES
CPU
Timer A
•
•
SAM88RCRI CPU core
Memory
•
8-KB Internal program memory(ROM)
•
256-byte internal register file
(160-byte:General Purpose)
Timer B
•
Instruction Set
•
41 instructions
•
IDLE and STOP instructions added for powerdown modes
Instruction Execution Time
•
One 8-bit basic timer for watchdog function and
programmable oscillation stabilization
programmable 8-bit timer internal generation
function interval, capture, PWM mode
match/capture overflow interrupt
Programmable 16-bit timer interval generation
function interval, capture, PWM mode
match/capture overflow interrupt
Universal Serial Bus with HUB
•
1 upstream port
•
4 downstream port and one embedded function
each port supports separated enable LED builtin 3.3 V voltage regulator
332ns at 12 MHz fOSC
Interrupts
USB/GPIO Function
•
32 interrupt sources with one vector, each
source has its pending bits
•
•
One level, one vector interrupt structure
Operation Temperature Range
Oscillation Frequency
•
Upstream port
- 40 °C to + 85 °C
•
12 MHz crystal/ceramic oscillator
Operation Voltage Range
•
External clock source
•
4.0 V to 5.5 V
General I/O
Package Types
•
•
64-pin SDIP
•
64-pin QFP
1-2
Bit programmable five I/O ports (30 pins total)
KS86C6308/P6308 (Preliminary Spec)
PRODUCT OVERVIEW
BLOCK DIAGRAM
USB Transceiver
&
Voltage Regulator
LPF
DP0/GPIO, DM0/GPIO
DP1, DM1
DP2, DM2
DP3, DM3
DP4, DM4
3.3 VOUT
12 MHz
XI
OSC
48 MHz
PLL
USB
Module
XO
12 MHz
OCDET1
OCDET2
OCDET3
OCDET4
SAM88RCRI
CORE
USB
Device
Control
LVD
VDD
8
Port
P0.0/INT2 - P0.7/INT2
160 Byte
RAM
B
i
t
B
U
S
Port
P1.0 - P1.7
Port
P2.0/INT0 - P2.7/INT0
Port
P3.3/TACLK/CLO
P3.2/TBCLK/USB_CLK
P3.1/TBCAP/TAOUT
P3.1/TACAP/TBOUT
TEST
RESET
TMOD
LEDON0
LEDON1
LEDON2
LEDON3
LEDON4
GANGED
8K
ROM
VSS
VSS1
PWREN1
PWREN2
PWREN3
PWREN4
Timer A
(8 Bit)
Timer B
(16 Bit)
Basic
Timer
Port
P4.0/INT1
P4.1/INT1
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
KS86C6308/P6308 (Preliminary Spec)
PIN ASSIGNMENTS
RESET/RESET
TMODE
DP0/GPIO
DM0/GPIO
DP1
DM1
DP2
DM2
DP3
DM3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
KS86C6308/P6308
LEDON4
P1.4
P1.5
P1.6
P1.7
P4.0/INT1
P4.1/INT1
P2.0/INT0
P2.1/INT0
P2.2/INT0
P2.3/INT0
P2.4/INT0
P2.5/INT0
SDAT /P2.6/INT0
SCLK /P2.7/INT0
VDD/VDD
VSS/VSS
XO /XO
XI/XI
TEST /TEST
LPF
VSS/VSSA
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
LEDON3
LEDPN2
LEDON1
LEDON0
OCDET4
PWREN4
P1.3
P1.2
P1.1
P1.0
P0.7/INT2
P0.6/INT2
P0.5/INT2
P0.4/INT2
P0.3/INT2
P0.2/INT2
P0.1/INT2
P0.0/INT2
OCDET3
PWREN3
P3.3/TACLK/CLO
P3.2/TBCLK/USB_CLK
P3.1/TBCAP/TAOUT
P3.0/TACAP/TBOUT
VSS1/VSS
OCDET2
PWREN2
ECDET1
PWREN1
3.3VOUT
DM4
DP4
Figure 1-2. Pin Assignment Diagram (64-Pin SDIP Package)
1-4
64
63
62
61
60
59
58
57
56
55
54
53
52
OCDET4
PWREN4
PRODUCT OVERVIEW
P41/INT1
P40/INT1
P17
P16
P15
P14
LEDON4
LEDON3
LEDON2
LEDON1
LEDON0
KS86C6308/P6308 (Preliminary Spec)
P2.0/INT0
P2.1/INT0
P2.2/INT0
P2.3/INT0
P2.4/INT0
P2.5/INT0
SDAT /P2.6/INT0
SCLK /P2.7/INT0
VDD/VDD
VSS/VSS
XO /XO
XI/XI
TEST /TEST
LPF
VSS/VSSA
RESET/RESET
KS86C6308
(KS86P6308)
51
50
43
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P1.3
P1.2
P1.1
P1.0
P0.7/INT2
P0.6/INT2
P0.5/INT2
P0.4/INT2
P0.3/INT2
P0.2/INT2
P0.1/INT2
P0.0/INT2
OCDET3
PWREN3
P3.3/TACLK/CLO
P3.2/TBCLK/USB_CLK
P3.1/TBCAP/TAOUT
P3.0/TACAP/TBOUT
GANGED
PWREN1
OCDET1
PWREN2
OCDET2
DP1
DM1
DP2
DM2
DP3
DM3
DP4
DM4
3.3VOUT
20
21
22
23
24
25
26
27
28
29
30
31
32
TMODE
DP0/GPIO
DM0/GPIO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Figure 1-3. Pin Assignment Diagram (64-Pin QFP Package)
1-5
PRODUCT OVERVIEW
KS86C6308/P6308 (Preliminary Spec)
PIN DESCRIPTIONS
Table 1-1. KS86C6308/P6308 Pin Descriptions
Pin
Names
I/O
Pin
Description
Pin
Type
Share
Pins
P0.0-P0.7
I/O
B
INT2
P1.0-P1.7
I/O
B
–
P2.0-P2.7
I/O
B
INT0
P3.0-P3.3
I/O
Bit-programmable I/O port for Schmitt trigger input or
open-drain output. Port 0 can be individually configured
as external interrupt inputs. Pull-up resistors are
assignable by software.
Bit-programmable I/O port for Schmitt trigger input or
open-drain output. Pull-up resistors are assignable by
software.
Bit-programmable I/O port for Schmitt trigger input or
open-drain output. Port 2 can also be individually
configured as external interrupt inputs. Pull-up resistors
are assignable by software.
Bit-programmable I/O port for Schmitt trigger input, opendrain output or push-pull output. Port 3 are designed for
to drive LED directly. P3.3 can be used to system clock
output(CLO) pin. P3.2 PLL clock out for PLL Block.
P4.0-P4.1
I/O
3.3 VOUT
–
XIN
XOUT
1-6
C
P3.3/TACLK/CLO
P3.2/TBCLK/
USB_CLK
P3.1/TBCAP/TAOUT
P3.0/TACAP/TBOUT
Bit-programmable I/O port for Schmitt trigger input or
open-drain output or push-pull output. Port4 can also be
individually configured as external interrupt inputs. In
output mode, pull-up resistors are assignable by
software. But in input mode, pull-up resistors are fixed.
3.3 V output from internal voltage regulator
D
INT1
–
–
–
System clock input and output pin (crystal/ceramic
oscillator, or external clock source)
–
–
INT0
INT1
INT2
RESET
LPF
TEST
I
External interrupt for bit-programmable port0, port2 and
port4 pins when set to input mode.
–
I
I
I
RESET signal input pin with LVD
Low Pass Filter Pin for PLL
Test signal input pin (for factory use only; must be
connected to VSS)
A
–
–
P2.0-P2.7
P4.0/P4.1
P0.0/P0.7
–
–
–
TMODE
I
Test signal input pin (for factory use only, must be
connected to VSS)
–
–
VDD
–
Power input pin
–
–
VSS
VSS1
–
VSS1 is a ground power for CPU core.
VSS2 is a ground power for I/O and OSC block.
–
–
KS86C6308/P6308 (Preliminary Spec)
PRODUCT OVERVIEW
Table 1-1. KS86C6308/P6308 Pin Descriptions (Continued)
Pin
Names
I/O
DP1, DM1
DP2, DM2
DP3, DM3
DP4, DM4
DP0/GPIO
DM0/GPIO
LEDON0
I/O
I/O
LEDON1-4
O
OCDET1-4
I
PWREN1-4
O
GANGED
I
O
Pin
Description
Pin
Type
Share
Pins
These pins are an USB Downstream pins.
K
–
These pins are an USB Upstream pin, programmable
port for USB interface or General purpose I/O interface.
Root port LED enable. N-channel open-drain output.
= 0 Turn LED ON. HUB not Suspend
= 1 Turn LED OFF. Reset, Suspend, Transfer in
progress
Four downstream port LED enable. N-channel opendrain output.
= 0 Turn LED ON. Port Enable and HUB not Suspend
= 1 Turn LED OFF. Reset, Suspend, Transfer in
progress
Four downstream power sense
= 0 Over Current Detected
= 1 Power Okay
Power on/off control signals. PWREN1 - PWREN4 are
active low, N-CH open-drain outputs.
In GANGED mode, all output are swithed together.
Gang or Individual Power Control of downstream ports
= 0 Individual
= 1 Gang
–
–
G
–
G
–
F
–
G
–
F
–
1-7
PRODUCT OVERVIEW
KS86C6308/P6308 (Preliminary Spec)
PIN CIRCUIT DIAGRAMS
VDD
VDD
Output Data
Open Drain
Pull-up
Resistor
Output
DIsable
Noise
Filter
Input Data
Figure 1-4. Pin Circuit Type A (RESET)
D0
MUX D1
VSS
Figure 1-6. Pin Circuit Type C (Port 3)
VDD
VDD
Pull-up
Resistor
Pull-up
Resistor
Pull-up Enable
VDD
Pull-up Enable
Output Data
Output Disable
Open Data
Input Data
Open Drain
D0
MUX D1
VSS
Output
DIsable
Input Data
D0
MUX D1
VSS
Figure 1-5. Pin Circuit Type B (Port 0, 1, 2)
Figure 1-7. Pin Circuit Type D (Port 4)
1-8
KS86C6308/P6308 (Preliminary Spec)
PRODUCT OVERVIEW
VDD
Pull-up
Resistor
Figure 1-8. Pin Circuit Type F
3.0 V < V <3.6 V
Only on
Upstream Ports
15 KΩ ± 5 %
or
Equivalent
DPX
DMX
RXD
RXDP
RXDM
TXDP
OEN
Speed (Only on Downstream Ports)
TXDM
Only on
Downstream
Ports
15 KΩ ± 5 %
Figure 1-9. Pin Circuit Type K
1-9
PRODUCT OVERVIEW
KS86C6308/P6308 (Preliminary Spec)
Output
Data
Figure 1-10. Pin Circuit Type G
1-10
KS86C6308/P6308 (Preliminary Spec)
PRODUCT OVERVIEW
APPLICATION CITCUIT
KS86C6308 (P6308)
VDD
XI
12 MHz
XO
GANGED
LPF
Downstream
Ports
VDD
DD+
VSS
Upstream Port
VDD
DD+
VSS
Keyboard
Matrix
VDD
DM0
DP0
VSS
P2.0-P2.7
P0.0-P0.7
P1.0-P1.7
DM1
DP1
DM2
DP2
VDD
DD+
VSS
DM3
DP3
VDD
DD+
VSS
DM4
DP4
VDD
DD+
VSS
P3.2
P3.1
P3.0
PWREN1
PWREN2
LEDON0
PWREN3
PWREN4
LEDON1
OCDET1
LEDON2
LEDON3
Power Switch
EN
IN
OCDET2
OCDET3
OCDET4
OC OUT
LEDON4
NOTES:
1. We recommand Power Switch, MIC2525 (by MICREL Semiconductor).
2. R1: 1.5 KΩ R2: 15 KΩ
3. For proper operation of the PLL, an external RC filter consisting of series
RC network resistor and capacitor must be connected from the LPF pin to V SS.
4. Port3 can use LED direct drive.
5. Upstream D+, D- can use GPIO interface (see GPIOCONINT)
Figure 1-11. Bus-Powered, Gang Port (64-SDIP, 64-QFP)
1-11
PRODUCT OVERVIEW
KS86C6308/P6308 (Preliminary Spec)
KS86C6308 (P6308)
XI
12 MHz
XO
GANGED
LPF
VDD
DD+
VSS
Downstream
Ports
VDD
DD+
VSS
VSS
Upstream Port
Keyboard
Matrix
VDD
DM0
DP0
VSS
P2.0-P2.7
P0.0-P0.7
P1.0-P1.7
DM1
DP1
DM2
DP2
VDD
DD+
VSS
DM3
DP3
VDD
DD+
VSS
DM4
DP4
VDD
DD+
VSS
P3.2
P3.1
PWREN1
P3.0
LEDON0
LEDON1
LEDON2
LEDON3
LEDON4
OCDET1
PWREN2
OCDET2
PWREN3
OCDET3
PWREN4
OCDET4
EN
IN
OC OUT
EN
IN
OC OUT
EN
IN
OC OUT
EN
IN
OC OUT
Power Switching
NOTES:
1. We recommand Power Switch, MIC2525 (by MICREL Semiconductor).
2. For proper operation of the PLL, an external RC filter consisting of series
RC network resistor and capacitor must be connected from the LPF pin to V SS.
3. Port3 can use LED direct drive.
4. Upstream D+, D- can use GPIO interface (see GPIOCONINT)
Figure 1-12. Bus-Powered, Individual Port (64-SDIP, 64-QFP)
1-12
KS86C6308/P6408 (Preliminary Spec)
12
ELECTRICAL DATA
ELECTRICAL DATA
OVERVIEW
In this section, the following KS86C6308/P6308 electrical characteristics are presented in tables and graphs:
— Absolute maximum ratings
— D.C. electrical characteristics
— Input/Output capacitance
— A.C. electrical characteristics
— Input timing for external interrupt (Ports 0, 2 and 4) DP0/GPIO, DM0/GPIO : GPIO Mode Only
— Input timing for RESET
— Oscillator characteristics
— Oscillation stabilization time
— Clock timing measurement points at XIN
— Data retention supply voltage in Stop mode
— Stop mode release timing when initiated by a reset
— Stop mode release timing when initiated by an external interrupt
— Characteristic curves
12-1
ELECTRICAL DATA
KS86C6308/P6408 (Preliminary Spec)
Table 12-1. Absolute Maximum Ratings
(TA = 25°C)
Parameter
Symbol
Conditions
Rating
Unit
Supply Voltage
VDD
–
– 0.3 to + 6.5
V
Input Voltage
VIN
All input ports
– 0.3 to VDD + 0.3
V
Output Voltage
VO
All output ports
– 0.3 to VDD + 0.3
V
Output Current High
IOH
One I/O pin active
– 18
mA
All I/O pins active
– 60
One I/O pin active
+ 30
Total pin current for ports 0, 1, 2, 4
+ 100
Total pin current for port 3
+ 100
Output Current Low
IOL
mA
Operating
Temperature
TA
–
– 40 to + 85
°C
Storage
Temperature
TSTG
–
– 65 to + 150
°C
12-2
KS86C6308/P6408 (Preliminary Spec)
ELECTRICAL DATA
Table 12-2. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 4.0 V to 5.5 V)
Parameter
Symbol
Conditions
Operating Voltage
VDD
fOSC = 12 MHz
Input High Voltage
VIH1
All input except VIH2
VIH2
XIN
VIL1
All input pins except VIL2
VIL2
XIN
Output High
Voltage
VOH
IOH = – 200 µA; All output
ports except ports 0, 1, 2, DP’s,
DM’s
Output Low
Voltage
VOL
Input Low Voltage
Input High
Leakage Current
Input Low
Leakage Current
Min
Typ
Max
Unit
4.0
–
5.5
V
0.8 VDD
–
VDD
V
VDD – 0.5
–
VDD
–
0.2 VDD
V
0.4
VDD – 1.0
–
–
V
IOL = 1 mA
All output ports except DP’s,
DM’s
–
–
0.4
V
ILIH1 (4)
VIN = VDD
All inputs excepts ILIH2, DP’s,
DM’s
–
–
3
µA
ILIH2 (4)
VIN = VDD
XIN, XOUT, RESET
–
–
20
µA
ILIL1 (4)
VIN = 0 V
All inputs excepts ILIL2, DP’s,
DM’s
–
–
–3
µA
ILIL2 (4)
VIN = 0 V
XIN, XOUT, RESET
–
–
– 20
µA
12-3
ELECTRICAL DATA
KS86C6308/P6408 (Preliminary Spec)
Table 12-2. D.C. Electrical Characteristics (continued)
(TA = – 40 °C to + 85 °C, VDD = 4.0 V to 5.5 V)
Parameter
Symbol
Output High
Leakage Current
ILOH
(1)
Output Low
Leakage Current
ILOL (1)
Pull-up Resistors
RL
Supply Current
Conditions
Min
Typ
Max
Unit
VOUT = VDD
All I/O pins and output pins
except DP’s and DM’s
–
–
3
µA
VOUT = 0 V
All I/O pins and output pins
except DP’s and DM’s
–
–
–3
µA
VIN = 0 V
Ports 0, 1, 2, 4, Reset
25
50
100
kΩ
30
mA
IDD1
Normal operation mode :
12 MHz Crystal Oscillator
IDD2
Idle mode;
12 MHz Crystal Oscillator
15
IDD3
Stop mode: Oscillator stop
500
–
µA
NOTES:
1. Except XIN and XOUT.
2.
3.
3.
Supply current does not include through internal pull-up resistors or external output current loads.
Figure 11-3 Transition Rise Timer (tR), Fall Timer (tF) parameter is guaranteed, but not tested.
When USB Mode Only in 4.20 V to 5.25 V, DP’s and DP’s satisfy the USB Specification version 1.0.
Table 12-3. Input/Output Capacitance
(TA = – 40 °C to + 85 °C, VDD = 0 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input
Capacitance
CIN
f = 1 MHz; Unmeasured pins
are connected to VSS
–
–
10
pF
Output
Capacitance
COUT
Min
Typ
Max
Unit
P0, P2 and P4
–
200
–
ns
RESET
–
1000
–
I/O Capacitance
CIO
Table 12-4. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 4.0 V to 5.5 V)
Parameter
Symbol
Interrupt Input
High, Low Width
tINTH, tINTL
RESET Input Low
tRSL
Width
12-4
Conditions
KS86C6308/P6408 (Preliminary Spec)
ELECTRICAL DATA
tINTL
tINTH
0.8 VDD
0.2 VDD
Figure 12-1. Input Timing Measurement Points (Ports 0, 2, and 4)
tRSL
RESET
0.5 V DD
Figure 12-2. Input Timing for RESET
tR
tF
0.5VDD
DP
DM
90%
90%
10%
10%
Figure 12-3. USB Data Signal Timing
12-5
ELECTRICAL DATA
KS86C6308/P6408 (Preliminary Spec)
Table 12-5. DPx, DMx Driver Characteristics, Full Speed Operation
Symbol
Parameter
Condition
Min
Max
Unit
tR
Rise Time
CL = 50pF
4
20
ns
tF
Fall Time
CL = 50pF
4
20
ns
tRFM
tR/tF Matching
–
90
11
%
Table 12-6. DPx, DMx Driver Characteristics, Low Speed Operation
12-6
Symbol
Parameter
Condition
Min
Max
Unit
tR
Rise Time
CL = 200-600pF
75
300
ns
tF
Fall Time
CL = 200-600pF
75
300
ns
tRFM
tR/tF Matching
–
80
125
%
KS86C6308/P6408 (Preliminary Spec)
ELECTRICAL DATA
RS
TXD+
CL
RS
TXD-
CL
CL = 50 pF
Figure 12-4. Full-Speed Load
TXD+
RS
CL
TXD-
3.6 V
RS
CL
CL = 200 pF to 600 pF
Figure 12-5. Low-Speed Load
12-7
ELECTRICAL DATA
KS86C6308/P6408 (Preliminary Spec)
Table 12-7. Oscillator Characteristics
(TA = – 40°C + 85°C)
Oscillator
Circuit
Main crystal Main
ceramic (fOSC)
Condition
Min
Typ
Max
Unit
VDD = 4.0V to 5.5V
–
12
–
MHz
VDD = 4.0V to 5.5V
–
12
–
Min
Typ
Max
Unit
–
–
20
ms
–
–
10
25
–
500
XIN
C1
XOUT
C2
External clock
XIN
XOUT
Table 12-8. Oscillation Stabilization Time
(TA = – 40°C + 85°C, VDD = 4.0 V to 5.5 V)
Oscillator
Symbol
Crystal
–
Ceramic
–
External
–
Condition
VDD = 4.0V to 5.5V
XIN input high & low level
width
ns
NOTE: The oscillator stabilization wait time, tWAIT, is determined by the setting in the basic timer control register, BTCON.
Table 12-9. Data Retention Supply Voltage in Stop Mode
(TA = – 40°C to + 85°C)
Parameter
Symbol
Conditions
Data Retention
Supply Voltage
VDDDR
Stop mode
Data Retention
Supply Current
IDDDR
Stop mode; VDDDR = 2.0 V
12-8
Min
Typ
Max
Unit
2.0
–
6
V
–
–
500
uA
KS86C6308/P6408 (Preliminary Spec)
13
MECHANICAL DATA
MECHANICAL DATA
OVERVIEW
The KS86C6308/P6308 is available in a 64-pin SDIP package (Samsung: 64-SDIP-750) and a 64-pin QFP
package (64-QFP-1420F). Package dimensions are shown in Figures 13-1 and 13-2.
#33
0.2
5
64-SDIP-750
+0
- 0 .10
.05
0-15
19.05
17.00 ± 0.20
#64
(1.34)
NOTE :
0.45
± 0.10
1.00
± 0.10
1.778
5.08 MAX
57.80 ± 0.20
3.30 ± 0.30
58.20 MAX
4.10 ± 0.20
#32
0.51 MIN
#1
Dimensions are in millimeters.
Figure 13-1. 64-Pin SDIP Package Mechanical Data (64-SDIP-750 )
13-1
MECHANICAL DATA
KS86C6308/P6408 (Preliminary Spec)
23.90 ± 0.30
0-8
20.00 ± 0.20
+ 0.10
14.00 ± 0.20
0.10 MAX
64-QFP-1420F
0.80 ± 0.20
17.90 ± 0.30
0.15 - 0.05
#64
#1
1.00
+ 0.10
0.40 - 0.05
0.05 MIN
0.15 MAX
(1.00)
2.65 ± 0.10
3.00 MAX
0.80
± 0.20
NOTE : Dimensions are in millimeters.
Figure 13-2. 64-Pin QFP Package Mechanical Data (64-QFP-1420F )
13-2
KS86C6308/P6308 (Preliminary Spec)
14
KS86P6308 OTP
KS86P6308 OTP
OVERVIEW
The KS86P6308 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
KS86C6308 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by
serial data format.
The KS86P6308 is fully compatible with the KS86C6308, both in function and in pin configuration. Because of its
simple programming requirements, the KS86P6308 is ideal for use as an evaluation chip for the KS86C6308.
14-1
KS86P6308 OTP
KS86C6308/P6308 (Preliminary Spec)
RESET/RESET
TMODE
DP0/GPIO
DM0/GPIO
DP1
DM1
DP2
DM2
DP3
DM3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
KS86P6308
LEDON4
P1.4
P1.5
P1.6
P1.7
P4.0/INT1
P4.1/INT1
P2.0/INT0
P2.1/INT0
P2.2/INT0
P2.3/INT0
P2.4/INT0
P2.5/INT0
SDAT /P2.6/INT0
SCLK /P2.7/INT0
VDD/VDD
VSS/VSS
XO /XO
XI/XI
TEST /TEST
LPF
VSS/VSSA
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
LEDON3
LEDPN2
LEDON1
LEDON0
OCDET4
PWREN4
P1.3
P1.2
P1.1
P1.0
P0.7/INT2
P0.6/INT2
P0.5/INT2
P0.4/INT2
P0.3/INT2
P0.2/INT2
P0.1/INT2
P0.0/INT2
OCDET3
PWREN3
P3.3/TACLK/CLO
P3.2/TBCLK/USB_CLK
P3.1/TBCAP/TAOUT
P3.0/TACAP/TBOUT
GANGED
OCDET2
PWREN2
ECDET1
PWREN1
3.3VOUT
DM4
DP4
Figure 14-1. Pin Assignment Diagram (64-Pin SDIP Package)
14-2
64
63
62
61
60
59
58
57
56
55
54
53
52
OCDET4
PWREN4
KS86P6308 OTP
P41/INT1
P40/INT1
P17
P16
P15
P14
LEDON4
LEDON3
LEDON2
LEDON1
LEDON0
KS86C6308/P6308 (Preliminary Spec)
P2.0/INT0
P2.1/INT0
P2.2/INT0
P2.3/INT0
P2.4/INT0
P2.5/INT0
SDAT /P2.6/INT0
SCLK /P2.7/INT0
VDD/VDD
VSS/VSS
XO /XO
XI/XI
TEST /TEST
LPF
VSS/VSSA
RESET/RESET
KS86P6308
51
50
43
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P1.3
P1.2
P1.1
P1.0
P0.7/INT2
P0.6/INT2
P0.5/INT2
P0.4/INT2
P0.3/INT2
P0.2/INT2
P0.1/INT2
P0.0/INT2
OCDET3
PWREN3
P3.3/TACLK/CLO
P3.2/TBCLK/USB_CLK
P3.1/TBCAP/TAOUT
P3.0/TACAP/TBOUT
GANGED
PWREN1
OCDET1
PWREN2
OCDET2
DP1
DM1
DP2
DM2
DP3
DM3
DP4
DM4
3.3VOUT
20
21
22
23
24
25
26
27
28
29
30
31
32
TMODE
DP0/GPIO
DM0/GPIO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Figure 14-2. Pin Assignment Diagram (64-Pin QFP Package)
14-3
KS86P6308 OTP
KS86C6308/P6308 (Preliminary Spec)
Table 14-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
P2.6
SDAT
9
P2.7
SCLK
TEST
I/O
(3)
Function
I/O
Serial Data Pin (Output when reading, Input
when writing) Input and Push-pull Output Port
can be assigned
10 (4)
I/O
Serial Clock Pin (Input Only Pin)
TEST
15 (9)
I
Chip Initialization and EPROM Cell Writing
Power Supply Pin (Indicates OTP Mode
Entering) When writing 12.5 V is applied and
when reading.
RESET
RESET
18 (12)
I
0 V: OTP write and test mode
5 V: Operating mode
VDD / VSS
VDD / VSS
11(5)/12(6)
–
Logic Power Supply Pin.
NOTE: ( ) means 64 QFP package.
Table 14-2. Comparison of KS86P6308 and KS86C308 Features
Characteristic
KS86P6308
KS86C6308
Program Memory
8-Kbyte EPROM
8-Kbyte mask ROM
Operating Voltage (VDD)
4.0 V to 5.25 V
4.0 V to 5.25 V
OTP Programming Mode
VDD = 5 V, VPP (RESET) = 12.5 V
Pin Configuration
64 SDIP/64 QFP
64 SDIP/64 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (RESET) pin of the KS86P6308, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 14-3 below.
Table 14-3. Operating Mode Selection Criteria
VDD
5V
REG/
MEM
ADDRESS
(RESET)
5V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
VPP
NOTE: "0" means Low level; "1" means High level.
14-4
R/W
MODE
(A15-A0)
KS86C6308/P6308 (Preliminary Spec)
KS86P6308 OTP
START
Address= First Location
VDD =5V, V PP=12.5V
x=0
Program One 1ms Pulse
Increment X
YES
x = 10
NO
FAIL
Verify Byte
Verify 1 Byte
Last Address
FAIL
NO
Increment Address
VDD = V PP= 5 V
FAIL
Compare All Byte
PASS
Device Failed
Device Passed
Figure 14-3. OTP Programming Algorithm
14-5
KS86P6308 OTP
KS86C6308/P6308 (Preliminary Spec)
Table 14-4. D.C. Electrical Characteristics
(TA = – 40_C to + 85_C, VDD = 5.25 V)
Parameter
Supply Current
Symbol
Conditions
Min
Typ
Max
Unit
–
–
30
mA
IDD1
Normal mode;
12 MHz crystal oscillator
IDD2
Idle mode;
12 MHz CPU clock
–
15
IDD3
Stop mode
–
500
(note)
µA
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
14-6