S3C72K8/P72K8 1 PRODUCT OVERVIEW PRODUCT OVERVIEW OVERVIEW The S3C72K8 singl-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM48 (Samsung Arrageable Microcontrollers). With a two-channel comparator, up-to320-dot LCD direct drive capability, 8-bit timer/counter, watchdog timer and serial I/O, the S3C72K8 offers an excellent design solution for a wide variety of applications which require LCD functions. Up to 27 pins of the 80-pin QFP package can be dedicated to I/O. Seven vectored interrupts provide fast response to internal and external events. In addition, the S3C72K8's advanced CMOS technology provides for low power consumption and a wide operating voltage range. OTP The S3C72K8 microcontroller is also available is OTP (one time programmable) version, S3P72K8. S3P72K8 microcontroller has an one-chop 8 Kbyte one time programmable EPROM instead of masked ROM. The S3P72K8 is comparable to S3C72K8, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C72K8/P72K8 FEATURES Memory Watch Timer — 8 K × 8-bit RAM — Timer interval generation: 0.5 s, 3.9 ms at 32,768 Hz — 1,024 × 4-bit ROM — Four frequency outputs to BUZ pin 27 I/O Pins — Clock source generation for LCD — Input only: 4 pins — I/O: 15 pins — Output: maximum 8 pins for 1-bit level output (sharing with segment driver outputs) Interrupts — Three internal vectored interrupts: INTB, INTT0, INTS Comparator — Four external vectored interrupts: INT0, INT1, INT4, INTK — Two channel mode: internal reference (4-bit resolution) — Two quasi-interrupts: INT2, INTW — One channel mode: external reference Memory-Mapped I/O Structure — Data memory bank 15 LCD Controller/Driver — 40 segments and 8 common terminals — 3, 4 and 8 common selectable — Internal resistor circuit for LCD bias — All dot can be switched on/off 8-Bit Basic Timer — 4 interval timer functions — Watchdog timer Two Power-Down Modes — Idle mode (only CPU clock stops) — Stop mode (main system oscillation stops) — Subsystem clock stop mode Oscillation Sources — Crystal, ceramic, or External RC for system clock — Main system clock frequency: 0.4 MHz–6 MHz — Subsystem clock frequency: 32,768 kHz 8-Bit Timer/Counter — CPU clock divider circuit (by 4, 8, or 64) — Programmable 8-bit timer — External event counter — Arbitrary clock frequency output — External clock signal divider — Serial I/O interface clock generator 8-Bit Serial I/O Interface Instruction Execution Times — 0.67 us at 6 MHz (minimum) — 0.95 µs at 4.19 MHz (minimum) — 122 µs at 32,768 kHz (minimum) Operating Temperature — 8-bit transmit/receive mode — – 40 °C to 85 °C — 8-bit receive only mode Operating Voltage Range — LSB-first or MSB-first transmission selectable — 2.0 V to 5.5 V — Internal or external clock source Bit Sequential Carrier — Support 16-bit serial data transfer in arbitrary format 1-2 Package Type — 80-pin QFP S3C72K8/P72K8 PRODUCT OVERVIEW BLOCK DIAGRAM RESET Watchdog Timer Basic Timer LCD Driver/ Controller Interrupt Control Block Watch Timer Instruction Decoder I/O Port 0 Comparator P1.0/INT0/CIN0 P1.1/INT1/CIN1 P1.2/INT2 P1.3/INT4 Clock Internal Interrupts SIO P0.0/SCK/K0 P0.1/SO/K1 P0.2/SI/K2 P0.3/BUZ/K3 XIN XOUT XTIN XTOUT Arithmetic and Logic Unit Stack Pointer VLC1-VLC5 COM0-COM7 SEG0-SEG31 P5.0/SEG32P5.7/SEG39 I/O Port 2 P2.0-P2.3 I/O Port 3 P3.0 P3.1 P3.2/LCDSY P3.3/CLDCK I/O Port 4 P4.0/CLO P4.1/TCL0 P4.2/TCLO0 Program Counter Program Status Word Flags 8-Bit Timer/ Counter Input Port 1 1024 x 4-Bit Data Memory 8 Kbyte Program Memory Figure 1-1. S3C72K8 Simplified Block Diagram 1-3 PRODUCT OVERVIEW S3C72K8/P72K8 PIN ASSIGNMENTS SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32/P5.0 SEG33/P5.1 SEG34/P5.2 SEG35/P5.3 SEG36/P5.4 SEG37/P5.5 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 P5.6/SEG38 P5.7/SEG39 VLC1 VLC2 VLC3 VLC4 VLC5 P0.0/SCK/K0 P0.1/SO/K1 P0.2/SI/K2 P0.3/BUZ/K3 VDD VSS XOUT XIN TEST XTIN XTOUT RESET P1.0/INT0/CIN0 P1.1/INT1/CIN1 P1.2/INT2 P1.3/INT4 P2.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 S3C72K8 (80-QFP-1420C) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 COM5 COM4 COM3 COM2 COM1 COM0 TCLO0/P4.2 TCL0/P4.1 CLO/P4.0 LCDCK/P3.3 LCDSY/P3.2 P3.1 P3.0 P2.3 P2.2 P2.1 Figure 1-2. S3C72K8 80-QFP Pin Assignment 1-4 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM7 COM6 S3C72K8/P72K8 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. S3C72K8 Pin Descriptions Pin Name Pin Type Description Circuit Type Pin Number Share Pin P0.0 P0.1 P0.2 P0.3 I/O 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. Individual pins are software configurable as input or output. Individual pins are software configurable as opendrain or push-pull output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. E–2 8 9 10 11 K0/SCK K1/SO K2/SI K3/BUZ P1.0 P1.1 P1.2 P1.3 I 4-bit input port. 1-bit or 4-bit read and test are possible. The 1-bit unit pull-up resistors are assigned to input pins by software. An interrupt is generated by digital input at P1.0, P1.1. F–4 F–4 A–3 A–3 20 21 22 23 INT0/CIN0 INT1/CIN1 INT2 INT4 P2.0–P2.3 I/O Same as port 0 except that 8-bit read/write and test is possible. E–2 24–27 – 28 29 30 31 – – LCDSY LCDCK P3.0 P3.1 P3.2 P3.3 P4.0 P4.1 P4.2 I/O Same as port 0 except that port 4 is 3-bit I/O port. E–2 32 33 34 CLO TCL0 TCLO0 P5.0–P5.7 O Output port for 1-bit data H–11 75– 80,1,2 SEG32– SEG39 SCK I/O Serial I/O interface clock signal E–2 8 P0.0/K0 SO I/O Serial data output E–2 9 P0.1/K1 SI I/O Serial data input E–2 10 P0.2/K2 BUZ I/O 2 KHz, 4 KHz, 8 KHz or 16 KHz frequency output at the watch timer clock frequency of 32.768 kHz. E–2 11 P0.3/K3 K0–K3 I/O External interrupt. The triggering edge is selectable. E–2 8–11 P0.0–P0.3 INT0 INT1 I External interrupts. The triggering edge for INT0 and INT1 is selectable. F–4 20 21 P1.0/CIN0 P1.1/CIN1 INT2 I Quasi-interrupt with detection of rising or falling edges A–3 22 P1.2 INT4 I External interrupts with detection of rising and falling edges A–3 23 P1.3 1-5 PRODUCT OVERVIEW S3C72K8/P72K8 Table 1-1. S3C72K8 Pin Descriptions (Continued) Pin Name Pin Type CIN0 CIN1 I LCDSY Description Circuit Type Pin Number Share Pin 2-channel comparator input. CIN0: comparator input or external reference input CIN1: comparator input only. F–4 20 21 P1.0/INT0 P1.1/INT1 I/O LCD synchronization clock output for display expansion E–2 30 P3.2 LCDCK I/O LCD clock output for display expansion E–2 31 P3.3 CLO I/O Clock output E–2 32 P4.0 TCL0 I/O External clock input for timer/counter 0 E–2 33 P4.1 TCLO0 I/O Timer/counter 0 clock output E–2 34 P4.2 SEG32– SEG39 O LCD segment signal output H–11 75– 80,1,2 P5.0–P5.7 SEG0– SEG31 O LCD segment signal output H–6 43–74 – COM0– COM7 O LCD common signal output H–6 35–42 – VLC1–VLC5 – LCD power supply. Voltage dividing resistors are assignable by mask option. – 3–7 – XIN, XOUT – Crystal, ceramic or RC oscillator pins for system clock. – 15, 14 – XTIN, XTOUT – Crystal oscillator pins for subsystem clock. – 17, 18 – VDD – Main power supply – 12 – VSS – Ground – 13 – RESET I Chip reset signal input B 19 – TEST I Chip test signal input (must be connected to VSS) – 16 – NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode 1-6 S3C72K8/P72K8 PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS VDD VDD Pull-Up Resistor P-Channel In In N-Channel Schmitt Trigger Figure 1-5. Pin Circuit Type B Figure 1-3. Pin Circuit Type A VDD VDD Pull-Up Resistor Pull-Up Resistor Enable P-Channel Data Out Output Disable In P-Channel N-Channel Schmitt Trigger Figure 1-4. Pin Circuit Type A-3 Figure 1-6. Pin Circuit Type 7 1-7 PRODUCT OVERVIEW S3C72K8/P72K8 VDD PNE Pull-up Resistor VDD Resistor Enable P-CH I/O Data N-CH Output Disable Schmitt Trigger Figure 1-7. Pin Circuit Type E-2 VDD Pull-up Resistor Resistor Enable Schmitt Trigger Digital In EXT-REF (P1.0 only) Analog In + Comparator INT-REF Digital or Analog Selectable by Software (P1MOD) Figure 1-8. Pin Circuit Type F-4 1-8 I/O S3C72K8/P72K8 PRODUCT OVERVIEW VDD VLC1 VLC2 SEG/COM Data Out Output Disable VLC3 VLC4 VLC5 Figure 1-9. Pin Circuit Type H-5 1-9 PRODUCT OVERVIEW S3C72K8/P72K8 VDD VLC1 VLC2 Out SEG/COM VLC3 VLC4 VLC5 Figure 1-10. Pin Circuit Type H-6 VDD P-CH Data Out N-CH Output Disable 1 SEG Output Disable 2 Circuit Type H-5 Figure 1-11. Pin Circuit Type H-11 1-10 S3C72K8/P72K8 15 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, information on S3C72K8 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics — Absolute maximum ratings — D.C. electrical characteristics — Main system clock oscillator characteristics — Subsystem clock oscillator characteristics — I/O capacitance — Comparator electrical characteristics — A.C. electrical characteristics — Operating voltage range Stop Mode Characteristics and Timing Waveforms — RAM data retention supply voltage in stop mode — Stop mode release timing when initiated by RESET — Stop mode release timing when initiated by an interrupt request Miscellaneous Timing Waveforms — A.C timing measurement points — Clock timing measurement at XIN — Clock timing measurement at XTIN — TCL timing — Input timing for RESET signal — Input timing for external interrupts — Serial data transfer timing 15-1 ELECTRICAL DATA S3C72K8/P72K8 Table 15-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Conditions Rating Units Supply Voltage VDD – – 0.3 to + 6.5 V Input Voltage VI1 All I/O pins active – 0.3 to VDD + 0.3 V Output Voltage VO – – 0.3 to VDD + 0.3 V Output Current High I OH One I/O pin active – 15 mA All I/O pins active – 35 One I/O pin active + 30 (Peak value) Output Current Low I OL mA + 15 (note) All I/O port, total + 100 (Peak value) + 60 (note) Operating Temperature TA – – 40 to + 85 °C Storage Temperature Tstg – – 65 to + 150 °C NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value × 15-2 Duty . S3C72K8/P72K8 ELECTRICAL DATA Table 15-2. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Symbol Conditions Min Typ Max Units – VDD V VIH1 Ports 2, 3, P4.0 and P4.2 0.7 VDD VIH2 Ports 0, 1, P4.1 and RESET 0.8 VDD VDD VIH3 XIN, XOUT and XTIN VDD – 0.1 VDD VIL1 Ports 2, 3, P4.0 and P4.2 VIL2 Ports 0, 1, P4.1 and RESET VIL3 XIN, XOUT and XTIN VOH1 VDD = 4.5 V to 5.5 V IOH = – 3 mA Ports 0, 2, 3 and 4 VDD – 2.0 VDD – 0.4 – VOH2 VDD = 4.5 V to 5.5 V IOH = – 100 µA Ports 5 VDD – 2.0 – – VOL1 VDD = 4.5 V to 5.5 V IOL = 15 mA – 0.4 2 – – 0.3 VDD V 0.2 VDD 0.1 V V Ports 0, 2, 3 and 4 Input High Leakage Current Input Low Leakage Current VOL2 VDD = 4.5 V to 5.5 V IOH = – 100 µA Ports 5 – – 1 ILIH1 VIN = VDD All input pins except those specified below for ILIH2 – – 3 ILIH2 VIN = VDD XIN, XOUT and XTIN ILIL1 VIN = 0 V All input pins except XIN, XOUT, XTIN, µA 20 – – –3 µA and RESET ILIL2 VIN = 0 V XIN, XOUT and XTIN – 20 Output High Leakage Current ILOH VO = VDD All output pins – – 3 µA Output Low Leakage Current ILOL VO = 0 V All output pins – – –3 µA 15-3 ELECTRICAL DATA S3C72K8/P72K8 Table 15-2. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Pull-Up Resistor Symbol RLI RL2 Conditions Min Typ Max Units VIN = 0 V; VDD = 5 V ± 10 % Ports 0-4 15 40 80 kΩ VDD = 3 V ± 10 % 30 80 200 VIN = 0 V; VDD = 5 V ± 10 % 150 220 350 300 400 800 40 60 90 kΩ mV RESET VDD = 3 V ± 10 % LCD Voltage Dividing Resistor RLCD |VDD-COMi| Voltage Drop (i = 0-7) VDC VDD = 2.7 V to 5.5 V – 15 µA per common pin – – 120 |VDD-SEGx| Voltage Drop (x = 0-39) VDS VDD = 2.7 V to 5.5 V – 15 µA per segment pin – – 120 VLC1 Output Voltage VLC2 VDD = 2.0 V to 5.5 V (1) LCD clock = 0 Hz, VLC5 = 0 V 0.8 VDD– 0.2 0.8 VDD 0.8 VDD+ 0.2 VLC2 Output Voltage VLC3 0.6 VDD– 0.2 0.6 VDD 0.6 VDD+ 0.2 VLC3 Output Voltage VLC4 0.4 VDD– 0.2 0.4 VDD 0.4 VDD+ 0.2 VLC4 Output Voltage VLC5 0.2 VDD– 0.2 0.2 VDD 0.2 VDD+ 0.2 15-4 – V S3C72K8/P72K8 ELECTRICAL DATA Table 15-2. D.C. Electrical Characteristics (Concluded) (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 (2) IDD2 (2) Conditions Typ Max Units – 3.5 2.5 8.0 5.5 mA VDD = 5 V ± 10% Crystal oscillator C1 = C2 = 22 pF 6.0 MHz 4.19 MHz VDD = 3 V ± 10% 6.0 MHz 4.19 MHz 1.8 1.3 4.0 3.0 Idle mode VDD = 5 V ± 10% Crystal oscillator C1 = C2 = 22 pF 6.0 MHz 4.19 MHz 1.3 1.2 2.5 1.8 VDD = 3 V ± 10% 6.0 MHz 4.19 MHz 0.5 0.4 1.5 1.0 15 30 6 15 2.5 5 0.5 3 0.2 3 0.1 2 IDD3 (3) VDD = 3 V ± 10% 32 kHz crystal oscillator IDD4 (3) Idle mode; VDD = 3 V ± 10% 32 kHz crystal oscillator IDD5 Min Stop mode; VDD = 5 V ± 10% SCMOD = 0000B XTIN = 0V Stop mode; VDD = 3 V ± 10% VDD = 5 V ± 10% VDD = 3 V ± 10% SCMOD = 0100B – µΑ NOTES: 1. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors, output port drive currents, comparator. 2. Data includes power consumption for subsystem clock oscillation. 3. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the subsystem clock is used. 4. Every values in this table is measured when the power control register (PCON) is set to "0011B". 15-5 ELECTRICAL DATA S3C72K8/P72K8 Table 15-3. Main System Clock Oscillator Characteristics (TA = – 40 °C + 85 °C, VDD = 2.0 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration XIN XOUT C1 Parameter Test Condition Min Typ Max Units Oscillation frequency (1) – 0.4 – 6.0 MHz Stabilization occurs when VDD is equal to the minimum oscillator voltage range. – – 4 ms – 0.4 – 6.0 MHz VDD = 4.5 V to 5.5 V – – 10 ms VDD = 2.7 V to 4.5 V – – 30 XIN input frequency (1) – 0.4 – 6.0 MHz XIN input high and low level width (tXH, tXL) – 83.3 – 1250 ns R = 10 kΩ, VDD = 5 V – 2 – MHz R = 30 kΩ, VDD = 3 V – 1 – C2 Stabilization time (2) Crystal Oscillator XIN XOUT C1 Oscillation frequency (1) C2 Stabilization time (2) External Clock RC Oscillator XIN XOUT XIN XOUT Frequency R NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated. 15-6 S3C72K8/P72K8 ELECTRICAL DATA Table 15-4. Subsystem Clock Oscillator Characteristics (TA = – 40 °C + 85 °C, VDD = 2.0 V to 5.5 V) Oscillator Clock Configuration Crystal Oscillator XTIN XTOUT C1 Parameter Test Condition Min Typ Max Units Oscillation frequency (1) – 32 32.768 35 kHz VDD = 4.5 V to 5.5 V – 1.0 2 s VDD = 2.0 V to 4.5 V – – 10 XTIN input frequency (1) – 32 – 100 kHz XTIN input high and low level width (tXTL, tXTH) – 5 – 15 µs C2 Stabilization time (2) External Clock XTIN XTOUT NOTES: 1. Oscillation frequency and XTIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs. 15-7 ELECTRICAL DATA S3C72K8/P72K8 Table 15-5. Input/Output Capacitance (TA = 25 °C, VDD = 0 V ) Parameter Symbol Condition Min Typ Max Units Input Capacitance CIN f = 1 MHz; Unmeasured pins are returned to VSS – – 15 pF Output Capacitance COUT – – 15 pF CIO – – 15 pF I/O Capacitance Table 15-6. Comparator Electrical Characteristics (TA = – 40 °C + 85 °C, VDD = 4.0 V to 5.5 V) Parameter Input Voltage Range Symbol Condition Min Typ Max Units – – 0 – VDD V Reference Voltage Range VREF 0 VDD V Input Voltage Accuracy VCIN – ± 150 mV Input Leakage Current ICIN, IREF –3 3 µA 15-8 S3C72K8/P72K8 ELECTRICAL DATA Table 15-7. A.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Instruction Cycle Time (note) TCL0 Input Frequency Symbol tCY f TI0, f TI1 Conditions Min Typ Max Units VDD = 2.7 V to 5.5 V 0.67 – 64 µs VDD = 2.0 V to 5.5 V 0.95 – 64 With subsystem clock (fxt) 114 122 125 0 – 1.5 VDD = 2.7 V to 5.5 V VDD = 2.0 V to 5.5 V TCL0 Input High, Low Width SCK Cycle Time tTIH0, tTIL0 tTIH1, tTIL1 tKCY MHz 1 VDD = 2.7 V to 5.5 V 0.48 VDD = 2.0 V to 5.5 V 1.8 VDD = 2.7 V to 5.5 V 800 – – µs – – ns – – ns – – ns – – ns External SCK source Internal SCK source VDD = 2.0 V to 5.5 V 650 3200 External SCK source SCK High, Low Width tKH, tKL Internal SCK source VDD = 2.7 V to 5.5 V 3800 325 External SCK source Internal SCK source VDD = 2.0 V to 5.5 V tKCY/2 – 50 1600 External SCK source Internal SCK source SI Setup Time to SCK High tSIK VDD = 2.7 V to 5.5 V tKCY/2 – 150 100 External SCK source Internal SCK source VDD = 2.0 V to 5.5 V 150 150 External SCK source SI Hold Time to SCK High tKSI Internal SCK source VDD = 2.7 V to 5.5 V 500 400 External SCK source Internal SCK source VDD = 2.0 V to 5.5 V 400 600 External SCK source Internal SCK source 500 NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source. 15-9 ELECTRICAL DATA S3C72K8/P72K8 Table 15-7. A.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Parameter Symbol Output Delay for SCK to SO Conditions tKSO VDD = 2.7 V to 5.5 V Min Typ Max Units – – 300 ns External SCK source Internal SCK source 250 VDD = 2.0 V to 5.5 V 1000 External SCK source Internal SCK source Interrupt Input High, Low Width tINTH, tINTL RESET Input Low Width tRSL 1000 INT0, INT1, INT2, INT4, K0–K3 10 – – µs Input 10 – – µs Main Oscillator Frequency (Divided by 4) CPU Clock 6 MHz 1.5 MHz 1.05 MHz 4.2 MHz 15.6 kHz 1 2 3 4 5 6 7 2.0 V 2.7 V Supply Voltage (V) CPU clock = 1/n x oscillator frequency (n = 4, 8 or 64) Figure 15-1. Standard Operating Voltage Range 15-10 S3C72K8/P72K8 ELECTRICAL DATA Table 15-8. RAM Data Retention Supply Voltage in Stop Mode (TA = – 40 °C to + 85 °C) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage VDDDR – 2.0 – 5.5 V Data retention supply current IDDDR – 0.1 10 µA Release signal set time tSREL 0 – – µs Oscillator stabilization wait time (1) tWAIT Released by RESET – 217 / fx – ms Released by interrupt – (2) – VDDDR = 2.0 V – NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time. 15-11 ELECTRICAL DATA S3C72K8/P72K8 TIMING WAVEFORMS Internal RESET Operation ~ ~ Idle Mode Stop Mode Normal Mode Data Retention Mode ~ ~ VDD VDDDR Execution of STOP Instrction RESET tWAIT tSREL Figure 15-2. Stop Mode Release Timing When Initiated By RESET Idle Mode ~ ~ Normal Mode Stop Mode Data Retention Mode ~ ~ VDD VDDDR Execution of STOP Instrction tSREL tWAIT Power-down Mode Terminating Signal (Interrupt Request) Figure 15-3. Stop Mode Release Timing When Initiated By Interrupt Request 15-12 S3C72K8/P72K8 ELECTRICAL DATA 0.8 VDD 0.8 VDD Measurement Points 0.2 VDD 0.2 VDD Figure 15-4. A.C. Timing Measurement Points (Except for XIN and XTIN) 1/fx tXL tXH XIN VDD - 0.1 V 0.1 V Figure 15-5. Clock Timing Measurement at XIN 1/fxt tXTL tXTH XTIN VDD - 0.1 V 0.1 V Figure 15-6. Clock Timing Measurement at XTIN 15-13 ELECTRICAL DATA S3C72K8/P72K8 1/fTI tTIL tTIH TCL0 0.8 VDD 0.2 VDD Figure 15-7. TCL Timing tRSL RESET 0.2 VDD Figure 15-8. Input Timing for RESET Signal tINTL INT0, 1, 2, 4, K0 to K3 tINTH 0.8 VDD 0.2 VDD Figure 15-9. Input Timing for External Interrupts and Quasi-Interrupts 15-14 S3C72K8/P72K8 ELECTRICAL DATA tKCY tKL tKH SCK 0.8 VDD 0.2 VDD tSIK tKSI 0.8 VDD SI Input Data 0.2 VDD tKSO SO Output Data Figure 15-10. Serial Data Transfer Timing 15-15 S3C72K8/P72K8 16 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C72K8 microcontroller is currently available in a 80-pin QFP package. 23.90 ± 0.30 0-8 20.00 ± 0.20 + 0.10 14.00 ± 0.20 0.10 MAX 80-QFP-1420C 0.80 ± 0.20 17.90 ± 0.30 0.15 - 0.05 #80 #1 0.80 0.35 + 0.10 0.05 MIN 0.15 MAX (0.80) 2.65 ± 0.10 3.00 MAX 0.80 ± 0.20 NOTE: Dimensions are in millimeters. Figure 16-1. 80-QFP-1420C Package Dimensions 16-1 S3C72K8/P72K8 17 S3P72K8 OTP S3P72K8 OTP OVERVIEW The S3P72K8 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C72K8 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P72K8 is fully compatible with the S3C72K8, both in function and in pin configuration except ROM size. Because of its simple programming requirements, the S3P72K8 is ideal for use as an evaluation chip for the S3C72K8. 17-1 S3P72K8 OTP S3C72K8/P72K8 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32/P5.0 SEG33/P5.1 SEG34/P5.2 SEG35/P5.3 SEG36/P5.4 SEG37/P5.5 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 P5.6/SEG38 P5.7/SEG39 VLC1 VLC2 VLC3 VLC4 VLC5 P0.0/SCK/K0 P0.1/SO/K1 SDAT/P0.2/SI/K2 SCLK/P0.3/BUZ/K3 VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT RESET/RESET RESET P1.0/INT0/CIN0 P1.1/INT1/CIN1 P1.1/INT2 P1.3/INT4 P2.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 S3P72K8 (80-QFP-1420C) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 COM5 COM4 COM3 COM2 COM1 COM0 TCLO0/P4.2 TCL0/P4.1 CLO/P4.0 LCDCK/P3.3 LCDSY/P3.2 P3.1 P3.0 P2.3 P2.2 P2.1 Figure 17-1. S3P72K8 Pin Assignments (80-QFP Package) 17-2 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM7 COM6 S3C72K8/P72K8 S3P72K8 OTP Table 17-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P0.2 SDAT 10 I/O P0.3 SCLK 11 I Serial clock pin. Input only pin. TEST VPP 16 I Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) RESET RESET 19 I Chip Initialization VDD/VSS VDD/VSS 12/13 I Logic power supply pin. VDD should be tied to +5 V during programming. Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. Table 17-2. Comparison of S3P72K8 and S3C72K8 Features Characteristic S3P72K8 S3C72K8 Program Memory 8-Kbyte EPROM 8-Kbyte mask ROM Operating Voltage (VDD) 2.0 V to 5.5 V 2.0 V to 5.5 V OTP Programming Mode VDD = 5 V, VPP (TEST) = 12.5V Pin Configuration 80 QFP 80 QFP EPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of the S3P72K8, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 17-3 below. Table 17-3. Operating Mode Selection Criteria VDD VPP (TEST) REG/ MEM Address (A15-A0) R/W Mode 5V 5V 0 0000H 1 EPROM read 12.5 V 0 0000H 0 EPROM program 12.5 V 0 0000H 1 EPROM verify 12.5 V 1 0E3FH 0 EPROM read protection NOTE: "0" means Low level; "1" means High level. 17-3 S3P72K8 OTP S3C72K8/P72K8 NOTES 17-4