L6660
®
MILLI-ACTUATOR DRIVER
PRODUCT PREVIEW
90V BCD MIXED TECHNOLOGY
SO24 PLASTIC SMD PACKAGE
4.5 TO 13.2V OPERATIVE VOLTAGE
±25 TO ±35V OUTPUT VOLTAGE RANGE
SELECTABLE BY EXTERNAL RESISTORS
FULL-WAVE RESONANT DC-DC CONVERTER USING SINGLE COIL FOR DUAL
HIGH VOLTAGE GENERATOR WITH OUTPUT SLEW RATE CONTROL AND SELF
CURRENT LIMITING FOR LOW EMI
±35V OR 0/+70V OPERATIVE VOLTAGE
DRIVING CONFIGURATION MODES:
1. SINGLE ENDED VOLTAGE MODE
2. DIFFERENTIAL VOLTAGE MODE
3. SINGLE ENDED CHARGE MODE
DOUBLE OPERATIONAL AMPLIFIERS WITH
500KHZ GAIN BANDWIDTH PRODUCT AND
LOAD DRIVING CAPABILITY FROM 0.4nF
UP TO 24nF
ANALOG VOLTAGE SHIFTING CIRCUITRY
SO24(Shrink)
INTERNAL 2.5V VOLTAGE REFERENCE
POWER SAVING SLEEP MODE
USER SPECIFIED INPUT REFERENCE
(2.25V DC)
DESCRIPTION
The L6660 is a piezoelectric actuator driver.
BLOCK AND APPLICATION DIAGRAM
[24] HVP
[7] SLEEP
HVP
SLEEP
1
K
-
[17] INB(inv)
[18] OUTK-B
B
[16] INB(not inv)
[19] OUT1-B
+
[10] Vosh
[11] Vin0-5
HVM
Shifter
Vosh=Vin-Vref
1
K
[23] HVM
HVP
K
1
From DAC
OUTPUT
[8] INA(inv)
-
[6] OUTK-A
A
[9] INA(not inv)
HVM
1
K
[4] AorB
MUX
Controll
Logic
+35V
[3] COIL
A-GND
Internal
Current
Bias
[20] V5/12AP
Back-Up
Oscill.
DC-DC LOGIC
Rfdb1
220nF
[14] IN Vref
+
Digital
Pwr Supply
[13] Vref out
2.2nF
47µH
V5/12
[15] WENA
[1] AandB
V512
[5] OUT1-A
+
Rs
-
68nF
Internal Band-gap
and 2.5 reference Voltage
HVM
Rfdb2
-35V
:5
220nF
[12] GND-A
[21] Vfdb
[22] RCcomp
[2] GND-P
100nF
47nF
HVP=VrefIN(1+Rfdb1/Rfdb2)
December 2000
This is preliminary information on a new product now in development. Details are subject to change without notice.
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L6660
PIN CONNECTION SO24-SHIRINK (Top view)
A and B
1
24
HVP
GND-P
2
23
HVM
COIL
3
22
A or B.
4
21
RC comp
VFDB
OUT1-A
5
20
V5/12-AP
OUTK-A
6
19
OUT1-B
SLEEP
7
18
OUTK-B
INA(inv)
8
17
INB(inv)
INA(not inv)
9
16
INB(not inv)
VOSH
10
15
WENA
Vin 0-5
11
14
Vref IN
GND-A
12
13
Vref OUT
PINCON
PIN FUNCTIONS
N.
2/9
Name
Description
1
AandB
MUX Enable (see Tab. 1).
2
GND-P
Power ground.
3
COIL
Coil for positive step UP and capacitor for negative charge.
4
AorB
MUX command Aor B input selection (0 = A; 1 = B).
5
OUT1-A
Output ampl.A.
6
OUTK-A
Hi current output ampl.A.
7
SLEEP
Sleep mode for stand-by condition (0=SLEEP 1=operative).
8
INA (inv)
9
INA (not inv)
10
Vosh
Inverting input of A-amplifier.
Non Inverting input of A-amplifier.
Analog level shifter output Vin-Vref (-2.5 to +2.5 dynamic range)
11
Vin 0-5
Analog level shifter input positive voltage.
12
GND-A
Analog ground.
13
Vref OUT
14
Vref IN
Input for external reference voltage.
15
WENA
Multiplexer Enable, Falling Edge sensitive.
16
INB (not inv)
17
INB (inv)
Inverting input of B-amplifier.
18
OUTK-B
Hi current output ampl.B.
19
OUT1-B
Output ampl.B.
20
V5/12-AP
21
Vfdb
22
RC comp
23
HVM
Negative High voltage generated op. amp. supply.
24
HVP
Positive High voltage generated op. amp. supply.
Precise 2.5V reference voltage.
Non Inverting input of B-amplifier.
Analog&Power voltage supply 5 to 12V.
Feedback voltage for HVP regulator.
DC-DC converter compensation network.
L6660
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V512
Supply voltage pin 17 referred to Ground
14
V
HVP
Positive high voltage referred to HVM
75
V
HVM
Negative high voltage referred to Ground
-38
V
Amplifier input voltage common mode
±6
V
IN A&B
∆V
17
V
Tamb
Operative Ambient Temperature
Maximum difference between pin 20 and pins 8, 9, 16 & 17
-20 to +80
°C
Tstg
Storage Temperature
-40 to +125
°C
All the voltage value are referred to ground unless otherwise specified.
ELECTRICAL CHARACTERISTICS
(All the following parameters are specified @ 27°C and V5/12 = 12V ±5%, unless otherwise specified.)
Symbol
V5/12
HVP (1)
Parameter
Main power supply
Output positive Voltage
HVripple
HVP, HVM ripple
Characterized only, Not Tested
Output current (see figure 1)
I, hvp
I, hvm
Top
Fswitch (2)
Rds, on
Iboost
Vsup
DC gain
GBW
DCinp
Vout
DC, Ibias
Iout (3)
PSRR,P
PSRR,N
Cload
Cint
K
Time to operating condition
Switching Frequency
Boost transistor ON resistance
Boost transistor current limiting
Minimum OpAmp supply
Voltage (HVP if externally
given)
OpAmp DC gain
OpAmp Gain Bandwidth
product
OpAmp Input dynamic voltage
OpAmp Output dynamic voltage
OpAmp Bias supply current
(both)
OpAmp Dynamic Output
Average current with external
supply
OpAmp Positive power supply
rejection ratio
OpAmp Negative power supply
rejection ratio
OpAmp Load capacitance
range
OpAmp Integration capacitance
OpAmp Current ratio
OUTK/OUT1
Test Condition
Double Supply Voltage V512 ≥ 8
Double Supply Voltage V512 < 8
Single Supply Voltage V512 ≥ 8
Single Supply Voltage V512 < 8
External filter cap. 100nF
ILOAD = 0mA
Min.
4.5
27
18
27
18
Refer to Block diagram
page1/10
Double Supply
Single Supply
Cload 0.4nF to 24nF
Double Supply Voltage
Double supply
Single supply
Capacitive load
|HVP| = |HVM| = 35V
Typ.
Max.
13.2
35
35
70
35
Unit
V
V
V
V
V
0.8
V
5
ms
kHz
4
850
Ω
mA
V
300
V512
+4
V512
+4
V
130
500
dB
KHz
-3.5
1.2
HVM
4.5
5
HVP
9
V
V
V
mA
-75
+75
mA
@ 50kHz not tested in production
-50
dB
@ 50kHz not tested in production
-50
dB
Voltage mode Gain min 20dB
0.4
Charge mode Gain min 20dB
0.4
9.8
10
24
nF
24
10.2
nF
3/9
L6660
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Vout0
VrefOUT
Ivref
Vref, cap
Vshifted
Shifter Gain
Parameter
OpAmp Output Voltage with 0V
Input Voltage
Reference Voltage PIN13
Reference Voltage Output Current
Filter capacitor at PIN13
Voltage shift value
(VPIN11 - VPIN10)
Analog Voltage Shifter DC
Voltage Gain
∆V10
∆V11
BWVshift
VrefIN
Isleep
EAoff
IEA
HVP%
Vlogic0
Vlogic1
Ztime
Top
Test Condition
External feedback programmed
for DC gain value <30V/V
1.0V ≤ Vin0-5 ≤ 3.5V
VPIN11 = VREFIN → V’10
VPIN11 = VREFIN + 0.1V → V"10
G=
Shifter circuitry Band Width
External reference voltage
(PIN14)
Total current in Sleep Mode
DC-DC converter Error
Amplifier Input voltage Offset
(VPIN14-VPIN21)
Error amplifier Current
Capability
Total HVP precision
Voltage level for 0 logic at
digital input pin (Pin 1-4-7-15)
Voltage level for 1 logic at
digital input pin (Pin 1-4-7-15)
Decay period for ∆V = |19V|
Min.
-1
Typ.
Max.
+1
Unit
V
2.4
-1
10
VrefIN
-2%
0.975
2.5
2.6
+1
100
VrefIN
+2%
1.025
V
mA
nF
V
VrefIN
1.00
V’’10 − V’10
0.1
3dB amplitude drop
PIN7 at 0 logic
VrefIN = 2.25V
2.0
2
2.6
MHz
V
-12
800
+12
µA
mV
±100
Vref = 2.25V±0%
-4
µA
+4
0.9
1.6
Vref (Pin14) = 2.25V See Fig. 3
0°C < Tcase < 80°C
Operative period from Not
Selected phase to Selected
phase for each driver
140
%
V
V
340
µs
4
µs
Note 1: Selectable by external resistors.
Note 2: Set by external Coil and Capacitor from 80 to 550KHz.
Note 3: Take into account the total power dissipation.
Figure 1. Load Regulation
36
34
12V
10V
8V
9V
11V
HVP Voltage
32
30
7V
28
26
6V
24
5V
22
1 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61 65
Load DC Current (mA)
4/9
OPERATIONAL AMPLIFIERS DESCRIPTION
Each driver has two output stages scaled in current by a factor K = 10.
In voltage mode configuration the two outputs are
shorted.
In charge mode configuration OUT1 drives a capacitor Cint and is closed in feedback, while
OUTK drives the piezo, mirroring the current supplied to Cint, with a current multiplied by a K factor (see Fig.2).
The supply voltage can be internally generated
by the DC-DC converter, or external, maintaining
the DC-DC converter in sleep mode (PIN3
shorted to ground), in this case the supply voltage can be 0 to V5/12+4 minimum value up to
70V in single supply or V5/12+4 to 35V symmetrical to ground.
The drivers have 130dB DC gain and the Bandwidth is 500KHz. Stability is guaranteed with a
minimum gain of 20dB, for a capacitive load in
the range 0.4nF up to 24nF.
L6660
The drivers can be supplied with HVP-HVM (double supply mode) or with HVP-Ground (single
supply mode). In both cases they can achieve a
rail-to rail output dynamic range with an average
load current up to ±75mA.
In double supply mode the input stage has 5V/+5V common mode dynamic range, while in
single supply configuration it has 1.2V up to 10V
input common mode dynamic range.
Figure 2. Charge Mode Configuration (configuration example; the final application depends on
user needs according with Electrical Characteristics).
Qpiezo=K*[Cint*(1+Ra/Rb)+C]*Vdac
Qpiezo=Cost*Vdac
Cost=k*[Cint*(1+Ra/Rb)+C]
HVP
1
K
+
Vdac
-
Cpiezo
HVM
Rb
1
RP
K
Ra
C
Cint
D98IN970A
Input Multiplexer
MULTIPLEXER is controlled by internal logic with 3 digital inputs, supplied by IntVref (2.5V), it is compatible to 3.3V and 5V logic command signals, it allows to perform the following configuration:
Table 1.
AandB
(PIN1)
AorB WENA
(PIN4) (PIN15)
INA+Status
INB+Status
Comment
0
1
X
INA+
connected to AGND
INB+
connected to AGND
Both drv. inp. are disconnected from ext
PIN and are connected to AGND
0
0
X
INA+
connected to PIN9
INB+
connected to PIN16
Both drv. inp. are accesible
(MUX is transparent)
1
1
1
INA+
connected to PIN9
INB+
connected to AGND
INA is selected
1
0
1
INA+
connected to AGND
INB+
connected to PIN16
INB is selected
1
1
(F.E.)
INA+
connected to PIN9
INB+
connected to AGND
From WENA Falling Edge, changes on
AorB (pin 4) will not change MUX state.
1
0
(F.E.)
INA+
connected to AGND
INB+
connected to PIN16
From WENA Falling Edge, changes on
AorB (pin 4) will not change MUX state.
F.E. = Falling Edge
The MUX is at NOT inv. Inputs, and NO current flows through the MUX switches, because the driver input stage is designed with high impedance stage.
5/9
L6660
Figure 3. Not selected driver return to Zero Output voltage. Both drivers have the same behavior.
The device is in operative condition and AandB (Pin1) and WENA (Pin15) are at 1 logic
condition. The external feedback programmed for a DC gain value <30V/V.
Drivers
OUTPUT
Voltage
+20V
Deselected
Driver Output
Voltage
+2V
0
t
AorB
(PIN4)
Ztime
AorB
(PIN4)
Ztime
Drivers
OUTPUT
Voltage
0
-2V
t
Deselected
Driver Output
Voltage
-20V
6/9
L6660
Not selected Output return to 0V
Using the Multiplexer features and selecting just
one driver, the second one, leaves its output voltage and "goes" to 0V (have showed in Fig. 3), in
"long time" with controlled slope see table 1.
PIN21. The HVP voltage is programmed by two
external resistors as shown in the block diagram,
its value is:
Voltage reference
An internal 2.5V voltage reference generator is
connected to PIN13 (VrefOUT); it is based on an
internal Band-Gap reference with a total precision
of ±4% and a current capability of ±1.0mA, it is always present even in sleep mode condition.
This voltage is used to supply the internal MUX
logic, allowing both 3.3V or 5V logic input signals,
also the internal bias current is based on this reference.
The DC-DC converter reference voltage comes
from PIN14 (VrefIN), so that the user can use an
external voltage reference (from 2.0V up to 2.6V)
or the internal one, in this case, just shorting together VrefOUT and VrefIN (PIN13 and PIN14).
The DC-DC control loop precision will be improved lower than ±4% respect external reference voltage and resistor voltage divider.
In Sleep Mode HVM is shorted to GND. When in
single supply, HVM must be connected to GND.
The topology is a standard resonant full-wave
boost one: the LC oscillation is kept running all
the time and a set of comparators is used to synchronize turning on and off of the power MOS in
order to have zero current and zero voltage
switching and furthermore controlled rectification.
The step-up converter is designed to work in Linear mode, and an AC compensation network is
required (RC-comp) to guarantee the stability in a
wide operative range (i.e. changing coil, load,
output and input voltage...).
According to the ouput voltage, the current
loaded into the coil is changing like a Voltage
Loop-Current Controlled system, and in every
pulse there is a regulated power transfer to the
load.
The resonant LC topology has been chosen in order to limit the voltage slew-rate across the coil
within reasonable values and so, to minimize radiation problems.
The negative converter is a simple charge transfer: it is supplied by the positive high voltage and
it capacitively translates this positive voltage
down to a negative one, obviously to limit radiation problems also the charge output has a limited slew-rate; moreover to reduce intermodulation phoenomenas the charge output is
synchronized with the LC oscillations of the resonant boost.
This negative voltage is (not counting drops on
external rectification diodes) in tracking with the
positive one and so the negative output controller
is not required.
If the drivers are supplied by HVP & HVM generated by external power supply the error amplifier
output has to be connected to V5/12.
In the external supply configuration the maximum
voltage between HVP and HVM (|HVP| + |HVM|)
must not exceed 70V and maximum voltage between GND and HVM must be lower than 35V.
Voltage Shifter
A voltage shifter is inserted to allow a ground
symmetrical driving voltage on the piezo, starting
from a positive (0V up to 5V) input signal coming
from a positive supplied DAC. The DC Input-Output typical tranfer function is plotted in Fig. 4. This
block works only in Double Supply mode, obviously it doesn’t work if no negative supply is present. The voltage shifter output has not DC-current capability.
For more details see the application note.
DC-DC CONVERTER DESCRIPTION
The DC-DC converter inside the chip can be supplied from 5V up to 12V and has two parts, one to
supply the positive and one to supply the negative voltage.
The DC-DC converter loop "measures" the HVP
voltage by the EXTERNAL voltage divider and
Figure 4. Shifter DC transfer function
Vosh
PIN10
VIN,MAX - VrefIN
0
VrefIN
0-VrefIN
VIN,MAX
VHVP = VPIN21 ⋅ (1 +
Rfdb1
)
Rfdb2
Vin0-5
PIN11
5.0V IF V5/12 > 5.5V
VIN,MAX =
{ V5/12 - 0.5V IF V
5/12
≤ 5.5V
7/9
L6660
mm
inch
OUTLINE AND
MECHANICAL DATA
DIM.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.00
0.079
A1
0.25
0.010
A2
1.51
2.00
0.060
B
0.25
0.35
0.010
C
0.10
0.35
0.004
0.014
D
8.35
9.35
0.33
0.37
E
7.60
8.70
0.30
0.34
E1
5.02
6.22
0.20
e
0.30
6.10
0.65
k
L
0.079
0.012
0.24
0.014
0.244
0.025
0˚ (min), 10˚ (max)
0.25
0.50
0.80
0.010
SSO24 (SHRINK)
0.020
0.031
A2
A
K
0.10mm
B
e
A1
C
L
E1
.004
Seating Plane
D
24
13
E
1
12
SSO24ME
8/9
L6660
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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