STMICROELECTRONICS M41T64

M41T62, M41T63
M41T64, M41T65
Serial Access Real-Time Clock with Alarms
FEATURES SUMMARY
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350nA TIMEKEEPING CURRENT @ 3V
TIMEKEEPING DOWN TO 1.0V
1.3V TO 3.6V I2C BUS OPERATING
VOLTAGE
COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, AND
CENTURY
SERIAL INTERFACE SUPPORTS I2C BUS
(400kHz)
PROGRAMMABLE ALARM WITH FLAG BIT
ONLY (M41T63/64)
PROGRAMMABLE ALARM WITH FLAG BIT
AND INTERRUPT FUNCTION (M41T62/65)
LOW OPERATING CURRENT OF 35µA
SOFTWARE CLOCK CALIBRATION
OSCILLATOR STOP DETECTION
32KHz SQUARE WAVE ON POWER-UP
(M41T62/63/64)
WATCHDOG TIMER
WATCHDOG OUTPUT (M41T63/65)
AUTOMATIC LEAP YEAR COMPENSATION
OPERATING TEMPERATURE OF –40 TO
85°C
LEAD-FREE 16-PIN QFN PACKAGE
TOTAL SURFACE AREA OF IC AND 32KHz
CRYSTAL IS 21.5mm2
Figure 1. Package
QFN16 (Q)
3mm x 3mm
Figure 2. 32KHz Crystal + QFN16 vs. VSOJ20
VSOJ20 (47.6mm2)
2
GND Plane Guard Ring (21.5mm )
SMT
CRYSTAL
1
XI
2
XO
3
4
ST QFN16
AI11107
Table 1. Device Options
Basic RTC
Alarms
OSC Fail
Detect
Watchdog
Timer
Calibration
SQW
Output
IRQ
Output
M41T62
✔
✔
✔
✔
✔
✔
✔
M41T63
✔
✔
✔
✔
✔
✔
M41T64
✔
✔
✔
✔
✔
✔
M41T65
✔
✔
✔
✔
✔
May 2005
WDO
Output
F32K
Output
✔
✔
✔
✔
1/33
M41T62/63/64/65
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. 32KHz Crystal + QFN16 vs. VSOJ20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. M41T62 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. M41T64 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 5. M41T63 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 6. M41T65 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 7. M41T62 16-pin QFN Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 8. M41T63 16-pin QFN Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 9. M41T64 16-pin QFN Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 10.M41T65 16-pin QFN Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 11.M41T62 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 12.M41T63 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 13.M41T64 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 14.M41T65 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 15.Hardware Hookup for Battery Back-up Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 16.Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 17.Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 18.Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 19.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 20.Alternative READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 21.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TIMEKEEPER® Registers . . . . . .
Table 3. M41T62 Register Map . .
Table 4. M41T63 Register Map . .
Table 5. M41T64 Register Map . .
Table 6. M41T65 Register Map . .
2/33
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. . . . 13
. . . . 14
. . . . 15
. . . . 16
. . . . 17
M41T62/63/64/65
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 22.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 23.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Setting Alarm Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24.Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Alarm Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Watchdog Output (WDO - M41T63/65 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Square Wave Output (M41T62/63/64). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 8. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Full-time 32KHz Square Wave Output (M41T64). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Century Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Output Driver Pin (M41T62/65) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Oscillator Stop Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 9. Initial Power-on Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 10. Century Bits Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 12. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 25.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 26.Crystal Isolation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 13. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 15. Crystal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 27.Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 17. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 28.QFN16 – 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Outline . . . . . . . . 28
Table 18. QFN16 – 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Mechanical Data . 29
Figure 29.QFN16 – 16-lead, Quad, Flat Package, No Lead, 3x3mm, Recommended Footprint . . 30
Figure 30.32KHz Crystal + QFN16 vs. VSOJ20 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . 30
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 19. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 20. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3/33
M41T62/63/64/65
SUMMARY DESCRIPTION
The M41T6x Serial Access TIMEKEEPER® is a
low power Serial RTC with a built-in 32.768 kHz
oscillator (external crystal controlled). Eight registers (see Table 3., page 14) are used for the clock/
calendar function and are configured in binary
coded decimal (BCD) format. An additional 8 registers provide status/control of Alarm, 32KHz output, Calibration, and Watchdog functions.
Addresses and data are transferred serially via a
two line, bi-directional I2C interface. The built-in
address register is incremented automatically after each WRITE or READ data byte.
Functions available to the user include a time-ofday clock/calendar, Alarm interrupts (M41T62/65),
32KHz output (M41T64), programmable Square
Wave output (M41T62/63/64), and Watchdog output (M41T63/65). The eight clock address locations contain the century, year, month, date, day,
hour, minute, second and tenths/hundredths of a
second in 24 hour BCD format. Corrections for 28, 29- (leap year), 30- and 31-day months are made
automatically.
The M41T6x is supplied in a 16-pin QFN.
Figure 3. M41T62 Logic Diagram
Figure 5. M41T63 Logic Diagram
VCC
VCC
XI
XI
(1)
XO
IRQ/OUT
M41T62
(2)
SCL
SQW
WDO(1)
XO
M41T63
SCL
SQW(2)
SDA
SDA
VSS
VSS
AI09103
AI09189
Note: 1. Open Drain.
2. Defaults to 32KHz on power-up.
Note: 1. Open Drain.
2. Defaults to 32KHz on power-up.
Figure 4. M41T64 Logic Diagram
Figure 6. M41T65 Logic Diagram
VCC
VCC
XI
XI
(1)
XO
SQW
M41T64
SCL
M41T65
(2)
F32K
SCL
IRQ/FT/OUT(1)
SDA
SDA
VSS
Note: 1. Open Drain.
2. Defaults to 32KHz on power-up.
4/33
WDO(1)
XO
VSS
AI09108
Note: 1. Open Drain.
AI09109
M41T62/63/64/65
NC
VCC
NC
NC
NC
VCC
NC
16
15
14
13
16
15
14
13
VSS
3
10
SCL
(1)
4
9
SDA
5
6
7
8
NC
XO
2
11
IRQ/FT/OUT(1)
VSS
3
10
SCL
(1)
4
9
SDA
WDO
AI09100
Note: 1. SQW Output will default to 32KHz upon power-up.
2. Open Drain.
5
6
7
8
NC
IRQ/OUT(2)
12
NC
11
1
NC
2
XI
VSS
XO
NC
NC
NC
12
NC
1
VSS
XI
SQW
Figure 10. M41T65 16-pin QFN Connections
NC
Figure 7. M41T62 16-pin QFN Connections
AI09102
Note: 1. Open Drain.
Table 2. Signal Names
NC
NC
VCC
NC
Figure 8. M41T63 16-pin QFN Connections
16
15
14
13
XI
Oscillator Input
XO
Oscillator Output
SDA
Serial Data Input/Output
SCL
Serial Clock Input
XO
2
11
WDO(2)
VSS
3
10
SCL
IRQ/OUT
(1)
4
9
SDA
IRQ/FT/
OUT
SQW
5
6
7
8
NC
NC
NC
12
NC
1
VSS
XI
AI09190
Interrupt or OUT Output (Open
Drain)
Interrupt, Frequency Test, or OUT
Output (Open Drain)
SQW
Programmable Square Wave Defaults to 32KHz on Power-up
(Open Drain for M41T64 only)
F32K
Dedicated 32KHz Output (M41T64
only)
WDO
Watchdog Timer Output (Open
Drain)
Note: 1. SQW Output will default to 32KHz upon power-up.
2. Open Drain.
NC
NC
VCC
NC
Figure 9. M41T64 16-pin QFN Connections
16
15
14
13
XO
2
11
SQW
VSS
3
10
SCL
(1)
4
9
SDA
F32K
5
6
7
8
NC
NC
NC
12
NC
1
VSS
XI
VCC
Supply Voltage
VSS
Ground
(2)
AI09101
Note: 1. Enabled on power-up.
2. Open Drain.
5/33
M41T62/63/64/65
Figure 11. M41T62 Block Diagram
REAL TIME CLOCK
CALENDAR
XTAL
32KHz
OSCILLATOR
OSCILLATOR FAIL OFIE
DETECT
RTC W/ALARM
SDA
I2C
INTERFACE
SCL
AFE
(1)
IRQ/OUT
WATCHDOG
SQUARE WAVE
SQWE
(2)
SQW
AI08899a
Note: 1. Open Drain.
2. Defaults to 32KHz on power-up.
Figure 12. M41T63 Block Diagram
REAL TIME CLOCK
CALENDAR
XTAL
32KHz
OSCILLATOR
OSCILLATOR FAIL
DETECT
RTC W/ALARM
SDA
I2C
INTERFACE
SCL
(1)
WATCHDOG
SQUARE WAVE
WDO
SQWE
(2)
SQW
AI09191
Note: 1. Open Drain.
2. Defaults to 32KHz on power-up.
Figure 13. M41T64 Block Diagram
32KE
F32K(1)
REAL TIME CLOCK
CALENDAR
XTAL
32KHz
OSCILLATOR
OSCILLATOR FAIL
DETECT
RTC W/ALARM
SDA
I2C
INTERFACE
SCL
WATCHDOG
SQUARE WAVE
SQWE
(2)
SQW
AI09192
Note: 1. Defaults enabled on power-up.
2. Open Drain.
6/33
M41T62/63/64/65
Figure 14. M41T65 Block Diagram
REAL TIME CLOCK
CALENDAR
OSCILLATOR FAIL OFIE
DETECT
FT
32KHz
OSCILLATOR
XTAL
RTC W/ALARM
SDA
I2C
INTERFACE
(1)
AFE
IRQ/FT/OUT
WDO(1)
WATCHDOG
SCL
AI09193
Note: 1. Open Drain.
Figure 15. Hardware Hookup for Battery Back-up Operation
VCC
(1)
MCU
M41T6x
VCC
XI
XO
VSS
VCC
(2)
IRQ/FT/OUT
(3)
WDO
(4)
SQW
Port
Reset Input
SQWIN
SCL
Serial Clock Line
SDA
Serial Data Line
F32K
32KHz CLKIN
AI10400
Note: 1.
2.
3.
4.
Diode required on open drain pin (M41T65 only) for battery (or SuperCap) back-up. Low threshold BAT42 diode recommended.
For M41T62 and M41T65 (Open Drain).
For M41T63 and M41T65 (Open Drain).
For M41T64 (Open Drain).
7/33
M41T62/63/64/65
OPERATION
The M41T6x clock operates as a slave device on
the serial bus. Access is obtained by implementing
a start condition followed by the correct slave address (D0h). The 16 bytes contained in the device
can then be accessed sequentially in the following
order:
1. Tenths/Hundredths of a Second Register
2. Seconds Register
3. Minutes Register
4. Hours Register
5. Square Wave/Day Register
6. Date Register
7. Century/Month Register
8. Year Register
9. Calibration Register
10. Watchdog Register
11 - 15. Alarm Registers
16. Flags Register
2-Wire Bus Characteristics
The bus is intended for communication between
different ICs. It consists of two lines: a bi-directional data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the
bus is not busy.
– During data transfer, the data line must remain
stable whenever the clock line is High.
– Changes in the data line, while the clock line is
High, will be interpreted as control signals.
8/33
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from high to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The devices that are controlled by the master are called
“slaves.”
M41T62/63/64/65
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low during the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
Figure 16. Serial Bus Data Transfer Sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
Figure 17. Acknowledgement Sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
1
MSB
2
8
9
LSB
DATA OUTPUT
BY RECEIVER
AI00601
9/33
M41T62/63/64/65
READ Mode
In this mode the master reads the M41T6x slave
after setting the slave address (see Figure
19., page 11). Following the WRITE Mode Control
Bit (R/W=0) and the Acknowledge Bit, the word
address 'An' is written to the on-chip address
pointer. Next the START condition and slave address are repeated followed by the READ Mode
Control Bit (R/W=1). At this point the master transmitter becomes the master receiver. The data byte
which was addressed will be transmitted and the
master receiver will send an Acknowledge Bit to
the slave transmitter. The address pointer is only
incremented on reception of an Acknowledge
Clock. The M41T6x slave transmitter will now
place the data byte at address An+1 on the bus,
the master receiver reads and acknowledges the
new byte and the address pointer is incremented
to “An+2.”
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume due
to a Stop Condition or when the pointer increments
to any non-clock address (08h-0Fh).
Note: This is true both in READ Mode and WRITE
Mode.
An alternate READ Mode may also be implemented whereby the master reads the M41T6x slave
without first writing to the (volatile) address pointer. The first address that is read is the last one
stored in the pointer (see Figure 20., page 11).
Figure 18. Slave Address Location
R/W
START
A
1
LSB
MSB
SLAVE ADDRESS
1
0
1
0
0
0
AI00602
10/33
M41T62/63/64/65
SLAVE
ADDRESS
DATA n+1
ACK
DATA n
ACK
S
ACK
BUS ACTIVITY:
R/W
START
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 19. READ Mode Sequence
STOP
SLAVE
ADDRESS
DATA n+X
P
NO ACK
AI00899
STOP
R/W
SLAVE
ADDRESS
DATA n+X
P
NO ACK
BUS ACTIVITY:
DATA n+1
ACK
DATA n
ACK
S
ACK
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 20. Alternative READ Mode Sequence
AI00895
11/33
M41T62/63/64/65
WRITE Mode
In this mode the master transmitter transmits to
the M41T6x slave receiver. Bus protocol is shown
in Figure 21., page 12. Following the START condition and slave address, a logic '0' (R/W=0) is
placed on the bus and indicates to the addressed
device that word address “An” will follow and is to
be written to the on-chip address pointer. The data
word to be written to the memory is strobed in next
and the internal address pointer is incremented to
the next address location on the reception of an
acknowledge clock. The M41T6x slave receiver
will send an acknowledge clock to the master
transmitter after it has received the slave address
see Figure 18., page 10 and again after it has received the word address and each data byte.
SLAVE
ADDRESS
12/33
STOP
DATA n+X
P
ACK
DATA n+1
ACK
BUS ACTIVITY:
DATA n
ACK
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 21. WRITE Mode Sequence
AI00591
M41T62/63/64/65
CLOCK OPERATION
The M41T6x is driven by a quartz-controlled oscillator with a nominal frequency of 32.768kHz. The
accuracy of the Real-Time Clock depends on the
frequency of the quartz crystal that is used as the
time-base for the RTC.
The eight byte clock register (see Table
3., M41T62 Register Map, Table 4., M41T63 Register Map, Table 5., M41T64 Register Map, and
Table 6., M41T65 Register Map) is used to both
set the clock and to read the date and time from
the clock, in a binary coded decimal format.
Tenths/Hundredths of Seconds, Seconds, Minutes, and Hours are contained within the first four
registers.
Note: A WRITE to any clock register will result in
the Tenths/Hundredths of Seconds being reset to
“00,” and Tenths/Hundredths of Seconds cannot
be written to any value other than “00.”
Bits D0 through D2 of Register 04h contain the
Day (day of week). Registers 05h, 06h, and 07h
contain the Date (day of month), Month, and
Years. The ninth clock register is the Calibration
Register (this is described in the Clock Calibration
section). Bit D7 of Register 01h contains the STOP
Bit (ST). Setting this bit to a '1' will cause the oscillator to stop. When reset to a '0' the oscillator restarts within one second (typical).
Note: Upon initial power-up, the user should set
the ST Bit to a '1,' then immediately reset the ST
Bit to '0.' This provides an additional “kick-start” to
the oscillator circuit.
Bit D7 of Register 02h (Minute Register) contains
the Oscillator Fail Interrupt Enable Bit (OFIE).
When the user sets this bit to '1,' any condition
which sets the Oscillator Fail Bit (OF) (see Oscillator Stop Detection, page 23) will also generate an
interrupt output.
Bits D6 and D7 of Clock Register 06h (Century/
Month Register) contain the CENTURY Bit 0
(CB0) and CENTURY Bit 1 (CB1).
Note: A WRITE to ANY location within the first
eight bytes of the clock register (00h-07h), including the OFIE Bit, RS0-RS3 Bit, and CB0-CB1 Bits
will result in an update of the system clock and a
reset of the divider chain. This could result in an inadvertent change of the current time. These nonclock related bits should be written prior to setting
the clock, and remain unchanged until such time
as a new clock time is also written.
The eight Clock Registers may be read one byte at
a time, or in a sequential block. Provision has been
made to assure that a clock update does not occur
while any of the eight clock addresses are being
read. If a clock address is being read, an update of
the clock registers will be halted. This will prevent
a transition of data during the READ.
TIMEKEEPER ® Registers
The M41T6x offers 16 internal registers which
contain Clock, Calibration, Alarm, Watchdog,
Flags, and Square Wave. The Clock registers are
memory locations which contain external (user accessible) and internal copies of the data (usually
referred to as BiPORT™ TIMEKEEPER cells). The
external copies are independent of internal functions except that they are updated periodically by
the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will
be reset upon the completion of a WRITE to any
clock address (00h to 07h).
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume either due to a Stop Condition or when the pointer
increments to a non-clock address.
TIMEKEEPER and Alarm Registers store data in
BCD format. Calibration, Watchdog, and Square
Wave Bits are written in a Binary Format.
13/33
M41T62/63/64/65
Table 3. M41T62 Register Map
Addr
D7
00h
D6
D5
D4
D3
0.1 Seconds
D2
D1
D0
Function/Range BCD
Format
0.01 Seconds
10ths/100ths
of Seconds
00-99
01h
ST
10 Seconds
Seconds
Seconds
00-59
02h
OFIE
10 Minutes
Minutes
Minutes
00-59
03h
0
0
Hours (24 Hour Format)
Hours
00-23
04h
RS3
RS2
Day
01-7
05h
0
0
Date: Day of Month
Date
01-31
06h
CB1
CB0
Month
Century/
Month
0-3/01-12
Year
Year
00-99
07h
10 Hours
RS1
RS0
10 Date
0
Day of Week
10M
10 Years
08h
OUT
0
S
09h
RB2
BMB4
BMB3
BMB2
0Ah
AFE
SQWE
0
Al 10M
0Bh
RPT4
RPT5
0Ch
RPT3
0
0Dh
RPT2
0Eh
RPT1
0Fh
WDF
Calibration
BMB1
BMB0
Calibration
RB1
RB0
Watchdog
Alarm Month
Al Month
01-12
AI 10 Date
Alarm Date
Al Date
01-31
AI 10 Hour
Alarm Hour
Al Hour
00-23
Alarm 10 Minutes
Alarm Minutes
Al Min
00-59
Alarm 10 Seconds
Alarm Seconds
Al Sec
00-59
AF
0
Keys: 0 = Must be set to '0'
AF = Alarm Flag (Read only)
AFE = Alarm Flag Enable Flag
BMB0 - BMB4 = Watchdog Multiplier Bits
CB0-CB1 = Century Bits
OF = Oscillator Fail Bit
OFIE = Oscillator Fail Interrupt Enable Bit
OUT = Output level
14/33
0
0
0
OF
0
0
Flags
RB0 - RB2 = Watchdog Resolution Bits
RPT1-RPT5 = Alarm Repeat Mode Bits
RS0-RS3 = SQW Frequency Bits
S = Sign Bit
SQWE = Square Wave Enable Bit
ST = Stop Bit
WDF = Watchdog Flag Bit (Read only)
M41T62/63/64/65
Table 4. M41T63 Register Map
Addr
D7
00h
D6
D5
D4
D3
0.1 Seconds
D2
D1
D0
Function/Range BCD
Format
0.01 Seconds
10ths/100ths
of Seconds
00-99
01h
ST
10 Seconds
Seconds
Seconds
00-59
02h
0
10 Minutes
Minutes
Minutes
00-59
03h
0
0
Hours (24 Hour Format)
Hours
00-23
04h
RS3
RS2
Day
01-7
05h
0
0
Date: Day of Month
Date
01-31
06h
CB1
CB0
Month
Century/
Month
0-3/01-12
Year
Year
00-99
07h
10 Hours
RS1
RS0
0
10 Date
0
Day of Week
10M
10 Years
08h
0
0
S
Calibration
09h
RB2
BMB4
BMB3
BMB2
0Ah
0
SQWE
0
Al 10M
0Bh
RPT4
RPT5
0Ch
RPT3
0
0Dh
RPT2
0Eh
RPT1
0Fh
WDF
BMB1
BMB0
Calibration
RB1
RB0
Watchdog
Alarm Month
Al Month
01-12
AI 10 Date
Alarm Date
Al Date
01-31
AI 10 Hour
Alarm Hour
Al Hour
00-23
Alarm 10 Minutes
Alarm Minutes
Al Min
00-59
Alarm 10 Seconds
Alarm Seconds
Al Sec
00-59
AF
0
Keys: 0 = Must be set to '0'
AF = Alarm Flag (Read only)
BMB0 - BMB4 = Watchdog Multiplier Bits
CB0-CB1 = Century Bits
OF = Oscillator Fail Bit
RB0 - RB2 = Watchdog Resolution Bits
0
0
OF
0
0
Flags
RPT1-RPT5 = Alarm Repeat Mode Bits
RS0-RS3 = SQW Frequency Bits
S = Sign Bit
SQWE = Square Wave Enable Bit
ST = Stop Bit
WDF = Watchdog Flag Bit (Read only)
15/33
M41T62/63/64/65
Table 5. M41T64 Register Map
Addr
D7
00h
D6
D5
D4
D3
0.1 Seconds
D2
D1
D0
Function/Range BCD
Format
0.01 Seconds
10ths/100ths
of Seconds
00-99
01h
ST
10 Seconds
Seconds
Seconds
00-59
02h
0
10 Minutes
Minutes
Minutes
00-59
03h
0
0
Hours (24 Hour Format)
Hours
00-23
04h
RS3
RS2
Day
01-7
05h
0
0
Date: Day of Month
Date
01-31
06h
CB1
CB0
Month
Century/
Month
0-3/01-12
Year
Year
00-99
07h
10 Hours
RS1
RS0
10 Date
0
Day of Week
10M
10 Years
08h
0
0
S
09h
RB2
BMB4
BMB3
BMB2
0Ah
0
SQWE
32KE
Al 10M
0Bh
RPT4
RPT5
0Ch
RPT3
0
0Dh
RPT2
0Eh
RPT1
0Fh
WDF
Calibration
BMB1
BMB0
Calibration
RB1
RB0
Watchdog
Alarm Month
Al Month
01-12
AI 10 Date
Alarm Date
Al Date
01-31
AI 10 Hour
Alarm Hour
Al Hour
00-23
Alarm 10 Minutes
Alarm Minutes
Al Min
00-59
Alarm 10 Seconds
Alarm Seconds
Al Sec
00-59
AF
0
Keys: 0 = Must be set to '0'
32KE = 32KHz Enable Bit
AF = Alarm Flag (Read only)
BMB0 - BMB4 = Watchdog Multiplier Bits
CB0-CB1 = Century Bits
OF = Oscillator Fail Bit
RB0 - RB2 = Watchdog Resolution Bits
16/33
0
0
0
OF
0
0
Flags
RPT1-RPT5 = Alarm Repeat Mode Bits
RS0-RS3 = SQW Frequency Bits
S = Sign Bit
SQWE = Square Wave Enable Bit
ST = Stop Bit
WDF = Watchdog Flag Bit (Read only)
M41T62/63/64/65
Table 6. M41T65 Register Map
Addr
D7
00h
D6
D5
D4
D3
0.1 Seconds
D2
D1
D0
Function/Range BCD
Format
0.01 Seconds
10ths/100ths
of Seconds
00-99
01h
ST
10 Seconds
Seconds
Seconds
00-59
02h
OFIE
10 Minutes
Minutes
Minutes
00-59
03h
0
0
Hours (24 Hour Format)
Hours
00-23
04h
0
0
Day
01-7
05h
0
0
Date: Day of Month
Date
01-31
06h
CB1
CB0
Month
Century/
Month
0-3/01-12
Year
Year
00-99
07h
10 Hours
0
0
0
10 Date
0
Day of Week
10M
10 Years
08h
OUT
FT
S
Calibration
09h
RB2
BMB4
BMB3
BMB2
0Ah
AFE
0
0
Al 10M
0Bh
RPT4
RPT5
0Ch
RPT3
0
0Dh
RPT2
0Eh
RPT1
0Fh
WDF
BMB1
BMB0
Calibration
RB1
RB0
Watchdog
Alarm Month
Al Month
01-12
AI 10 Date
Alarm Date
Al Date
01-31
AI 10 Hour
Alarm Hour
Al Hour
00-23
Alarm 10 Minutes
Alarm Minutes
Al Min
00-59
Alarm 10 Seconds
Alarm Seconds
Al Sec
00-59
AF
0
Keys: 0 = Must be set to '0'
AF = Alarm Flag (Read only)
AFE = Alarm Flag Enable Flag
BMB0 - BMB4 = Watchdog Multiplier Bits
CB0-CB1 = Century Bits
FT = Frequency Test Bit
OF = Oscillator Fail Bit
0
0
OF
0
0
Flags
OFIE = Oscillator Fail Interrupt Enable Bit
OUT = Output level
RB0 - RB2 = Watchdog Resolution Bits
RPT1-RPT5 = Alarm Repeat Mode Bits
S = Sign Bit
ST = Stop Bit
WDF = Watchdog Flag Bit (Read only)
17/33
M41T62/63/64/65
Calibrating the Clock
The M41T6x is driven by a quartz controlled oscillator with a nominal frequency of 32,768Hz. The
accuracy of the Real-Time Clock depends on the
frequency of the quartz crystal that is used as the
time-base for the RTC. The accuracy of the clock
is dependent upon the accuracy of the crystal, and
the match between the capacitive load of the oscillator circuit and the capacitive load for which the
crystal was trimmed. The M41T6x oscillator is designed for use with a 6pF crystal load capacitance.
When the Calibration circuit is properly employed,
accuracy improves to better than ±2 ppm at 25°C.
The oscillation rate of crystals changes with temperature (see Figure 22., page 19). Therefore, the
M41T6x design employs periodic counter correction. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure
23., page 19. The number of times pulses which
are blanked (subtracted, negative calibration) or
split (added, positive calibration) depends upon
the value loaded into the five Calibration Bits found
in the Calibration Register. Adding counts speeds
the clock up, subtracting counts slows the clock
down.
The Calibration Bits occupy the five lower order
bits (D4-D0) in the Calibration Register (08h).
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign Bit;
'1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64
minute cycle. The first 62 minutes in the cycle
may, once per minute, have one second either
shortened by 128 or lengthened by 256 oscillator
cycles. If a binary '1' is loaded into the register,
only the first 2 minutes in the 64 minute cycle will
be modified; if a binary 6 is loaded, the first 12 will
be affected, and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
18/33
+4.068 or –2.034 PPM of adjustment per calibration step in the calibration register.
Assuming that the oscillator is running at exactly
32,768 Hz, each of the 31 increments in the Calibration byte would represent +10.7 or –5.35 seconds per day which corresponds to a total range of
+5.5 or –2.75 minutes per month (see Figure
23., page 19).
Two methods are available for ascertaining how
much calibration a given M41T6x may require:
– The first involves setting the clock, letting it run
for a month and comparing it to a known
accurate reference and recording deviation
over a fixed period of time. Calibration values,
including the number of seconds lost or gained
in a given period, can be found in Application
Note AN934, “TIMEKEEPER®
CALIBRATION.” This allows the designer to
give the end user the ability to calibrate the
clock as the environment requires, even if the
final product is packaged in a non-user
serviceable enclosure. The designer could
provide a simple utility that accesses the
Calibration byte.
– The second approach is better suited to a
manufacturing environment, and involves the
use of either the SQW pin (M41T62/63/64) or
the IRQ/FT/OUT pin (M41T65). The SQW pin
will toggle at 512Hz when RS3 = '0,' RS2 = '1,'
RS1 = '1,' RS0 = '0,' SQWE = '1,' and ST = '0.'
Alternatively, for the M41T65, the IRQ/FT/
OUT pin will toggle at 512Hz when FT and
OUT Bits = '1' and ST = '0.'
Any deviation from 512Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of
512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring a –10 (XX001010) to
be loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency test or Square
Wave output frequency.
M41T62/63/64/65
Figure 22. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
∆F = K x (T – T )2
O
F
–80
2
2
K = –0.036 ppm/°C ± 0.006 ppm/°C
–100
TO = 25°C ± 5°C
–120
–140
–160
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI07888
Figure 23. Calibration Waveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
19/33
M41T62/63/64/65
Setting Alarm Clock Registers
Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second, or repeat every year, month,
day, hour, minute, or second. Bits RPT5–RPT1
put the alarm in the repeat mode of operation. Table 7., page 20 shows the possible configurations.
Codes not listed in the table default to the once per
second mode to quickly alert the user of an incorrect alarm setting.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5–RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set (M41T62/65), the
alarm condition activates the IRQ/OUT or IRQ/FT/
OUT pin. To disable the alarm, write '0' to the
Alarm Date Register and to RPT5–RPT1.
Note: If the address pointer is allowed to increment to the Flag Register address, an alarm condition will not cause the Interrupt/Flag to occur until
the address pointer is moved to a different address. It should also be noted that if the last address written is the “Alarm Seconds,” the address
pointer will increment to the Flag address, causing
this situation to occur.
The IRQ output is cleared by a READ to the Flags
Register as shown in Figure 24., page 20. A subsequent READ of the Flags Register is necessary
to see that the value of the Alarm Flag has been
reset to '0.'
Figure 24. Alarm Interrupt Reset Waveform
0Eh
0Fh
00h
ALARM FLAG BIT (AF)
HIGH-Z
IRQ/OUT or
IRQ/FT/OUT
AI08898
Table 7. Alarm Repeat Modes
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm Setting
1
1
1
1
1
Once per Second
1
1
1
1
0
Once per Minute
1
1
1
0
0
Once per Hour
1
1
0
0
0
Once per Day
1
0
0
0
0
Once per Month
0
0
0
0
0
Once per Year
20/33
M41T62/63/64/65
Watchdog Timer
The watchdog timer can be used to detect an outof-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address 09h.
Bits BMB4-BMB0 store a binary multiplier and the
three bits RB2-RB0 select the resolution where:
000=1/16 second (16Hz);
001=1/4 second (4Hz);
010=1 second (1Hz);
011=4 seconds (1/4Hz); and
100 = 1 minute (1/60Hz).
Note: Invalid combinations (101, 110, and 111) will
NOT enable a watchdog time-out. Setting the
BMB4-BMB0 = 0 with any combination of RB2RB0, other than 000, will result in an immediate
watchdog time-out.
The amount of time-out is then determined to be
the multiplication of the five-bit multiplier value with
the resolution. (For example: writing 00001110 in
the Watchdog Register = 3*1 or 3 seconds). If the
processor does not reset the timer within the specified period, the M41T6x sets the WDF (Watchdog
Flag) and generates an interrupt on the IRQ pin
(M41T62), or a watchdog output pulse (M41T63
and M41T65 only) on the WDO pin. The watchdog
timer can only be reset by having the microproces-
sor perform a WRITE of the Watchdog Register.
The time-out period then starts over.
Should the watchdog timer time-out, any value
may be written to the Watchdog Register in order
to clear the IRQ pin. A value of 00h will disable the
watchdog function until it is again programmed to
a new value. A READ of the Flags Register will reset the Watchdog Flag (Bit D7; Register 0Fh). The
watchdog function is automatically disabled upon
power-up, and the Watchdog Register is cleared.
Note: A WRITE to any clock register will restart
the watchdog timer.
Watchdog Output (WDO - M41T63/65 only)
If the processor does not reset the watchdog timer
within the specified period, the Watchdog Output
(WDO) will pulse low for trec (see Table
17., page 27). This output may be connected to
the Reset input of the processor in order to generate a processor reset. After a watchdog time-out
occurs, the timer will remain disabled until such
time as a new countdown value is written into the
watchdog register.
Note: The crystal oscillator must be running for the
WDO pulse to be available.
The WDO output is an N-channel, open drain output driver (with IOL as specified in Table
14., page 26).
21/33
M41T62/63/64/65
Square Wave Output (M41T62/63/64)
The M41T62/63/64 offers the user a programmable square wave function which is output on the
SQW pin. RS3-RS0 bits located in 04h establish
the square wave output frequency. These frequencies are listed in Table 8. Once the selection
of the SQW frequency has been completed, the
SQW pin can be turned on and off under software
control with the Square Wave Enable Bit (SQWE)
located in Register 0Ah.
The SQW output is an N-channel, open drain output driver for the M41T64, and a full CMOS output
driver for the M41T62/63. The initial power-up default for the SQW output is 32KHz (except for
M41T64, which defaults disabled).
Table 8. Square Wave Output Frequency
Square Wave Bits
RS3
RS2
RS1
RS0
Frequency
Units
0
0
0
0
None
–
0
0
0
1
32.768
kHz
0
0
1
0
8.192
kHz
0
0
1
1
4.096
kHz
0
1
0
0
2.048
kHz
0
1
0
1
1.024
kHz
0
1
1
0
512
Hz
0
1
1
1
256
Hz
1
0
0
0
128
Hz
1
0
0
1
64
Hz
1
0
1
0
32
Hz
1
0
1
1
16
Hz
1
1
0
0
8
Hz
1
1
0
1
4
Hz
1
1
1
0
2
Hz
1
1
1
1
1
Hz
Full-time 32KHz Square Wave Output (M41T64)
The M41T64 offers the user a special 32KHz
square wave function which is enabled on powerup to output on the F32K pin as long as VCC ≥ 1.3V,
and the oscillator is running (ST Bit = '0'). This
function is available within one second (typ) of ini-
22/33
Square Wave
tial power-up and can only be disabled by setting
the 32KE Bit to '0' or the ST Bit to '1.' If not used,
the F32K pin should be disconnected and allowed
to float.
M41T62/63/64/65
Century Bits
These two bits will increment in a binary fashion at
the turn of the century, and handle all leap years
correctly. See Table 10., page 23 for additional
explanation.
Output Driver Pin (M41T62/65)
When the OFIE Bit, AFE Bit, and watchdog register are not set to generate an interrupt, the IRQ/
OUT pin becomes an output driver that reflects the
contents of D7 of the Calibration Register. In other
words, when D7 (OUT Bit) is a '0,' then the IRQ/
OUT pin will be driven low.
Note: The IRQ/OUT pin is an open drain which requires an external pull-up resistor.
Oscillator Stop Detection
If the Oscillator Fail (OF) Bit is internally set to a '1,'
this indicates that the oscillator has either stopped,
or was stopped for some period of time and can be
used to judge the validity of the clock and date data. This bit will be set to '1' any time the oscillator
stops.
In the event the OF Bit is found to be set to '1' at
any time other than the initial power-up, the STOP
Bit (ST) should be written to a '1,' then immediately
reset to '0.' This will restart the oscillator.
The following conditions can cause the OF Bit to
be set:
– The first time power is applied (defaults to a '1'
on power-up).
Note: If the OF Bit cannot be written to '1' four
(4) seconds after the initial power-up, the
STOP Bit (ST) should be written to a '1,' then
immediately reset to '0.'
– The voltage present on VCC or battery is
insufficient to support oscillation.
– The ST Bit is set to '1.'
– External interference of the crystal
If the Oscillator Fail Interrupt Enable Bit (OFIE) is
set to a '1,' the IRQ pin will also be activated. The
IRQ output is cleared by resetting the OFIE or OF
Bit to '0' (NOT by reading the Flag Register).
The OF Bit will remain set to '1' until written to logic
'0.' The oscillator must start and have run for at
least 4 seconds before attempting to reset the OF
Bit to '0.' If the trigger event occurs during a powerdown condition, this bit will be set correctly.
Initial Power-on Defaults
Upon application of power to the device, the register bits will initially power-on in the state indicated
in Table 9.
Table 9. Initial Power-on Default Values
Condition
Initial
Power-up(1)
Device
ST
OF
OFIE
OUT
FT
AFE
SQWE
32KE
RS3-1
RS0
Watchdog
M41T62
0
1
0
1
N/A
0
1
N/A
0
1
0
M41T63
0
1
N/A
N/A
N/A
N/A
1
N/A
0
1
0
M41T64
0
1
N/A
N/A
N/A
N/A
0
1
0
1
0
M41T65
0
1
0
1
0
0
N/A
N/A
N/A
N/A
0
Note: 1. All other control bits power-up in an undetermined state.
Table 10. Century Bits Examples
CB0
CB1
Leap Year?
Example(1)
0
0
Yes
2000
0
1
No
2100
1
0
No
2200
1
1
No
2300
Note: 1. Leap year occurs every four years (for years evenly divisible by four), except for years evenly divisible by 100. The only exceptions
are those years evenly divisible by 400 (the year 2000 was a leap year, year 2100 is not).
23/33
M41T62/63/64/65
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 11. Absolute Maximum Ratings
Sym
Parameter
Conditions(1)
Value(2)
Unit
TSTG
Storage Temperature (VCC Off, Oscillator Off)
–55 to 125
°C
VCC
Supply Voltage
–0.3 to 4.6
V
260
°C
–0.2 to Vcc+0.3
V
TSLD
(3)
VIO
Lead Solder Temperature for 10 Seconds
Input or Output Voltages
IO
Output Current
20
mA
PD
Power Dissipation
1
W
VESD(HBM)
VESD(RCDM)
Electro-static discharge voltage (Human Body Model)
TA = 25°C
>1000
V
Electro-static discharge voltage (Robotic Charged Device
Model)
TA = 25°C
>1000
V
Note: 1. Test conforms to JEDEC standard.
2. Data based on characterization results, not tested in production.
3. Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C for greater than 30 seconds).
24/33
M41T62/63/64/65
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 12. Operating and AC Measurement Conditions
Parameter
M41T6x
Supply Voltage (VCC)
1.3V to 3.6V
Ambient Operating Temperature (TA)
–40 to 85°C
Load Capacitance (CL)
50pF
Input Rise and Fall Times
≤ 5ns
Input Pulse Voltages
0.2VCC to 0.8 VCC
Input and Output Timing Ref. Voltages
0.3VCC to 0.7 VCC
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 25. AC Measurement I/O Waveform
Figure 26. Crystal Isolation Example
Local Grounding Plane
(Layer 2)
XI
Crystal
0.8VCC
XO
0.7VCC
GND
0.3VCC
0.2VCC
AI02568
AI09127
Note: Substrate pad should be tied to VSS.
Table 13. Capacitance
Parameter(1,2)
Symbol
CIN
COUT(3)
tLP
Max
Unit
7
pF
Output Capacitance
10
pF
Low-pass filter input time constant (SDA and SCL)
50
ns
Input Capacitance
Min
Note: 1. Effective capacitance measured with power supply at 3.6V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
25/33
M41T62/63/64/65
Table 14. DC Characteristics
Sym
Parameter
VCC(3) Operating Voltage
ICC1
Min
Clock(2)
I2C bus (400kHz)
SCL = 0Hz
All inputs
≥ VCC – 0.2V
≤ VSS + 0.2V
Supply Current (standby)
SQW Off
Typ
Max
Unit
1.0
3.6
V
1.3
3.6
V
100
µA
3.6V
50
3.0V
35
µA
2.5V
30
µA
2.0V
20
µA
3.6V
375
3.0V @ 25°C
350
nA
2.0V @ 25°C
310
nA
SCL = 400kHz
(No load)
Supply Current
ICC2
Test Condition(1)
700
nA
VIL
Input Low Voltage
–0.2
0.3VCC
V
VIH
Input High Voltage
0.7VCC
VCC+0.3
V
VCC = 3.6V, IOL = 3.0mA
(CMOS or Open Drain)
0.4
V
VCC = 3.6V, IOL = 1.0mA
(SQW, WDO, IRQ)
0.4
V
VOL
Output Low Voltage
VOH
VCC = 3.6V, IOH = –1.0mA (Push-Pull)
Output High Voltage
2.4
V
Pull-up Supply Voltage
(Open Drain)
IRQ/OUT, IRQ/FT/OUT, WDO, SQW
(M41T64 only)
3.6
V
ILI
Input Leakage Current
0V ≤ VIN ≤ VCC
±1
µA
ILO
Output Leakage Current
0V ≤ VOUT ≤ VCC
±1
µA
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 1.3V to 3.6V (except where noted).
2. Oscillator start-up guaranteed at 1.5V only.
3. When using battery back-up, VCC fall time should not exceed 10mV/µs.
Table 15. Crystal Electrical Characteristics
Parameter(1,2)
Sym
fO
Min
Resonant Frequency
RS
Series Resistance
CL
Load Capacitance
Typ
Max
32.768
kHz
65(3)
6
Units
kΩ
pF
Note: 1. Externally supplied if using the QFN16 package. STMicroelectronics recommends the Citizen CFS-145 (1.5x5mm) and the KDS
DT-38 (3x8mm) for thru-hole, or the KDS DMX-26S (3.2x8mm) for surface-mount, tuning fork-type quartz crystals.
KDS can be contacted at [email protected] or http://www.kdsj.co.jp.
Citizen can be contacted at [email protected] or http://www.citizencrystal.com.
2. Load capacitors are integrated within the M41T6x. Circuit board layout considerations for the 32.768kHz crystal of minimum trace
lengths and isolation from RF generating signals should be taken into account.
3. Guaranteed by design.
26/33
M41T62/63/64/65
Table 16. Oscillator Characteristics
Symbol
Parameter
VSTA
Oscillator Start Voltage
tSTA
Oscillator Start Time
Conditions
Min
≤ 10 seconds
1.5
Typ
Max
Unit
V
VCC = 3.0V
1
s
Cg
XIN
12
pF
Cd
XOUT
12
pF
IC-to-IC Frequency Variation (1)
–10
+10
ppm
Note: 1. Reference value. T A = 25°C, VCC = 3.0V, CMJ-145 (CL = 6pF, 32,768Hz) manufactured by Citizen.
Figure 27. Bus Timing Requirements Sequence
SDA
tBUF
tHD:STA
tHD:STA
tF
tR
SCL
tHIGH
P
S
tLOW
tSU:DAT
tHD:DAT
tSU:STA
SR
tSU:STO
P
AI00589
Table 17. AC Characteristics
Parameter(1)
Sym
Min
Typ
Max
Units
400
kHz
fSCL
SCL Clock Frequency
tLOW
Clock Low Period
1.3
µs
tHIGH
Clock High Period
600
ns
0
tR
SDA and SCL Rise Time
300
ns
tF
SDA and SCL Fall Time
300
ns
tHD:STA
START Condition Hold Time
(after this period the first clock pulse is generated)
600
ns
tSU:STA
START Condition Setup Time
(only relevant for a repeated start condition)
600
ns
tSU:DAT(2)
Data Setup Time
100
ns
tHD:DAT
Data Hold Time
0
µs
tSU:STO
STOP Condition Setup Time
600
ns
tBUF
Time the bus must be free before a new
transmission can start
1.3
µs
trec
Watchdog Output Pulse Width
96
98
ms
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 1.3 to 3.6V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
27/33
M41T62/63/64/65
PACKAGE MECHANICAL INFORMATION
Figure 28. QFN16 – 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Outline
D
E
A3
A
A1
ddd C
e
b
L
K
1
2
E2
Ch
3
K
D2
QFN16-A
Note: Drawing is not to scale.
28/33
M41T62/63/64/65
Table 18. QFN16 – 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Mechanical Data
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
A
0.90
0.80
1.00
0.035
0.032
0.039
A1
0.02
0.00
0.05
0.001
0.000
0.002
A3
0.20
–
–
0.008
–
–
b
0.25
0.18
0.30
0.010
0.007
0.012
D
3.00
2.90
3.10
0.118
0.114
0.122
D2
1.70
1.55
1.80
0.067
0.061
0.071
E
3.00
2.90
3.10
0.118
0.114
0.122
E2
1.70
1.55
1.80
0.067
0.061
0.071
e
0.50
–
–
0.020
–
–
K
0.20
–
–
0.008
–
–
L
0.40
0.30
0.50
0.016
0.012
0.020
ddd
–
0.08
–
–
0.003
–
Ch
–
0.33
–
–
0.013
–
N
16
16
29/33
M41T62/63/64/65
Figure 29. QFN16 – 16-lead, Quad, Flat Package, No Lead, 3x3mm, Recommended Footprint
1.60
3.55
2.0
0.28
AI09126
Note: Dimensions shown are in millimeters (mm).
Figure 30. 32KHz Crystal + QFN16 vs. VSOJ20 Mechanical Data
7.0 ± 0.3
VSOJ20
6.0 ± 0.2
3.2
SMT
CRYSTAL
1
XI
2
XO
2.9
3
4
1.5
ST QFN16
2.9
AI11146
Note: Dimensions shown are in millimeters (mm).
30/33
M41T62/63/64/65
PART NUMBERING
Table 19. Ordering Information Scheme
Example:
M41T
62
Q
6
F
Device Family
M41T
Device Type and Supply Voltage
62 = VCC = 1.3V to 3.6V
63 = VCC = 1.3V to 3.6V
64 = VCC = 1.3V to 3.6V
65 = VCC = 1.3V to 3.6V
Package
Q = QFN16
Temperature Range
6 = –40°C to 85°C
Shipping Method for SOIC
F = Lead-free Package, Tape & Reel
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
31/33
M41T62/63/64/65
REVISION HISTORY
Table 20. Document Revision History
Date
Version
Revision Details
November 13, 2003
1.0
First Issue
19-Nov-03
1.1
Add features, update characteristics (Figure 3, 4, 6, 11, 24; Table 2, 3, 9, 11, 14, 17)
25-Dec-03
2.0
Reformatted; add crystal isolation, footprint (Figure 26)
14-Jan-04
2.1
Update characteristics (Figure 3, 11, 26; Table 1, 3. 9, 14)
27-Feb-04
2.2
Update characteristics and mechanical dimensions (Figure 3, 4, 5, 6, 7, 8, 11, 12, 13,
14, 28, 29; Table 3, 4, 5, 6, 9, 11, 14, 18)
02-Mar-04
2.3
Update characteristics (Figure 9, 10, 13; Table 2, 14)
26-Apr-04
3.0
Reformat and republish
13-May-04
4.0
Update characteristics (Figure 7, 8, 9, 10, 26, 29; Table 11, 14, 15)
06-Aug-04
5.0
Correct diagrams; update characteristics (Figure 4, 5, 26; Table 2, 14, 16)
11-Oct-04
6.0
Update characteristics (Table 11, 14)
18-Jan-05
7.0
Correct footprint dimensions; update characteristics (Figure 4, 9, 13, 15, 29; Table 1,
2, 5, 8, 9, 11, 12, 14, 15, 16, 17)
05-May-05
8.0
Add package comparison and mechanical data (Figure 2, 30)
M41T6x, 41T6X, T6X, T62, T63, T64, T65, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial,
Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial,
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Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Switchover, Switchover, Switchover, Switchover, Switchover,
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32/33
M41T62/63/64/65
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
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