STW55NE10 N - CHANNEL 100V - 0.021Ω - 55A - TO247 STripFET POWER MOSFET TYPE STW 55NE10 ■ ■ ■ ■ ■ V DSS R DS(on) ID 100 V <0.027 Ω 55 A TYPICAL RDS(on) = 0.021 Ω EXCEPTIONAL dv/dt CAPABILITY 100% AVALANCHE TESTED LOW GATE CHARGE AT 100 oC APPLICATION ORIENTED CHARACTERIZATION DESCRIPTION This Power MOSFET is the latest development of STMicroelectronics unique ”Single Feature Size” strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. 1 2 3 TO-247 INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ HIGH CURRENT, HIGH SPEED SWITCHING ■ SOLENOID AND RELAY DRIVERS ■ MOTOR CONTROL, AUDIO AMPLIFIERS ■ DC-DC & DC-AC CONVERTERS ■ AUTOMOTIVE ENVIRONMENT ABSOLUTE MAXIMUM RATINGS Symbol V DS V DGR V GS Parameter Value Drain-source Voltage (VGS = 0) 100 V Drain- gate Voltage (R GS = 20 kΩ) 100 V ± 20 V 55 A Drain Current (continuous) at Tc = 100 C 35 A Drain Current (pulsed) 220 A T otal Dissipation at Tc = 25 C 180 W Derating Factor 1.2 W /o C 9 V/ns G ate-source Voltage o ID Drain Current (continuous) at Tc = 25 C ID o I DM (•) P tot o dv/dt ( 1) Peak Diode Recovery voltage slope Ts tg Tj Un it Storage Temperature Max. Operating Junction Temperature (•) Pulse width limited by safe operating area January 1999 -65 to 175 o C 175 o C ( 1) ISD ≤ 55 A, di/dt ≤ 300 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX 1/8 STW55NE10 THERMAL DATA R thj -case Rthj -amb R thc-sink Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature F or Soldering Purpose o 0.83 30 0.1 300 C/W oC/W o C/W o C Max Value Unit AVALANCHE CHARACTERISTICS Symbo l Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 55 A E AS Single Pulse Avalanche Energy (starting Tj = 25 o C, ID = IAR , V DD = 50 V) 350 mJ ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symbo l V (BR)DSS Parameter Drain-source Breakdown Voltage Test Con ditions I D = 250 µA V GS = 0 I DSS V DS = Max Rating Zero Gate Voltage Drain Current (V GS = 0) V DS = Max Rating IGSS Gate-body Leakage Current (VDS = 0) Min. Typ. Max. 100 Unit V T c = 125 oC V GS = ± 20 V 1 10 µA µA ± 100 nA Max. Unit ON (∗) Symbo l Parameter Test Con ditions V GS(th) Gate Threshold Voltage V DS = V GS ID = 250 µA R DS(on) Static Drain-source On Resistance V GS = 10V ID = 27.5 A I D(o n) On State Drain Current V DS > ID(o n) x R DS(on )ma x V GS = 10 V Min. 2 Typ. 2.6 4 V 0.021 0.027 Ω 55 A DYNAMIC Symbo l g f s (∗) C iss C os s C rss 2/8 Parameter Test Con ditions Forward Transconductance V DS > ID(o n) x R DS(on )ma x Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 25 V f = 1 MHz I D =25 A V GS = 0 Min. Typ. Max. Unit 10 35 S 4350 500 175 pF pF pF STW55NE10 ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbo l Typ. Max. Unit t d(on) tr Turn-on Time Rise Time Parameter V DD = 50 V I D = 25 A R G =4.7 Ω V GS = 10 V (see test circuit, figure 3) Test Con ditions 25 100 34 135 ns ns Qg Q gs Q gd Total G ate Charge Gate-Source Charge Gate-Drain Charge V DD = 80 V 123 24 47 165 32 64 nC nC nC Typ. Max. Unit 45 35 65 60 47 88 ns ns ns Typ. Max. Unit 55 220 A A 1.5 V 155 210 ns 815 1100 nC 10.5 15 A I D = 50 A Min. V GS = 10 V SWITCHING OFF Symbo l tr (Voff) tf tc Parameter Off-voltage Rise T ime Fall T ime Cross-over Time Test Con ditions Min. V DD = 80 V I D = 55 A R G =4.7 Ω V GS = 10 V (see test circuit, figure 5) SOURCE DRAIN DIODE Symbo l Parameter Test Con ditions ISD I SDM (•) Source-drain Current Source-drain Current (pulsed) V SD (∗) Forward On Voltage I SD = 55 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 55 A di/dt = 100 A/µs o Tj = 150 C V DD = 30 V (see test circuit, figure 5) t rr Q rr I RRM Min. V GS = 0 (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area Safe Operating Area Thermal Impedance 3/8 STW55NE10 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STW55NE10 Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/8 STW55NE10 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STW55NE10 TO-247 MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 4.7 5.3 0.185 0.209 D 2.2 2.6 0.087 0.102 E 0.4 0.8 0.016 0.031 F 1 1.4 0.039 0.055 F3 2 2.4 0.079 0.094 F4 3 3.4 0.118 0.134 G 10.9 0.429 H 15.3 15.9 0.602 0.626 L 19.7 20.3 0.776 0.779 L3 14.2 14.8 0.559 0.413 L4 34.6 1.362 L5 5.5 0.217 0.582 M 2 3 0.079 0.118 Dia 3.55 3.65 0.140 0.144 P025P 7/8 STW55NE10 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics 1998 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com . 8/8