STD2NB60 STD2NB60-1 N-CHANNEL 600V - 3.3 Ω - 2.6A DPAK/IPAK PowerMESH™ MOSFET Figure 1. Package Table 1. General Features Type VDSS RDS(on) ID STD2NB60 600 V < 3.6 Ω 2.6 A STD2NB60-1 600 V < 3.6 Ω 2.6 A FEATURES SUMMARY ■ TYPICAL RDS(on) = 3.3 Ω ■ EXTREMELY HIGH dv/dt CAPABILITY ■ 100% AVALANCHE TESTED ■ VERY LOW INTRINSIC CAPACITANCES ■ GATE CHARGE MINIMIZED DESCRIPTION Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/ dt capabilities and unrivalled gate charge and switching characteristics. 3 3 2 1 1 IPAK TO-251 DPAK TO-252 Figure 2. Internal Schematic Diagram APPLICATIONS ■ SWITCH MODE POWER SUPPLIES (SMPS) ■ DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE Table 2. Order Codes Part Number Marking Package Packaging STD2NB60T4 D2NB60 DPAK TAPE & REEL STD2NB60-1 D2NB60 IPAK TUBE REV. 2 April 2004 1/11 STD2NB60/STD2NB60-1 Table 3. Absolute Maximum Ratings Symbol Value Unit Drain-source Voltage (VGS = 0) 600 V Drain- gate Voltage (RGS = 20 kΩ) 600 V Gate-source Voltage ± 30 V ID Drain Current (cont.) at TC = 25 °C 2.6 A ID Drain Current (cont.) at TC = 100 °C 1.6 A Drain Current (pulsed) 10.4 A Total Dissipation at TC = 25 °C 50 W Derating Factor 0.4 W°/C Peak Diode Recovery voltage slope 4.5 V/ns -65 to 150 °C 150 °C Value Unit VDS VDGR VGS IDM (1) Ptot dv/dt (2) Tstg Tj Parameter Storage Temperature Max. Operating Junction Temperature Note: 1. Pulse width limited by safe operating area 2. ISD ≤ 2.6A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX Table 4. Thermal Data Symbol Parameter Rthj-case Thermal Resistance Junction-case Max 2.5 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 100 °C/W 275 °C Max Value Unit Tl Maximum Lead Temperature For Soldering Purpose Table 5. Avalanche Characteristics Symbol 2/11 Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max, δ < 1%) 2.6 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C; ID = IAR; VDD = 50 V) 80 mJ STD2NB60/STD2NB60-1 ELECTRICAL CHARACTERISTICS (Tcase = 25°C unless otherwise specified) Table 6. Off Symbol Parameter V(BR)DSS Drain-source Breakdown Voltage ID = 250 µA VGS = 0 IDSS Zero Gate Voltage VDS = Max Rating 1 µA Drain Current (VGS = 0) VDS = Max Rating Tc = 125 °C 50 µA Gate-body Leakage Current (VDS = 0) VGS = ± 30 V ± 100 nA IGSS Test Conditions Min. Typ. Max. 600 Unit V Table 7. On (1) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS; ID = 250 µA RDS(on) Static Drain-source On Resistance VGS = 10V; ID = 1.6 A Min. Typ. Max. Unit 3 4 5 V 3.3 3.6 Ω Min. Typ. Max. Unit 1.2 2 Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % Table 8. Dynamic Symbol Parameter Test Conditions gfs (1) Forward Transconductance VDS > ID(on) x RDS(on)max; ID = 1.6 A Ciss Input Capacitance VDS = 25 V; f = 1 MHz; VGS = 0 Coss Crss S 400 520 pF Output Capacitance 57 77 pF Reverse Transfer Capacitance 7 9 pF Typ. Max. Unit Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % Table 9. Switching On Symbol Parameter Test Conditions Min. Turn-on Time VDD = 300 V; ID = 1.6 A; RG = 4.7 Ω 11 17 ns Rise Time VGS = 10 V (see test circuit, Figure 16) 7 11 ns Qg Total Gate Charge VDD = 480 V; ID = 3.3 A; VGS = 10 V 15 22 nC Qgs Gate-Source Charge 6.2 nC Qgd Gate-Drain Charge 5.6 nC td(on) tr Table 10. Switching Off Symbol Parameter Test Conditions Min. Typ. Max. Unit Off-voltage Rise Time VDD = 480 V; ID = 3.3 A; RG = 4.7 Ω 11 16 ns tf Fall Time VGS = 10 V (see test circuit, Figure 18) 13 18 ns tc Cross-over Time 18 25 ns tr(Voff) 3/11 STD2NB60/STD2NB60-1 Table 11. Source Drain Diode Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD Source-drain Current 3.3 A ISDM (1) Source-drain Current (pulsed) 13.2 A VSD (2) Forward On Voltage ISD = 3.3 A; VGS = 0 1.6 V trr Reverse Recovery Time Qrr Reverse RecoveryCharge ISD = 3.3 A; di/dt = 100 A/µs VDD = 100 V; Tj = 150 °C (see test circuit, Figure 18) IRRAM Reverse RecoveryCharge 500 ns 2.1 µC 8.5 A Note: 1. Pulse width limited by safe operating area 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % Figure 3. Safe Operating Area Figure 4. Thermal Impedance Figure 5. Output Characteristics Figure 6. Transfer Characteristics 4/11 STD2NB60/STD2NB60-1 Figure 7. Transconductance Figure 8. Gate Charge vs Gate-source Voltage Figure 9. Static Drain-source On Resistance Figure 10. Capacitance Variations Figure 11. Normalized Gate Thresold Voltage vs Temperature Figure 12. Normalized On Resistance vs Temperature 5/11 STD2NB60/STD2NB60-1 Figure 13. Source-drain Diode Forward Characteristics 6/11 STD2NB60/STD2NB60-1 Figure 14. Unclamped Inductive Load Test Circuit Figure 15. Unclamped Inductive Waveforms Figure 16. Switching Times Test Circuits For Resistive Load Figure 17. Gate Charge Test Circuit Figure 18. Test Circuit For Inductive Load Switching And Diode Recovery Times 7/11 STD2NB60/STD2NB60-1 PACKAGE MECHANICAL Table 12. DPAK Mechanical Data Symbol millimeters Min Typ inches Max Min A 2.20 2.40 0.087 0.094 A1 0.90 1.10 0.035 0.043 A2 0.03 0.23 0.001 0.009 B 0.64 0.90 0.025 0.035 B2 5.20 5.40 0.204 C 0.45 0.60 0.018 Typ Max 0.213 0.024 C2 0.48 0.60 0.019 0.024 D 6.00 6.20 0.236 0.244 E 6.40 6.60 0.252 0.260 G 4.40 4.60 0.173 0.181 H 9.35 10.10 0.368 0.398 L2 0.8 0.031 L4 0.60 1.00 0.024 0.039 V2 0° 8° 0° 0° Figure 19. DPAK Package Dimensions P032P_B Note: Drawing is not to scale. 8/11 STD2NB60/STD2NB60-1 Table 13. IPAK Mechanical Data millimeters Symbol Min inches Typ Max Min Typ Max A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A3 0.7 1.3 0.027 0.051 B 0.64 0.9 0.025 0.031 B2 5.2 5.4 0.204 0.212 B3 0.85 B5 0.033 0.63 0.012 B6 0.95 0.037 C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 E 6.4 6.6 0.252 0.260 G 4.4 4.6 0.173 0.181 H 15.9 16.3 0.626 0.641 L 9 9.4 0.354 0.370 L1 0.8 1.2 0.031 0.047 L2 0.8 1 0.031 0.039 Figure 20. IPAK Package Dimensions A1 C2 A3 A C H B B3 2 G = 1 = = E B2 = 3 B5 L D B6 L2 L1 0068771-E Note: Drawing is not to scale. 9/11 STD2NB60/STD2NB60-1 REVISION HISTORY Table 14. Revision History 10/11 Date Revision Description of Changes March-1998 1 First Issue 14-Apr-2004 2 Stylesheet update. No content change. STD2NB60/STD2NB60-1 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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