STE110NS20FD N-CHANNEL 200V - 0.022Ω - 110A ISOTOP MESH OVERLAY™ Power MOSFET TYPE STE110NS20FD n n n n n n n VDSS RDS(on) ID 200V < 0.024Ω 110 A TYPICAL RDS(on) = 0.022Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED GATE CHARGE MINIMIZED ± 20V GATE TO SOURCE VOLTAGE RATING LOW INTRINSIC CAPACITANCE FAST BODY-DRAIN DIODE:LOW trr, Qrr DESCRIPTION Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patented STrip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(ON) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteristics. ISOTOP INTERNAL SCHEMATIC DIAGRAM APPLICATIONS n HIGH CURRENT, HIGH SPEED SWITCHING n SWITCH MODE POWER SUPPLY (SMPS) n DC-AC CONVERTER FOR WELDING EQUIPMENT AND UNINTERRUPTABLE POWER SUPPLY AND MOTOR DRIVE ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Drain-source Voltage (VGS = 0) 200 V Drain-gate Voltage (RGS = 20 kΩ) 200 V Gate- source Voltage ±20 V ID Drain Current (continuos) at TC = 25°C 110 A ID Drain Current (continuos) at TC = 100°C 69 A Drain Current (pulsed) 440 A Total Dissipation at TC = 25°C 500 W Derating Factor 4 W/°C Peak Diode Recovery voltage slope 25 V/ns 2500 V –65 to 150 °C 150 °C VDS VDGR VGS IDM (l) PTOT dv/dt (1) Parameter VISO Insulation Winthstand Voltage (AC-RMS) Tstg Storage Temperature Tj Max. Operating Junction Temperature (•)Pulse width limited by safe operating area January 2002 (1)ISD ≤110A, di/dt ≤200A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX 1/8 STE110NS20FD THERMAL DATA Rthj-case Thermal Resistance Junction-case Max 0.25 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 30 °C/W 300 °C Tl Maximum Lead Temperature For Soldering Purpose AVALANCHE CHARACTERISTICS Symbol Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Parameter 110 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 750 mJ ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol Parameter Test Conditions Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating IGSS Gate-body Leakage Current (VDS = 0) V(BR)DSS Min. Typ. Max. 200 Unit V 10 µA VDS = Max Rating, TC = 125 °C 100 µA VGS = ± 20V ±100 nA ON (1) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250µA RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 50A Min. Typ. Max. Unit 3 4 5 V 0.022 0.024 Ω Typ. Max. Unit DYNAMIC Symbol gfs (1) Parameter Forward Transconductance Test Conditions VDS > ID(on) x RDS(on)max, ID = 50A VDS = 25V, f = 1 MHz, VGS = 0 30 S Ciss Input Capacitance 7900 pF Coss Output Capacitance 1500 pF Crss Reverse Transfer Capacitance 460 pF Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2/8 Min. STE110NS20FD ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Parameter Turn-on Delay Time Rise Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge Test Conditions Min. VDD = 100V, ID = 50A RG = 4.7Ω VGS = 10V (see test circuit, Figure 3) VDD = 100V, ID = 100A, VGS = 10V Typ. Max. Unit 40 ns 130 ns 360 504 nC 35 nC 135 nC SWITCHING OFF Symbol tr(Voff) Parameter Off-voltage Rise Time tf Fall Time tc Cross-over Time Test Conditions Min. VDD = 100V, ID = 100A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 5) Typ. Max. Unit 245 ns 140 ns 220 ns SOURCE DRAIN DIODE Symbol Max. Unit Source-drain Current 110 A ISDM (2) Source-drain Current (pulsed) 440 A VSD (1) Forward On Voltage ISD = 100A, VGS = 0 1.6 V ISD = 100A, di/dt = 100A/µs, VDD = 160V, Tj = 150°C (see test circuit, Figure 5) ISD Parameter trr Reverse Recovery Time Qrr Reverse Recovery Charge IRRM Reverse Recovery Current Test Conditions Min. Typ. 225 ns 1.35 µC 12 A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/8 STE110NS20FD Output Characteristics Transconductance Gate Charge vs Gate-source Voltage 4/8 Transfer Characteristics Static Drain-source On Resistance Capacitance Variations STE110NS20FD Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/8 STE110NS20FD Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STE110NS20FD ISOTOP MECHANICAL DATA mm DIM. MIN. A TYP. 11.8 inch MAX. MIN. TYP. MAX. 12.2 0.466 0.480 B 8.9 9.1 0.350 0.358 C 1.95 2.05 0.076 0.080 D 0.75 0.85 0.029 0.033 E 12.6 12.8 0.496 0.503 F 25.15 25.5 0.990 1.003 G 31.5 31.7 1.240 1.248 H 4 J 4.1 4.3 0.161 0.169 K 14.9 15.1 0.586 0.594 L 30.1 30.3 1.185 1.193 M 37.8 38.2 1.488 1.503 8.2 0.307 0.157 N 4 O 7.8 0.157 0.322 A G B O F E H D N J K C L M 7/8 STE110NS20FD Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics © 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 8/8