STQ1NC60R N-CHANNEL 600V - 12Ω - 0.3A TO-92 PowerMESH II Power MOSFET TYPE STPQ1NC60R ■ ■ ■ ■ ■ V DSS RDS(on) ID 600 V < 15 Ω 0.3 A TYPICAL RDS(on) = 12 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED NEW HIGH VOLTAGE BENCHMARK GATE CHARGE MINIMIZED DESCRIPTION Using the latest high voltage MESH OVERLAYII process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteristics. TO-92 BULK TO-92 (AMMOPACK) INTERNAL SCHEMATIC DIAGRAM APPLICATIONS LOW SWITCH MODE POWER SUPPLIES (SMPS) ■ BATTERY CHARGER ■ ORDERING INFORMATION SALES TYPE MARKING PACKAGE PACKAGING STQ1NC60R Q1NC60R TO-92 BULK STQ1NC60R-AP Q1NC60R TO-92 AMMOPACK May 2002 1/9 STQ1NC60R ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR Parameter Value Unit Drain-source Voltage (VGS = 0) 600 V Drain-gate Voltage (RGS = 20 kΩ) 600 V Gate- source Voltage ± 30 V ID Drain Current (continuous) at TC = 25°C 0.3 A ID Drain Current (continuous) at TC = 100°C 0.19 A IDM (l ) Drain Current (pulsed) 1.2 A PTOT Total Dissipation at TC = 25°C VGS 3.1 W 0.025 W/°C 3 V/ns -65 to 150 -65 to 150 °C °C Derating Factor dv/dt (1) Tj Tstg Peak Diode Recovery voltage slope Operating Junction Temperature Storage Temperature ( l ) Pulse width limi ted by safe operating area (1) ISD ≤0.3A, di/dt ≤100A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. THERMAL DATA TO-92 Rthj-amb Rthj-lead Tl 120 °C/W Thermal Resistance Junction-lead Max 40 °C/W Maximum Lead Temperature For Soldering Purpose 260 °C Thermal Resistance Junction-ambient Max AVALANCHE CHARACTERISTICS Symbol Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Parameter 0.3 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 60 mJ ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) ON/OFF Symbol Test Conditions Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 IDSS Zero Gate Voltage Drain Current (V GS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 °C IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 30V VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250µA R DS(on) Static Drain-source On Resistance VGS = 10V, ID = 0.3 A V(BR)DSS 2/9 Parameter Min. Typ. Max. 600 2 Unit V 1 50 µA µA ±100 nA 3 4 V 12 15 Ω STQ1NC60R ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) DYNAMIC Symbol gfs (1) C iss Coss Crss Parameter Test Conditions Forward Transconductance VDS = 15 V, ID = 0.3 A Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. Max. 0.87 Unit S pF pF pF 108 18 2.5 SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time VDD = 300 V, ID = 0.5 A RG = 4.7Ω VGS = 10 V (Resistive Load see, Figure 3) 7.2 8 Qg Qgs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 480V, I D = 1 A, VGS = 10V, R G = 4.7Ω 7.3 3.4 2.5 10 nC nC nC Typ. Max. Unit ns ns SWITCHING OFF Symbol tr(Voff) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Condition s Min. VDD = 480V, ID = 1 A, R G = 4.7Ω, VGS = 10V (Inductive Load see, Figure 5) ns ns ns 33 11 43 SOURCE DRAIN DIODE Symbol Parameter Test Conditions ISD ISDM (2) Source-drain Current Source-drain Current (pulsed) VSD (1) Forward On Voltage ISD = 0.3 A, VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 1 A, di/dt = 100A/µs VDD = 25 V, T j = 150°C (see test circuit, Figure 5) trr Qrr IRRM Min. Typ. 450 720 3.2 Max. Unit 0.3 1.2 A A 1.6 V ns µC A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/9 STQ1NC60R Output Characteristics . Transfer Characteristics Tranconductance Static Drain-Source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/9 STQ1NC60R Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/9 STQ1NC60R Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/9 STQ1NC60R TO-92 MECHANICAL DATA mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 4.58 5.33 0.180 0.210 B 4.45 5.2 0.175 0.204 C 3.2 4.2 0.126 0.165 D 12.7 E 0.500 1.27 F 0.4 G 0.35 0.050 0.51 0.016 0.020 0.14 7/9 STQ1NC60R TO-92 AMMOPACK DIM. mm. MIN. TYP MAX. MIN. TYP. MAX. A1 4.8 0.19 T 3.8 0.15 T1 1.6 0.06 T2 2.3 0.09 d 0.48 0.02 P0 12.5 12.7 12.9 0.49 0.5 0.51 P2 5.65 6.35 7.05 0.22 0.25 0.27 F1, F2 2.44 2.54 2.94 0.09 0.1 0.11 delta H -2 2 -0.08 0.08 W 17.5 18 19 0.69 0.71 0.74 W0 5.7 6 6.3 0.22 0.23 0.24 W1 8.5 9 9.25 0.33 0.35 W2 0.5 H 18.5 H0 15.5 16 H1 D0 8/9 inch 20.5 0.72 16.5 0.61 0.80 0.63 25 3.8 4 4.2 0.36 0.02 0.65 0.98 0.15 0.157 0.16 t 0.9 0.035 L 11 0.43 l1 3 delta P -1 0.11 1 -0.04 0.04 STQ1NC60R Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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