STMICROELECTRONICS STP5NK60ZFP

STD5NK60Z
STP5NK60Z - STP5NK60ZFP
N-CHANNEL 650V @Tjmax - 1.2Ω - 5A TO-220/FP/DPAK
Zener-Protected SuperMESH™ MOSFET
Table 1: General Features
Figure 1: Package
TYPE
VDSS@
TJmax
RDS(on)
Id
PTOT
STP5NK60Z
STP5NK60ZFP
STD5NK60Z
650 V
650 V
650 V
< 1.6 Ω
< 1.6 Ω
< 1.6 Ω
5A
5A
5A
90 W
25 W
90 W
■
■
■
■
■
■
TYPICAL RDS(on) = 1.2 Ω
EXTREMELY HIGH dv/dt CAPABILITY
100% AVALANCHE TESTED
GATE CHARGE MINIMIZED
VERY LOW INTRINSIC CAPACITANCES
VERY GOOD MANUFACTURING
REPEATIBILITY
DESCRIPTION
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt capability
for the most demanding applications. Such series
complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products.
3
3
1
2
1
2
TO-220FP
TO-220
3
1
DPAK
Figure 2: Internal Schematic Diagram
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ IDEAL FOR OFF-LINE POWER SUPPLIES,
ADAPTORS AND PFC
■ LIGHTING
Table 2: Order Codes
SALES TYPE
MARKING
PACKAGE
PACKAGING
STP5NK60Z
P5NK60Z
TO-220
TUBE
STP5NK60ZFP
P5NK60ZFP
TO-220FP
TUBE
STD5NK60ZT4
D5NK60
DPAK
TAPE & REEL
Rev. 7
December 2005
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STP5NK60Z - STP5NK60ZFP- STD5NK60Z
Table 3: Absolute Maximum ratings
Symbol
Parameter
Value
TO-220/DPAK
VDS
VDGR
VGS
Unit
TO-220FP
Drain-source Voltage (VGS = 0)
600
V
Drain-gate Voltage (RGS = 20 kΩ)
600
V
Gate- source Voltage
± 30
V
ID
Drain Current (continuous) at TC = 25°C
5
5 (*)
A
ID
Drain Current (continuous) at TC = 100°C
3.16
3.16 (*)
A
IDM (z )
Drain Current (pulsed)
20
20 (*)
A
PTOT
Total Dissipation at TC = 25°C
90
25
W
0.72
0.2
W/°C
Derating Factor
VESD(G-S)
dv/dt (1)
Gate source ESD(HBM-C=100pF, R=1.5KΩ)
3000
V
4.5
V/ns
Peak Diode Recovery voltage slope
VISO
Insulation Withstand Voltage (DC)
Tj
Tstg
Operating Junction Temperature
Storage Temperature
-
2500
-55 to 150
V
°C
(z) Pulse width limited by safe operating area
(1) ISD ≤5A, di/dt ≤200A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX.
(*) Limited only by maximum temperature allowed
Thermal Data
TO-220/DPAK
TO-220FP
1.39
5
Rthj-case
Thermal Resistance Junction-case Max
Rthj-amb
Thermal Resistance Junction-ambient Max
62.5
°C/W
Maximum Lead Temperature For Soldering Purpose
300
°C
Max Value
Unit
5
A
220
mJ
Tl
°C/W
(#) When mounted on 1inch² FR-4, 2 Oz copper board.
Table 4: Avalanche Characteristics
Symbol
Parameter
IAR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tj max)
EAS
Single Pulse Avalanche Energy
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)
Table 5: Gate-Source Zener Diode
Symbol
BVGSO
Parameter
Gate-Source Breakdown
Voltage
Test Conditions
Igs=± 1mA (Open Drain)
Min.
30
Typ.
Max.
Unit
V
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
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STP5NK60Z - STP5NK60ZFP- STD5NK60Z
ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)
Table 6: On/Off
Symbol
V(BR)DSS
Parameter
Test Conditions
Min.
Typ.
Max.
600
Unit
Drain-source
Breakdown Voltage
ID = 1 mA, VGS = 0
IDSS
Zero Gate Voltage
Drain Current (VGS = 0)
VDS = Max Rating
VDS = Max Rating, TC = 125 °C
1
50
µA
µA
IGSS
Gate-body Leakage
Current (VDS = 0)
VGS = ± 20V
±10
µA
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 50µA
3.75
4.5
V
RDS(on)
Static Drain-source On
Resistance
VGS = 10V, ID = 2.5 A
1.2
1.6
Ω
Typ.
Max.
Unit
3
V
Table 7: Dynamic
Symbol
gfs (1)
Ciss
Coss
Crss
Coss eq. (3)
Parameter
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
Test Conditions
Min.
VDS = 8 V, ID = 2.5 A
VDS = 25V, f = 1 MHz, VGS = 0
4
S
690
90
20
pF
pF
pF
Equivalent Output
Capacitance
VGS = 0V, VDS = 0V to 480V
40
pF
td(on)
tr
td(off)
tr
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
VDD = 300 V, ID = 2.5 A
RG = 4.7Ω VGS = 10 V
(see Figure 20)
16
25
36
25
ns
ns
ns
ns
tr(Voff)
tf
tc
Off-voltage Rise Time
Fall Time
Cross-over Time
VDD = 480V, ID = 5 A,
RG = 4.7Ω, VGS = 10V
(see Figure 20)
12
10
24
ns
ns
ns
Qg
Qgs
Qgd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD = 400V, ID = 5 A,
VGS = 10V
(see Figure 23)
26
6
20
34
nC
nC
nC
Typ.
Max.
Unit
5
20
A
A
1.6
V
Table 8: Source Drain Diode
Symbol
Parameter
ISD
ISDM (2)
Source-drain Current
Source-drain Current (pulsed)
VSD (1)
Forward On Voltage
ISD = 5 A, VGS = 0
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
ISD = 5 A, di/dt = 100A/µs
VDD = 30V, Tj = 150°C
(see Figure 21)
trr
Qrr
IRRM
Test Conditions
Min.
485
2.7
11
ns
µC
A
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80%
VDSS.
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STP5NK60Z - STP5NK60ZFP- STD5NK60Z
Figure 3: Safe Operating Area For TO-220/
DPAK
Figure 6: Thermal Impedance For TO-220/
DPAK
Figure 4: Safe Operating Area For TO-220FP
Figure 7: Thermal Impedance For TO-220FP
Figure 5: Output Characteristics
Figure 8: Transfer Characteristics
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STP5NK60Z - STP5NK60ZFP- STD5NK60Z
Figure 9: Transconductance
Figure 12: Static Drain-source On Resistance
Figure 10: Gate Charge vs Gate-source Voltage
Figure 13: Capacitance Variations
Figure 11: Normalized Gate Threshold Voltage
vs Temperature
Figure 14: Normalized On Resistance vs Temperature
Figure 15:
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STP5NK60Z - STP5NK60ZFP- STD5NK60Z
Figure 16: Source-Drain Forward Characteristics
Figure 17: Maximum Avalanche Energy vs
Temperature
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Figure 18: Normalized BVdss vs Temperature
STP5NK60Z - STP5NK60ZFP- STD5NK60Z
Figure 19: Unclamped Inductive Load Test Circuit
Figure 22: Unclamped Inductive Wafeform
Figure 20: Switching Times Test Circuit For
Resistive Load
Figure 23: Gate Charge Test Circuit
Figure 21: Test Circuit For Inductive Load
Switching and Diode Recovery Times
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STP5NK60Z - STP5NK60ZFP- STD5NK60Z
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These
packages have a Lead-free second level interconnect . The category of second level interconnect is
marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The
maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an
ST trademark. ECOPACK specifications are available at: www.st.com
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STP5NK60Z - STP5NK60ZFP- STD5NK60Z
TO-220 MECHANICAL DATA
DIM.
A
mm.
MIN.
TYP
inch
MAX.
MIN.
4.40
4.60
0.173
TYP.
MAX.
0.181
0.034
b
0.61
0.88
0.024
b1
1.15
1.70
0.045
0.066
c
0.49
0.70
0.019
0.027
D
15.25
15.75
0.60
0.620
E
10
10.40
0.393
0.409
e
2.40
2.70
0.094
0.106
e1
4.95
5.15
0.194
0.202
F
1.23
1.32
0.048
0.052
H1
6.20
6.60
0.244
0.256
J1
2.40
2.72
0.094
0.107
L
13
14
0.511
0.551
L1
3.50
3.93
0.137
0.154
L20
16.40
0.645
L30
28.90
1.137
øP
3.75
3.85
0.147
0.151
Q
2.65
2.95
0.104
0.116
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STP5NK60Z - STP5NK60ZFP- STD5NK60Z
TO-220FP MECHANICAL DATA
mm.
DIM.
MIN.
inch
TYP
MAX.
MIN.
TYP.
MAX.
A
4.4
4.6
0.173
0.181
B
2.5
2.7
0.098
0.106
D
2.5
2.75
0.098
0.108
E
0.45
0.7
0.017
0.027
F
0.75
1
0.030
0.039
F1
1.15
1.7
0.045
0.067
F2
1.15
1.7
0.045
0.067
G
4.95
5.2
0.195
0.204
G1
2.4
2.7
0.094
0.106
H
10
10.4
0.393
0.409
L2
16
0.630
L3
28.6
30.6
1.126
1.204
L4
9.8
10.6
.0385
0.417
L5
2.9
3.6
0.114
0.141
L6
15.9
16.4
0.626
0.645
9
9.3
0.354
0.366
Ø
3
3.2
0.118
0.126
B
D
A
E
L7
L3
L6
F2
H
G
G1
F
F1
L7
L2
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L5
1 2 3
L4
STP5NK60Z - STP5NK60ZFP- STD5NK60Z
TO-252 (DPAK) MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
A
2.20
2.40
0.087
TYP.
MAX.
0.094
A1
0.90
1.10
0.035
0.043
A2
0.03
0.23
0.001
0.009
B
0.64
0.90
0.025
0.035
B2
5.20
5.40
0.204
0.213
C
0.45
0.60
0.018
0.024
C2
0.48
0.60
0.019
0.024
D
6.00
6.20
0.236
0.244
E
6.40
6.60
0.252
0.260
G
4.40
4.60
0.173
0.181
H
9.35
10.10
0.368
0.398
L2
0.8
0.031
L4
0.60
1.00
0.024
0.039
V2
0o
8o
0o
0o
P032P_B
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STP5NK60Z - STP5NK60ZFP- STD5NK60Z
DPAK FOOTPRINT
All dimensions are in millimeters
TAPE AND REEL SHIPMENT
REEL MECHANICAL DATA
DIM.
mm
MIN.
A
B
DIM.
mm
MIN.
MAX.
A0
6.8
7
0.267 0.275
B0
10.4
10.6
0.409 0.417
B1
D
12/14
inch
1.5
MIN.
MAX.
12.1
0.476
1.6
0.059 0.063
D1
1.5
E
1.65
1.85
0.065 0.073
0.059
F
7.4
7.6
0.291 0.299
K0
2.55
2.75
0.100 0.108
P0
3.9
4.1
0.153 0.161
P1
7.9
8.1
0.311 0.319
P2
1.9
2.1
R
40
W
15.7
0.075 0.082
1.574
16.3
0.618
0.641
MIN.
330
1.5
C
12.8
D
20.2
G
16.4
N
50
T
TAPE MECHANICAL DATA
inch
MAX.
MAX.
12.992
0.059
13.2
0.504 0.520
0.795
18.4
0.645 0.724
1.968
22.4
0.881
BASE QTY
BULK QTY
2500
2500
STP5NK60Z - STP5NK60ZFP- STD5NK60Z
Table 9: Revision History
Date
Revision
05-Apr-2005
29-Apr-2005
06-Sep-2005
14-Oct-2005
28-Oct-2005
14-Nov-2005
15-Dec-2005
1
2
3
4
5
6
7
Description of Changes
First issue
Modified value in Table 7.
Inserted Ecopack indication
Modified value on Table 1
Tape & Reel info added
Modified value on Table 6
Various corrections
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STP5NK60Z - STP5NK60ZFP- STD5NK60Z
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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All other names are the property of their respective owners
© 2005 STMicroelectronics - All Rights Reserved
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