STU13NC50 N-CHANNEL 500V - 0.31Ω - 13A Max220 PowerMesh™II MOSFET TYPE STU13NC50 ■ ■ ■ ■ ■ VDSS RDS(on) ID 500V < 0.4 Ω 13 A TYPICAL RDS(on) = 0.31Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED NEW HIGH VOLTAGE BENCHMARK GATE CHARGE MINIMIZED DESCRIPTION The PowerMESH™II is the evolution of the first generation of MESH OVERLAY™. The layout refinements introduced greatly improve the Ron*area figure of merit while keeping the device at the leading edge for what concerns swithing speed, gate charge and ruggedness. 1 2 3 Max220 INTERNAL SCHEMATIC DIAGRAM APPLICATIONS HIGH CURRENT, HIGH SPEED SWITCHING ■ UNINTERRUPTIBLE POWER SUPPLIES (UPS) ■ DC-AC CONVERTERS FOR TELECOM, INDUSTRIAL, AND LIGHTING EQUIPMENT ■ ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Drain-source Voltage (VGS = 0) 500 V Drain-gate Voltage (RGS = 20 kΩ) 500 V Gate- source Voltage ±30 V ID Drain Current (continuos) at TC = 25°C 13 A ID Drain Current (continuos) at TC = 100°C 8 A VDS VDGR VGS IDM (●) PTOT dv/dt(1) Tstg Tj Parameter Drain Current (pulsed) 52 A Total Dissipation at TC = 25°C 160 W Derating Factor 1.28 W/°C Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature (•)Pulse width limited by safe operating area October 2001 3.5 V/ns –65 to 150 °C 150 °C (1)ISD ≤13A, di/dt ≤130A/µs, V DD ≤ V(BR)DSS, Tj ≤ T JMAX. 1/8 STU13NC50 THERMAL DATA Rthj-case Thermal Resistance Junction-case Max 0.78 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W Maximum Lead Temperature For Soldering Purpose 300 °C Tl AVALANCHE CHARACTERISTICS Symbol Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Parameter 13 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 800 mJ ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol Parameter Test Conditions Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating IGSS Gate-body Leakage Current (VDS = 0) VGS = ±30V V(BR)DSS Min. Typ. Max. 500 Unit V VDS = Max Rating, TC = 125 °C 1 µA 50 µA ±100 nA ON (1) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 7 A Min. Typ. Max. Unit 2 3 4 V 0.31 0.4 Ω Typ. Max. Unit DYNAMIC Symbol 2/8 Parameter gfs Forward Transconductance Test Conditions VDS > ID(on) x RDS(on)max, ID = 7A VDS = 25V, f = 1 MHz, VGS = 0 Min. 13 S Ciss Input Capacitance 1970 pF Coss Output Capacitance 300 pF Crss Reverse Transfer Capacitance 48 pF STU13NC50 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Qg Parameter Turn-on Delay Time Rise Time Test Conditions Min. VDD = 250V, ID = 7 A RG = 4.7Ω VGS = 10V (see test circuit, Figure 3) Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge Typ. Unit 20 ns 23 ns 75 VDD = 400V, ID = 14 A, VGS = 10V Max. 105 nC 10 nC 38 nC SWITCHING OFF Symbol tr(Voff) Parameter Off-voltage Rise Time tf Fall Time tc Cross-over Time Test Conditions Min. Typ. Max. 25 VDD = 400V, ID = 14 A, RG = 4.7Ω, VGS = 10V (see test circuit, Figure 5) Unit ns 30 ns 62 ns SOURCE DRAIN DIODE Symbol ISD Parameter Test Conditions Min. Typ. Source-drain Current ISDM (2) Source-drain Current (pulsed) VSD (1) Forward On Voltage ISD = 14 A, VGS = 0 trr Reverse Recovery Time Qrr Reverse Recovery Charge IRRM Reverse Recovery Current ISD = 14 A, di/dt = 100A/µs, VDD = 100V, Tj = 150°C (see test circuit, Figure 5) Max. Unit 13 A 52 A 1.4 V 670 ns 6.7 µC 20 A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/8 STU13NC50 Output Characteristics Transconductance Gate Charge vs Gate-source Voltage 4/8 Transfer Characteristics Static Drain-source On Resistance Capacitance Variations STU13NC50 NormalizedGateTheresholdVoltagevsTemperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/8 STU13NC50 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STU13NC50 Max220 MECHANICAL DATA mm DIM. MIN. inch MAX. MIN. A 4.3 TYP. 4.6 0.169 TYP. MAX. 0.181 A1 2.2 2.4 0.087 0.094 A2 2.9 3.1 0.114 0.122 b 0.7 0.93 0.027 0.036 b1 1.25 1.4 0.049 0.055 b2 1.2 1.38 0.047 0.054 c 0.45 0.6 0.18 0.023 D 15.9 16.3 0.626 0.641 D1 9 9.35 0.354 0.368 D2 0.8 1.2 0.031 0.047 D3 2.8 3.2 0.110 0.126 e 2.44 2.64 0.096 0.104 E 10.05 10.35 0.396 0.407 L 13.2 13.6 0.520 0.535 L1 3 3.4 0.118 0.133 D1 D2 A1 A2 A C D3 b b2 b1 D e E L1 L P011R 7/8 STU13NC50 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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