STB80NE03L-06 STB80NE03L-06-1 N-CHANNEL 30V - 0.005Ω - 80A D2PAK / I2PAK STripFET™ POWER MOSFET TYPE STB80NE03L-06 STB80NE03L-06-1 ■ ■ ■ ■ VDSS RDS(on) ID 30 V 30 V < 0.006 Ω < 0.006 Ω 80 A 80 A TYPICAL RDS(on) = 0.005 Ω EXCEPTIONAL dv/dt CAPABILITY LOW GATE CHARGE 100°C 100% AVALANCHE TESTED DESCRIPTION This Power MOSFET is the latest development of STMicroelectronics unique “Single Feature Size™” strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. 3 3 12 1 I2PAK D2PAK INTERNAL SCHEMATIC DIAGRAM APPLICATIONS HIGH CURRENT, HIGH SPEED SWITCHING ■ SOLENOID AND RELAY DRIVERS ■ MOTOR CONTROL,AUDIO AMPLIFIERS ■ DC-DC & DC-AC CONVERTERS ■ AUTOMOTIVE ENVIRONMENT (INJECTION, ABS, AIR-BAG, LAMPDRIVERS, Etc.) ■ ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Value Unit 30 V 30 V ± 20 V ID Drain Current (continuos) at TC = 25°C 80 A ID Drain Current (continuos) at TC = 100°C 60 A IDM () PTOT dv/dt (1) Tstg Tj Drain Current (pulsed) 320 A Total Dissipation at TC = 25°C 150 W Derating Factor 1 W/°C Peak Diode Recovery voltage slope 7 V/ns – 55 to 175 °C Storage Temperature Max. Operating Junction Temperature (● ) Pulse width limited by safe operating area February 2003 (1) ISD ≤804A, di/dt ≤300A/µs, VDD ≤ V(BR)DSS, T j ≤ TJMAX. 1/9 STB80NE03L-06 / STB80NE03L-06-1 THERMAL DATA Rthj-case Thermal Resistance Junction-case Max Rthj-amb Tl 1 °C/W Thermal Resistance Junction-ambient Max 62.5 °C/W Maximum Lead Temperature For Soldering Purpose 300 °C AVALANCHE CHARACTERISTICS Symbol Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 15 V) Max Value Unit 80 A 600 mJ ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Test Conditions Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating Gate-body Leakage Current (VDS = 0) VGS = ± 20 V Min. Typ. Max. 30 Unit V 1 VDS = Max Rating, TC = 125 °C µA 10 µA ± 100 nA ON (1) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250µA RDS(on) Static Drain-source On Resistance VGS = 10 V, ID = 40 A Min. Typ. Max. Unit 1 1.7 2.5 V 0.005 0.006 Ω 0.008 Ω Max. Unit VGS = 4.5 V, ID = 40 A DYNAMIC Symbol gfs (1) 2/9 Parameter Forward Transconductance Test Conditions VDS > ID(on) x RDS(on)max, ID = 40 A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 30 50 S 6500 pF Ciss Input Capacitance Coss Output Capacitance 1500 pF Crss Reverse Transfer Capacitance 500 pF STB80NE03L-06 / STB80NE03L-06-1 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Typ. Max. Unit 40 55 ns 260 350 ns 95 30 44 130 nC nC nC Typ. Max. Unit 70 165 250 95 220 340 ns ns ns Typ. Max. Unit Source-drain Current 80 A Source-drain Current (pulsed) 320 A Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions Min. VDD = 15 V, ID = 40 A RG = 4.7Ω VGS = 4.5 V (see test circuit, Figure 3) VDD = 24 V, ID = 80A, VGS = 5V SWITCHING OFF Symbol tr(Voff) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Conditions Min. VDD = 24 V, ID = 80 A, RG = 4.7Ω, VGS = 5V (see test circuit, Figure 3) SOURCE DRAIN DIODE Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM Parameter Test Conditions Forward On Voltage ISD = 80 A, VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 80 A, di/dt = 100A/µs, VDD = 15 V, Tj = 150°C (see test circuit, Figure 5) Min. 1.5 75 0.14 4 V ns nC A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area Thermal Impedence 3/9 STB80NE03L-06 / STB80NE03L-06-1 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/9 STB80NE03L-06 / STB80NE03L-06-1 Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/9 STB80NE03L-06 / STB80NE03L-06-1 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/9 STB80NE03L-06 / STB80NE03L-06-1 D2PAK MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 4.4 4.6 0.173 0.181 A1 2.49 2.69 0.098 0.106 A2 0.03 0.23 0.001 0.009 B 0.7 0.93 0.027 0.036 B2 1.14 1.7 0.044 0.067 C 0.45 0.6 0.017 0.023 C2 1.23 1.36 0.048 0.053 D 8.95 9.35 0.352 0.368 D1 E 8 0.315 10 E1 10.4 0.393 8.5 0.334 G 4.88 5.28 0.192 0.208 L 15 15.85 0.590 0.625 L2 1.27 1.4 0.050 0.055 L3 1.4 1.75 0.055 0.068 M 2.4 3.2 0.094 0.126 R 0.015 0º 8º 3 V2 0.4 7/9 1 STB80NE03L-06 / STB80NE03L-06-1 TO-262 (I2PAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. 4.4 4.6 0.173 0.181 A1 2.49 2.69 0.098 0.106 B 0.7 0.93 0.027 0.036 B2 1.14 1.7 0.044 0.067 C 0.45 0.6 0.017 0.023 C2 1.23 1.36 0.048 0.053 D 8.95 9.35 0.352 0.368 e 2.4 2.7 0.094 0.106 E 10 10.4 0.393 0.409 L 13.1 13.6 0.515 0.531 L1 3.48 3.78 0.137 0.149 L2 1.27 1.4 0.050 0.055 E e B B2 C2 A1 A C A L1 L2 D L P011P5/E 8/9 STB80NE03L-06 / STB80NE03L-06-1 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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