TDA7339 3 BAND DIGITAL CONTROLLED AUDIO PROCESSOR PRODUCT PREVIEW THREE STEREO INPUT ONE RECORD OUTPUT ONE STEREO OUTPUT TWO INDEPENDENT VOLUME CONTROL IN 1.0dB STEPS TREBLE, MIDDLE AND BASS CONTROL IN 1.0dB STEPS ALL FUNCTIONS PROGRAMMABLE VIA SERIAL I2 CBUS DIP28 DESCRIPTION The TDA7339 is a volume and tone (bass , middle and treble) processor for quality audio application in car radio and Hi-Fi system. Control is accomplished by serial I2C bus microprocessor interface. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. ORDERING NUMBER: TDA7339 Thanks to the used BIPOLAR/MOS Technology, Low Distortion, Low Noise and Low DC stepping are obtained. BLOCK DIAGRAM R1 2.7K C7 5.6nF IN1(L) IN2(L) IN3(L) 3x 2.2µF C1 2 C2 4 C3 5 REC OUT(L) TREBLE(L) 8 C9 18nF C10 22nF M IN(L) 3 R3 2.7K C13 100nF M OUT(L) 6 C14 100nF B IN(L) 7 9 B OUT(L) 10 1st VOL 2nd VOL TREBLE MIDDLE BASS SOFTMUTE MUTE 12 14 13 SERIAL BUS DECODE & LATCHES 18 MULTIPLEXER IN1(R) IN2(R) IN3(R) C4 27 C5 25 C6 24 15 1st VOL 11 TREBLE MIDDLE BASS 2nd VOL MUTE 3x 2.2µF SOFTMUTE OUT L SCL SDA BUS ADDR DIG.GND CMUTE CSM 22nF 17 OUT R 1 VS SUPPLY 16 ANAL.GND CREF 28 21 26 REC OUT(R) TREBLE(R) CREF 10µF C8 5.6nF M IN(R) C11 18nF 23 22 M OUT(R) C12 22nF R2 2.7K 20 19 B IN(R) B OUT(R) C15 100nF D94AU067C C16 100nF R4 5.6K July 1999 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/12 TDA7339 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value 10.5 V Tamb Operating Ambient Temperature -40 to 85 °C Tstg Storage Temperature Range -55 to 150 °C VS Operating Supply Voltage Unit PIN CONNECTION VS 1 28 CREF IN1L 2 27 IN1R TREBLE L 3 26 TREBLE R IN2L 4 25 IN2R IN3L 5 24 IN3R M IN L 6 23 M IN R M OUT L 7 22 M OUT R REC OUT L 8 21 REC OUT R B IN L 9 20 B IN R B OUT L 10 19 B OUT R CMUTE 11 18 ADDR OUT L 12 17 OUT R SDA 13 16 AGND SCL 14 15 DIG GND D95AU217A THERMAL DATA Symbol Rth j-amb Parameter Thermal Resistance Junction-pins Value Unit 65 °C/W Unit QUICK REFERENCE DATA Symbol Min. Typ. Max. VS Supply Voltage Parameter 6 9 10 VCL Max. input signal handling 2 V Vrms THD Total Harmonic Distortion V = 1Vrms f = 1KHz 0.01 S/N Signal to Noise Ratio 106 dB SC Channel Separation f = 1KHz 100 dB % 1st and 2nd Volume Control 1dB step -47 0 dB Bass, Middle and Treble Control 1dB step -14 +14 dB Mute Attenuation 2/12 0.08 100 dB TDA7339 ELECTRICAL CHARACTERISTICS (VS = 9V; RL = 10KΩ; f = 1KHz; all control = flat (G = 0); Tamb = 25°C Refer to the test circuit, unless otherwise specified.) Symbol Parameter Test Condition Min. Typ. Max. Unit 35 50 65 KΩ INPUTS R in Input Resistance 1st VOLUME CONTROL C RANGE Control Range 45 47 49 dB AVMAX Astep EA Maximum Attenuation Step Resolution Attenuation Set Error 45 0.5 -1.0 47 1.0 49 1.5 1.0 dB dB dB 1.5 1 2 dB dB dB 100 0 0.5 3 5 dB mV mV 47 47 1.0 49 49 1.5 dB dB dB 1.0 1.5 1 dB dB dB 2 Et Amute VDC Tracking Error Mute Attenuation DC Steps G = 0 to -24dB G = -24 to -47dB G = 0 to -24dB G = 24 to -47dB -1.5 80 Adiacent Attenuation Steps From 0dB to AVMAX 2nd VOLUME CONTROL C RANGE AVMAX Astep Control Range Maximum Attenuation Step Resolution EA Attenuation Set Error Et Tracking Error 45 45 0.5 G = 0 to -24dB G = -24 to -47dB G = 0 to -24dB -1.0 -1.5 G = 24 to -47dB AMUTE VDC Mute Attenuation DC Steps Adiacent Attenuation Steps 100 0 3 dB dB mV From 0dB to AVMAX 0.5 5 mV 80 BASS Rb C RANGE Astep Internal Feedback Resistance Control Range Step Resolution 32 ±11.5 0.5 44 ±14 1 56 ±16 1.5 KΩ dB dB Internal Feedback Resistance Control Range 18 ±11.5 25 ±14 32 ±16 KΩ dB Step Resolution 0.5 1 1.5 dB Control Range ±13 0.5 ±14 1 ±15 1.5 dB Step Resolution Supply Voltage (note1) Supply Current Ripple Rejection 6 4 60 9 7 90 10.5 10 V mA dB 2 45 ms ms MIDDLE Rb C RANGE Astep TREBLE C RANGE Astep dB SUPPLY VS IS SVR SOFT MUTE AMUTE tD Mute Attenuation Delay Time C SM = 22µF; 0 to 20dB; I = IMAX C SM = 22µF; 0 to 20dB; I = IMIN 45 60 0.8 15 1.5 25 dB 3/12 TDA7339 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. 2 2.6 Max. Unit AUDIO OUTPUT Vclip Clipping Level R Ol Output Load Resistance RO Output Impedance VDC DC Voltage Level d = 0.3% Vrms 2 100 KΩ 180 300 3.8 Ω V GENERAL eNO Et Output Noise All Gains 0dB (B = 20 to 20kHz flat) 5 15 µV Total Tracking Error AV = 0 to -24dB 0 1 dB AV = -24 to -47dB 0 2 dB S/N Signal to Noise Ratio SC Channel Separation d Distortion All Gains = 0dB; VO = 1Vrms 106 80 AV = 0; V in = 1Vrms dB 100 0.01 dB 0.08 % 1 V 5 µA 0.8 V BUS INPUTS V il Input Low Voltage Vih Input High Voltage Iin Input Current Vin = 0.4V VO Output Voltage SDA Acknowledge IO = 1.6mA 3 NOTE 1: the device is functionally good at Vs = 5V. A step down, on V S, to 4V does’t reset the device. 4/12 V -5 0.4 TDA7339 I2C BUS INTERFACE Data transmission from microprocessor to the TDA7319 and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). Data Validity As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simplier transmission: simply it generates the 9th clock pulse without checking the slave acknowledging, and then sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. Data Validity on the I 2CBUS Timing Diagram of I2CBUS Acknowledge on the I2CBUS 5/12 TDA7339 address (the 8th bit of the byte must be 0). The TDA7339 must always acknowledge at the end of each transmitted byte. A sequence of data (N-bytes + acknowledge) A stop condition (P) SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: A start condition (s) A chip address byte, containing the TDA7339 TDA7339 ADDRESS first byte MSB S 1 0 0 0 LSB 0 1 A MSB LSB 0 ACK DATA MSB LSB DATA ACK ACK P Data Transferred (N-bytes + Acknowledge) ACK = Acknowledge S = Start P = Stop MAX CLOCK SPEED 100kbits/s SOFTWARE SPECIFICATION Chip address 1 MSB 0 0 0 0 1 A 0 LSB A = Logic level ON pin ADDR FUNCTION CODES MSB F6 F5 F4 F3 F2 F1 LSB 0 1st VOLUME 0 F6 F5 F4 F3 F2 F1 2nd VOLUME 0 F6 F5 F4 F3 F2 F1 1 TREBLE 1 0 0 F4 F3 F2 F1 F0 MIDDLE 1 0 1 F4 F3 F2 F1 F0 BASS 1 1 0 F4 F3 F2 F1 F0 MUTMUX 1 1 1 F4 F3 F2 F1 F0 POWER ON RESET: 1st volume = 2nd volume = Mute Treble = Middle = Bass = -14dB Mutmux = Active Input IN 1 6/12 TDA7339 1st VOLUME CODES MSB F6 F5 F4 F3 F2 F1 0 LSB FUNCTION 0 step 1dB 0 0 0 0dB 0 0 1 -1dB 0 1 0 -2dB 0 1 1 -3dB 1 0 0 -4dB 1 0 1 -5dB 1 1 0 -6dB 1 1 1 -7dB 0 0 step 8dB 0 0 0 0dB 0 0 1 -8dB 0 1 0 -16dB 0 1 1 -24dB 1 0 0 -32dB 1 0 1 -40dB 1 1 1 MUTE F5 F4 2nd VOLUME CODES MSB F6 F3 F2 F1 0 0 0 0dB 0 0 1 -1dB 0 1 0 -2dB 0 1 1 -3dB 1 0 0 -4dB 1 0 1 -5dB 1 1 0 -6dB 1 1 1 0 0 LSB FUNCTION 1 step 1dB -7dB 1 step 8dB 0 0 0 0dB 0 0 1 -8dB 0 1 0 -16dB 0 1 1 -24dB 1 0 0 -32dB 1 0 1 -40dB 1 1 1 MUTE 7/12 TDA7339 TREBLE CODES MSB F6 F5 1 0 0 1 8/12 0 F4 F3 F2 F1 LSB FUNCTION TREBLE BOOST 0 0 0 0 0 0dB 0 0 0 0 1 1dB 0 0 0 1 0 2dB 0 0 0 1 1 3dB 0 0 1 0 0 4dB 0 0 1 0 1 5dB 0 0 1 1 0 6dB 0 0 1 1 1 7dB 0 1 0 0 0 8dB 0 1 0 0 1 9dB 0 1 0 1 0 10dB 0 1 0 1 1 11dB 0 1 1 0 0 12dB 0 1 1 0 1 13dB 0 1 1 1 0 14dB 0 1 1 1 1 14dB 1 0 0 0 0 0dB 1 0 0 0 1 -1dB 1 0 0 1 0 -2dB 1 0 0 1 1 -3dB 1 0 1 0 0 -4dB 1 0 1 0 1 -5dB 1 0 1 1 0 -6dB 1 0 1 1 1 -7dB 1 1 0 0 0 -8dB 1 1 0 0 1 -9dB 1 1 0 1 0 -10dB 1 1 0 1 1 -11dB 1 1 1 0 0 -12dB 1 1 1 0 1 -13dB 1 1 1 1 0 -14dB 1 1 1 1 1 -14dB 0 TREBLE CUT TDA7339 MIDDLE CODES MSB F6 F5 1 0 1 1 0 F4 F3 F2 F1 LSB FUNCTION MIDDLE BOOST 0 0 0 0 0 0dB 0 0 0 0 1 1dB 0 0 0 1 0 2dB 0 0 0 1 1 3dB 0 0 1 0 0 4dB 0 0 1 0 1 5dB 0 0 1 1 0 6dB 0 0 1 1 1 7dB 0 1 0 0 0 8dB 0 1 0 0 1 9dB 0 1 0 1 0 10dB 0 1 0 1 1 11dB 0 1 1 0 0 12dB 0 1 1 0 1 13dB 0 1 1 1 0 14dB 0 1 1 1 1 14dB 1 0 0 0 0 0dB 1 0 0 0 1 -1dB 1 0 0 1 0 -2dB 1 0 0 1 1 -3dB 1 0 1 0 0 -4dB 1 0 1 0 1 -5dB 1 0 1 1 0 -6dB 1 0 1 1 1 -7dB 1 1 0 0 0 -8dB 1 1 0 0 1 -9dB 1 1 0 1 0 -10dB 1 1 0 1 1 -11dB 1 1 1 0 0 -12dB 1 1 1 0 1 -13dB 1 1 1 1 0 -14dB 1 1 1 1 1 -14dB 1 MIDDLE CUT 9/12 TDA7339 BASS CODES MSB F6 F5 1 1 0 1 1 F4 F3 F2 F1 LSB FUNCTION BASS BOOST 0 0 0 0 0 0dB 0 0 0 0 1 1dB 0 0 0 1 0 2dB 0 0 0 1 1 3dB 0 0 1 0 0 4dB 0 0 1 0 1 5dB 0 0 1 1 0 6dB 0 0 1 1 1 7dB 0 1 0 0 0 8dB 0 1 0 0 1 9dB 0 1 0 1 0 10dB 0 1 0 1 1 11dB 0 1 1 0 0 12dB 0 1 1 0 1 13dB 0 1 1 1 0 14dB 0 1 1 1 1 14dB 1 0 0 0 0 0dB 1 0 0 0 1 -1dB 1 0 0 1 0 -2dB 1 0 0 1 1 -3dB 1 0 1 0 0 -4dB 1 0 1 0 1 -5dB 1 0 1 1 0 -6dB 1 0 1 1 1 -7dB 1 1 0 0 0 -8dB 1 1 0 0 1 -9dB 1 1 0 1 0 -10dB 1 1 0 1 1 -11dB 1 1 1 0 0 -12dB 1 1 1 0 1 -13dB 1 1 1 1 0 -14dB 1 1 1 1 1 -14dB 0 BASS CUT MUTMUX CODES MSB F6 F5 1 1 1 10/12 F4 F3 F2 F1 LSB FUNCTION X X X 0 0 SLOW SOFT MUTE SLOPE (I=IMIN) X X X 0 1 FAST SOFT MUTE SLOPE (I=IMAN) X X X 1 X SOFT MUTE OFF X 0 0 NOT ALLOWED X 0 1 IN3 X 1 0 IN2 X 1 1 IN1 INPUTS TDA7339 mm DIM. MIN. TYP. inch MAX. MIN. TYP. a1 0.63 0.025 b 0.45 0.018 b1 0.23 b2 0.31 1.27 D E 0.009 0.012 0.050 37.34 15.2 16.68 1.470 0.598 0.657 e 2.54 0.100 e3 33.02 1.300 F MAX. OUTLINE AND MECHANICAL DATA 14.1 0.555 I 4.445 0.175 L 3.3 0.130 DIP28 11/12 TDA7339 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 12/12