STMICROELECTRONICS TDA7439

TDA7439
THREE BANDS
DIGITALLY CONTROLLED AUDIO PROCESSOR
1
■
FEATURES
Figure 1. Package
INPUT MULTIPLEXER
– 4 STEREO INPUTS
– SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES
■
ONE STEREO OUTPUT
■
TREBLE, MIDDLE AND BASS CONTROL IN
2.0dB STEPS
Table 1. Order Codes
■
VOLUME CONTROL IN 1.0dB STEPS
■
TWO SPEAKER ATTENUATORS:
– TWO INDEPENDENT SPEAKER CONTROL
IN 1.0dB STEPS FOR BALANCE FACILITY
– INDEPENDENT MUTE FUNCTION
■
2
SDIP30
ALL FUNCTION ARE PROGRAMMABLE VIA
SERIAL BUS
DESCRIPTION
The TDA7439 is a volume tone (bass, middle and
treble) balance (Left/Right) processor for quality
Part Number
Package
TDA7439
SDIP30
audio applications in car-radio and Hi-Fi systems.
Selectable input gain is provided. Control of all the
functions is accomplished by serial bus.
The AC signal setting is obtained by resistor networks and switches combined with operational
amplifiers.
Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise and DC stepping are
obtained
Figure 2. Block Diagram
MUXOUTL
L-IN1
11
TREBLE(L)
INL
15
16
MIN(L) MOUT(L) BIN(L)
27
26
100K
L-IN2
25
BOUT(L)
23
RM
24
RB
12
100K
L-IN3
G
13
VOLUME
TREBLE
MIDDLE
SPKR ATT
LEFT
BASS
6
LOUT
100K
L-IN4
14
100K
R-IN1
30
0/30dB
2dB STEP
10
2
I CBUS DECODER + LATCHES
1
29
100K
R-IN2
SDA
DIG_GND
9
100K
R-IN3
SCL
VOLUME
G
TREBLE
MIDDLE
SPKR ATT
RIGHT
BASS
5
ROUT
8
VREF
100K
R-IN4
3
7
100K
SUPPLY
INPUT MULTIPLEXER
+ GAIN
RM
17
MUXOUTR
June 2004
18
INR
28
TREBLE(R)
19
RB
20
21
MIN(R) MOUT(R) BIN(R)
22
4
VS
AGND
2
BOUT(R) CREF
D95AU342B
REV. 10
1/19
TDA7439
Figure 3. PIN CONNECTION
SDA
1
30
SCL
CREF
2
29
DIG_GND
VS
3
28
TREBLE(R)
AGND
4
27
TREBLE(L)
ROUT
5
26
MIN(L)
LOUT
6
25
MOUT(L)
R-IN4
7
24
BOUT(L)
R-IN3
8
23
BIN(L)
R-IN2
9
22
BOUT(R)
R-IN1
10
21
BIN(R)
L-IN1
11
20
MOUT(R)
L-IN2
12
19
MIN(R)
L-IN3
13
18
INR
L-IN4
14
17
MUXOUTR
MUXOUTL
15
16
INL
D95AU340A
Table 2. Absolute Maximum Ratings
Symbol
VS
Parameter
Operating Supply Voltage
Tamb
Operating Ambient Temperature
Tstg
Storage Temperature Range
Value
Unit
10.5
V
0 to 70
°C
-55 to 150
°C
Value
Unit
85
°C/W
Table 3. Thermal Data
Symbol
Rth j-pin
Parameter
Thermal Resistance Junction-pins
Table 4. QUICK REFERENCE DATA
Symbol
Parameter
Typ.
Max.
Unit
9
10.2
V
VS
Supply Voltage
6
VCL
Max. input signal handling
2
THD
Total Harmonic Distortion V = 1Vrms f = 1KHz
0.01
S/N
Signal to Noise Ratio Vout = 1Vrms (mode = OFF)
106
dB
SC
Channel Separation f = 1KHz
90
dB
Input Gain in (2dB step)
Vrms
0.1
%
0
30
dB
Volume Control (1dB step)
-47
0
dB
Treble Control (2dB step)
-14
+14
dB
Middle Control (2dB step)
-14
+14
dB
Bass Control (2dB step)
-14
+14
dB
Balance Control 1dB step
-79
0
dB
Mute Attenuation
2/19
Min.
100
dB
TDA7439
Table 5. Electrical Characteristcs (refer to the test circuit Tamb = 25°C, VS = 9V, RL= 10KΩ, RG = 600Ω,
all controls flat (G = 0dB), unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY
VS
Supply Voltage
6
9
10.2
V
IS
Supply Current
4
7
10
mA
Ripple Rejection
60
90
70
100
SVR
dB
INPUT STAGE
RIN
Input Resistance
VCL
Clipping Level
THD = 0.3%
2
2.5
Vrms
SIN
Input Separation
The selected input is grounded
through a 2.2µ capacitor
80
100
dB
130
KΩ
Ginmin
Minimum Input Gain
-1
0
1
dB
Ginman
Maximum Input Gain
29
30
31
dB
Gstep
Step Resolution
1.5
2
2.5
dB
Input Resistance
20
33
50
KΩ
Control Range
45
47
49
dB
AVMAX
Max. Attenuation
45
47
49
dB
ASTEP
Step Resolution
0.5
1
1.5
dB
AV = 0 to -24dB
-1.0
0
1.0
dB
AV = -24 to -47dB
-1.5
0
1.5
dB
AV = 0 to -24dB
0
1
dB
AV = -24 to -47dB
0
2
dB
0
0.5
3
mV
mV
VOLUME CONTROL
R
i
CRANGE
EA
EΤ
VDC
Amute
Attenuation Set Error
Tracking Error
DC Step
adjacent attenuation steps
from 0dB to AV max
Mute Attenuation
80
100
dB
±12.0
±14.0
±16.0
dB
BASS CONTROL (1)
Gb
Control Range
BSTEP
Step Resolution
1
2
3
dB
Internal Feedback Resistance
33
44
55
KΩ
±13.0
±14.0
±15.0
dB
1
2
3
dB
±12.0
±14.0
±16.0
dB
1
2
3
dB
18.75
25
31.25
KΩ
RB
Max. Boost/cut
TREBLE CONTROL (1)
Gt
Control Range
TSTEP
Step Resolution
Max. Boost/cut
MIDDLE CONTROL (1)
Gm
Control Range
MSTEP
Step Resolution
RM
Internal Feedback Resistance
Max. Boost/cut
3/19
TDA7439
Table 5. Electrical Characteristcs (continued)
SPEAKER ATTENUATORS
CRANGE
Control Range
70
76
82
dB
SSTEP
Step Resolution
0.5
1
1.5
dB
-1.5
0
1.5
dB
-2
0
2
dB
0
3
mV
E
A
Attenuation Set Error
AV = 0 to -20dB
AV = -20 to -56dB
VDC
Amute
DC Step
adjacent attenuation steps
Mute Attenuation
80
100
dB
2.1
2.6
VRMS
AUDIO OUTPUTS
VCLIP
Clipping Level
d = 0.3%
RL
Output Load Resistance
2
KΩ
RO
Output Impedance
10
40
70
Ω
VDC
DC Voltage Level
3.5
3.8
4.1
V
GENERAL
ENO
Et
Output Noise
All gains = 0dB;
BW = 20Hz to 20KHz flat
5
15
µV
Total Tracking Error
AV = 0 to -24dB
0
1
dB
AV = -24 to -47dB
0
2
dB
S/N
Signal to Noise Ratio
SC
Channel Separation Left/Right
d
Distortion
All gains 0dB; VO = 1VRMS ;
95
106
dB
80
100
dB
AV = 0; VI = 1VRMS ;
0.01
0.08
%
1
V
BUS INPUT
VIL
Input Low Voltage
VIH
Input High Voltage
IIN
Input Current
VIN = 0.4V
VO
Output Voltage SDA Acknowledge
IO = 1.6mA
3
-5
V
0
5
µA
0.4
0.8
V
Notes: 1. The device is functionally good at Vs = 5V. a step down, on Vs, to 4V does’t reset the device.
2. BASS, MIDDLE and TREBLE response: The center frequency and the response quality can be chosen by the external circuitry.
4/19
TDA7439
Figure 4. TEST CIRCUIT
2.7K
5.6nF
MUXOUTL
11
0.47µF
0.47µF
24
RM
G
VOLUME
TREBLE
RB
MIDDLE
SPKR ATT
LEFT
BASS
6
30
0/30dB
2dB STEP
10
2
I CBUS DECODER + LATCHES
1
29
100K
LOUT
SCL
SDA
DIGGND
9
100K
VOLUME
G
TREBLE
MIDDLE
5
SPKR ATT
RIGHT
BASS
ROUT
8
VREF
100K
7
3
100K
INPUT MULTIPLEXER
+ GAIN
RM
SUPPLY
RB
4
VS
AGND
17
INR
MUXOUTR
18
28
TREBLE(R)
2.2µF
19
20
MOUT(R)
18nF
5.6nF
3
BOUT(L)
23
100K
0.47µF
R-IN4
BIN(L)
14
0.47µF
R-IN3
25
100K
0.47µF
R-IN2
26
100K
13
0.47µF
R-IN1
MOUT(L)
27
100nF
12
0.47µF
L-IN4
22nF 100nF
100K
0.47µF
L-IN3
TREBLE(L)
16
MIN(R)
L-IN2
INL
15
MIN(L)
2.2µF
L-IN1
5.6K
18nF
21
22
BIN(R)
BOUT(R)
22nF 100nF
2.7K
5.6K
100nF
2
CREF
10µF
D95AU339B
APPLICATION SUGGESTIONS
The first and the last stages are volume control blocks. The control range is 0 to -47dB (mute) for the first
one, 0 to -79dB (mute) for the last one.
Both of them have 1dB step resolution. The very high resolution allows the implementation of systems free
from any noisy acoustical effect. The TDA7439 audioprocessor provides 3 bands tones control.
3.1 Bass, Middle Stages
The Bass and the middle cells have the same structure. The Bass cell has an internal resistor Ri = 44KΩ
typical.
The Middle cell has an internal resistor Ri = 25KΩ typical.
Several filter types can be implemented, connecting external components to the Bass/Middle IN and OUT
pins.
Figure 5.
Ri internal
IN
OUT
C1
C2
R2
D95AU313
5/19
TDA7439
The fig.5 refers to basic T Type Bandpass Filter starting from the filter component values (R1 internal and
R2,C1,C2 external) the centre frequency Fc, the gain Av at max. boost and the filter Q factor are computed
as follows:
1
FC = ----------------------------------------------------------------2 ⋅ π ⋅ R1 ⋅ R2 ⋅ C 1 ⋅ C2
R2C 2 + R2C1 + RiC1
AV = -----------------------------------------------------------R2 C1 + R2C2
R 1 ⋅ R2 ⋅ C1 ⋅ C2
Q = -------------------------------------------------R 2C1 + R2C2
Viceversa, once Fc, Av, and Ri internal value are fixed, the external components values will be:
2
Q ⋅ C1
C2 = -----------------------------2
AV – 1 – Q
AV – 1
C1 = -----------------------------------------2 ⋅ π ⋅ Fc ⋅ Ri ⋅ Q
2
AV – 1 – Q
R2 = ---------------------------------------------------------------------2 ⋅ π ⋅ C1 ⋅ Fc ⋅ ( AV – 1 ) ⋅ Q
3.2 Treble Stage
The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25KΩ typical) and
an external capacitor connected between treble pins and ground Typical responses are reported in Figg.
10 to 13.
3.3 CREF
The suggested 10µF reference capacitor (CREF) value can be reduced to 4.7µF if the application requires
faster power ON.
Figure 6. THD vs. frequency
6/19
Figure 7. THD vs. RLOAD
TDA7439
Figure 8. Channel separation vs. frequency
Figure 11. Middle response
Figure 9. Bass response
Figure 12. Typical tone response
Figure 10. Treble response
7/19
TDA7439
4
I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7439 and vice versa takes place through the 2 wires
I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage
must be connected).
4.1 Data Validity
As shown in fig. 13, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
4.2 Start and Stop Conditions
As shown in fig.14 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
4.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge
bit. The MSB is transferred first.
4.4 Acknowledge
The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
15). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this
clock pulse.
The audio processor which has been addressed has to generate an acknowledge after the reception of
each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case
the master transmitter can generate the STOP information in order to abort the transfer.
4.5 Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio processor, the mP can use a simpler transmission:
simply it waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
Figure 13. Data Validity on the I2CBUS
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
Figure 14.
SCL
I2CBUS
SDA
START
8/19
D99AU1032
STOP
TDA7439
Figure 15.
SCL
1
2
3
7
8
9
SDA
MSB
START
5
ACKNOWLEDGMENT
FROM RECEIVER
D99AU1033
SOFTWARE SPECIFICATION
5.1 Interface Protocol
The interface protocol comprises:
■
A start condition (S)
■
A chip address byte, containing the TDA7439 address
■
A subaddress bytes
■
A sequence of data (N byte + acknowledge)
■
A stop condition (P)
Figure 16.
SUBADDRESS
CHIP ADDRESS
MSB
S
1
LSB
0
0
0
1
0
0
0
MSB
ACK
X
DATA 1 to DATA n
LSB
X
X
B
DATA
MSB
ACK
LSB
DATA
ACK
P
D96AU420
ACK = Acknowledge
S = Start
P = Stop
A = Address
B = Auto Increment
6
EXAMPLES
6.1 No Incremental Bus
The TDA7439 receives a start condition, the correct chip address, a subaddress with the B = 0 (no incremental bus), N-data (all these data concern the subaddress selected), a stop condition.
Figure 17.
SUBADDRESS
CHIP ADDRESS
MSB
S
1
LSB
0
0
0
1
0
0
0
MSB
ACK
X
DATA
LSB
X
X
0 D3 D2 D1 D0 ACK
MSB
LSB
DATA
ACK
P
D96AU421
9/19
TDA7439
6.2 Incremental Bus
The TDA7439 receive a start conditions, the correct chip address, a subaddress with the B = 1 incremental
bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from
"XXX1000" to "XXX1111" of DATA are ignored.
The DATA 1 concern the subaddress sent, and the DATA 2 concern the subaddress sent plus one in the
loop etc, and at the end it receivers the stop condition.
Figure 18.
SUBADDRESS
CHIP ADDRESS
MSB
S
1
LSB
0
0
0
1
0
0
0
MSB
ACK
X
DATA 1 to DATA n
LSB
X
X
MSB
1 D3 D2 D1 D0 ACK
LSB
DATA
ACK
D96AU422
Table 6. POWER ON RESET CONDITION
7
INPUT SELECTION
IN2
INPUT GAIN
28dB
VOLUME
MUTE
BASS
0dB
MIDDLE
2dB
TREBLE
2dB
SPEAKER
MUTE
DATA BYTES
Address = 88 HEX (ADDR:OPEN).
Figure 19. FUNCTION SELECTION: First byte (subaddress)
MSB
LSB
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
B
0
0
0
0
INPUT SELECT
X
X
X
B
0
0
0
1
INPUT GAIN
X
X
X
B
0
0
1
0
VOLUME
X
X
X
B
0
0
1
1
BASS
X
X
X
B
0
1
0
0
MIDDLE
X
X
X
B
0
1
0
1
TREBLE
X
X
X
B
0
1
1
0
SPEAKER ATTENUATE "R"
X
X
X
B
0
1
1
1
SPEAKER ATTENUATE "L"
B = 1: INCREMENTAL BUS ACTIVE
B = 0: NO INCREMENTAL BUS
X = DON’T CARE
10/19
P
TDA7439
Table 7. INPUT SELECTION
MSB
LSB
INPUT MULTIPLEXER
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
0
0
IN4
X
X
X
X
X
X
0
1
IN3
X
X
X
X
X
X
1
0
IN2
X
X
X
X
X
X
1
1
IN1
Table 8. INPUT GAIN SELECTION
MSB
D7
D6
D5
D4
LSB
INPUT GAIN
D3
D2
D1
D0
2dB STEPS
0
0
0
0
0dB
0
0
0
1
2dB
0
0
1
0
4dB
0
0
1
1
6dB
0
1
0
0
8dB
0
1
0
1
10dB
0
1
1
0
12dB
0
1
1
1
14dB
1
0
0
0
16dB
1
0
0
1
18dB
1
0
1
0
20dB
1
0
1
1
22dB
1
1
0
0
24dB
1
1
0
1
26dB
1
1
1
0
28dB
1
1
1
1
30dB
GAIN = 0 to 30dB
11/19
TDA7439
Table 9. VOLUME SELECTION
MSB
D7
D6
0
D5
0
D4
D3
0
0
LSB
VOLUME
D2
D1
D0
1dB STEPS
0
0
0
0dB
0
0
1
-1dB
0
1
0
-2dB
0
1
1
-3dB
1
0
0
-4dB
1
0
1
-5dB
1
1
0
-6dB
1
1
1
-7dB
0dB
0
0
0
1
-8dB
0
0
1
0
-16dB
0
0
1
1
-24dB
0
1
0
0
-32dB
0
1
0
1
-40dB
X
1
1
1
X
X
X
MUTE
LSB
BASS
VOLUME = 0 to 47dB/MUTE
Table 10. BASS SELECTION
MSB
D7
12/19
D6
D5
D4
D3
D2
D1
D0
2dB STEPS
0
0
0
0
-14dB
0
0
0
1
-12dB
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
0
1
1
0
-2dB
0
1
1
1
0dB
1
1
1
1
0dB
1
1
1
0
2dB
1
1
0
1
4dB
1
1
0
0
6dB
1
0
1
1
8dB
1
0
1
0
10dB
1
0
0
1
12dB
1
0
0
0
14dB
TDA7439
Table 11. MIDDLE SELECTION
MSB
D7
D6
D5
D4
LSB
MIDDLE
D3
D2
D1
D0
2dB STEPS
0
0
0
0
-14dB
0
0
0
1
-12dB
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
0
1
1
0
-2dB
0
1
1
1
0dB
1
1
1
1
0dB
1
1
1
0
2dB
1
1
0
1
4dB
1
1
0
0
6dB
1
0
1
1
8dB
1
0
1
0
10dB
1
0
0
1
12dB
1
0
0
0
14dB
LSB
TREBLE
Table 12. TREBLE SELECTION
MSB
D7
D6
D5
D4
D3
D2
D1
D0
2dB STEPS
0
0
0
0
-14dB
0
0
0
1
-12dB
0
0
1
0
-10dB
0
0
1
1
-8dB
0
1
0
0
-6dB
0
1
0
1
-4dB
0
1
1
0
-2dB
0
1
1
1
0dB
1
1
1
1
0dB
1
1
1
0
2dB
1
1
0
1
4dB
1
1
0
0
6dB
1
0
1
1
8dB
1
0
1
0
10dB
1
0
0
1
12dB
1
0
0
0
14dB
13/19
TDA7439
Table 13. SPEAKER ATTENUATE SELECTION
MSB
D7
D6
D5
D4
D3
SPEAKER ATTENUATION
D2
D1
D0
1dB
0
0
0
0dB
0
0
1
-1dB
0
1
0
-2dB
0
1
1
-3dB
1
0
0
-4dB
1
0
1
-5dB
1
1
0
-6dB
1
1
1
-7dB
0
0
0
0
0dB
0
0
0
1
-8dB
0
0
1
0
-16dB
0
0
1
1
-24dB
0
1
0
0
-32dB
0
1
0
1
-40dB
0
1
1
0
-48dB
0
1
1
1
-56dB
1
0
0
0
-64dB
1
0
0
1
-72dB
1
1
1
1
SPEAKER ATTENUATION = 0 to -79dB/MUTE
14/19
LSB
X
X
X
MUTE
TDA7439
Figure 20. PINS: 2
Figure 23. PINS 15, 17
VS
VS
VS
VS
20µA
20K
CREF
MIXOUT
20K
GND
D96AU430
Figure 21. PINS: 5, 6
D96AU426
Figure 24. PINS 16, 18
VS
VS
20µA
24
ROUT
LOUT
INL
INR
20µA
33K
D96AU427
VREF
D96AU434
Figure 22. PINS 7, 8, 9, 10, 11, 12, 13, 14
Figure 25. PINS 20, 25
VS
VS
20µA
20µA
IN
100K
VREF
25K
D96AU425
MOUT(L)
MOUT(R)
D96AU431
15/19
TDA7439
Figure 26. PINS 19,26
Figure 29. PINS 27, 28
VS
VS
20µA
20µA
TREBLE(L)
TREBLE(R)
50K
25K
MOUT(L)
D96AU433
MOUT(R)
D96AU431
Figure 27. PINS 21, 23
Figure 30. PIN 30
VS
20µA
20µA
SCL
44K
BIN(L)
D96AU424
BIN(R)
D96AU428
Figure 28. PINS 22, 24
Figure 31. PIN 1
VS
20µA
20µA
SDA
44K
BOUT(L)
BOUT(R)
16/19
D96AU423
D96AU429
TDA7439
Figure 32. SDIP30 Mechanical Data & Package Dimensions
mm
DIM.
MIN.
inch
TYP.
MAX.
A
MIN.
TYP.
5.08
MAX.
0.20
A1
0.51
A2
3.05
3.81
4.57
0.12
0.15
0.18
B
0.36
0.46
0.56
0.014
0.018
0.022
B1
0.76
0.99
1.40
0.030
0.039
0.055
C
0.20
0.25
0.36
0.008
0.01
0.014
D
27.43
27.94
28.45
1.08
1.10
1.12
E
10.16
10.41
11.05
0.400
0.410
0.435
E1
8.38
8.64
9.40
0.330
0.340
0.370
0.020
e
1.778
0.070
e1
10.16
0.400
L
2.54
M
S
3.30
3.81
0.10
0°(min.), 15°(max.)
0.31
OUTLINE AND
MECHANICAL DATA
0.13
0.15
SDIP30 (0.400")
0.012
17/19
TDA7439
Table 14. Revision History
Date
Revision
January 2004
9
First Issue in EDOCS DMS
June 2004
10
Changed the Style-sheet in compliance to the new “Corporate Technical
Pubblications Design Guide”
18/19
Description of Changes
TDA7439
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19/19