TDA7565 QUAD POWER AMPLIFIER WITH BUILT-IN VOLTAGE CONVERTER PRODUCT PREVIEW ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DMOS POWER OUTPUT NON-SWITCHING HI-EFFICIENCY AMPLIFIER SWITCHING HIGH EFFICIENCY VOLTAGE CONVERTER HIGH OUTPUT POWER CAPABILITY 4x60W EIAJ/4Ω MULTIPOWER BCD TECHNOLOGY MOSFET OUTPUT POWER STAGE FLEXIWATT27 FULL I2C BUS DRIVING: – ST-BY – INDEPENDENT FRONT/REAR SOFT PLAY/MUTE – SELECTABLE GAIN 26dB - 12dB (FOR LOW NOISE LINE OUTPUT FUNCTION) – HIGH EFFICIENCY ENABLE/DISABLE – VOLTAGE CONVERTER ENABLE/DISABLE – REGULATED VOLTAGE SELECTION – SWITCHING FREQUENCY SELECTION HARDWARE MUTE FUNCTION FULL FAULT PROTECTION DC OFFSET DETECTION FOUR INDEPENDENT SHORT CIRCUIT PROTECTION CLIPPING DETECTOR WITH SELECTABLE THRESHOLD (1%/10%) VIA I2C BUS ORDERING NUMBER: TDA7565 DESCRIPTION The TDA7565 is a new BCD technology QUAD BRIDGE type of car radio amplifier in Flexiwatt27 package specially intended for car radio applications. Thanks to the DMOS output stage the TDA7565 has a very low distortion allowing a clear powerful sound. The built-in voltage converter control block assures a very high output power with an extremely low number of added components.The dissipated power under average listening condition is alligned to the conventional solutions (4x40W). BLOCK DIAGRAM VS MUTE CLK VCC1 DATA VCC2 I2C BUS CC GND CLIP DETECTOR MUTE1 MUTE2 IN RF VOLTAGE CONVERTER CONTROL MG VOLTAGE CONVERTER EXTERNAL CIRCUIT F OUT RF+ 12/26dB OUT RF- IN RR SHORT CIRCUIT PROTECTION R OUT RR+ 12/26dB OUT RR- IN LF SHORT CIRCUIT PROTECTION F OUT LF+ 12/26dB OUT LF- IN LR SHORT CIRCUIT PROTECTION R OUT LR+ 12/26dB OUT LRSHORT CIRCUIT PROTECTION SVR AC_GND RF RR LF LR PW_GND TAB S_GND D00AU1232A September 2003 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/10 TDA7565 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit 18 V Vopc OFF Operating Supply Voltage , converter OFF Vopc ON Operating Supply Voltage , converter ON 25 V DC Supply Voltage 28 V Peak Supply Voltage (for t = 50ms) 50 V CK pin Voltage 6 V Data Pin Voltage 6 V IO Output Peak Current (not repetitive t = 100µs) 8 A IO Output Peak Current (repetitive f > 10Hz) VS Vpeak VCK VDATA Ptot Tstg, Tj Power Dissipation Tcase = 70°C Storage and Junction Temperature 6 A 80 W -55 to 150 °C THERMAL DATA Symbol Rth j-case Description Thermal Resistance Junction-case Max. PIN CONNECTION 27 MUTE 26 DATA 25 PW_GND RR 24 OUT RR- 23 CK 22 OUT RR+ 21 VCC2 20 OUT RF- 19 PW_GND RF 18 OUT RF+ 17 AC_GND 16 IN RF 15 IN RR 14 S_GND 13 IN LR 12 IN LF 11 SVR 10 OUT LF+ 9 PW_GND LF 8 OUT LF- 7 VCC1 6 OUT LR+ 5 CC GND 4 OUT LR- 3 PW_GND LR 2 MG 1 TAB D00AU1233A 2/10 Value Unit 1 °C/W TDA7565 ELECTRICAL CHARACTERISTICS (Refer to the test circuit, VS = 13.5V; RL = 4Ω; f = 1KHz; Voltage converter Disabled (VCOff); Tamb = 25°C; unless otherwise specified.) Symbol Parameter POWER AMPLIFIER Supply Voltage Range VS Total Quiescent Drain Current Id Id Total Quiescent Drain Current (VCon) PO Output Power (VCoff) V = 14.4V PO Output Power (VCon) V = 14.4V THD Total Harmonic Distortion CT RIN Cross Talk GV1 ∆GV1 GV2 ∆GV2 EIN1 EIN2 Output Noise Voltage 2 SVR Supply Voltage Rejection BW ASB Power Bandwidth Stand-by Attenuation ISB AM VOS VAM Stand-by Current Mute Attenuation Offset Voltage Min. Supply Voltage Threshold Slew Rate Turn on Delay Turn off Delay Thermal Foldback Junction Temperature Clip Det THD level CDTHD VO Offset Detection Thw Thermal Warning Min. Typ. 8 180 TBD Max. Unit 18 300 V mA mA EIAJ (VS = 13.7V) 35 W THD = 10% THD = 1% EIAJ (VS = 13.7V) 25 20 60 W W W 40 31 0.03 0.03 0.1 0.15 55 W W % % % % dB THD = 10% THD = 1% PO = 1W to 12W; STDMODE HE MODE; PO = 1-2W HE MODE; PO = 4-12W PO = 1-12W, f = 10kHz f = 1KHz to 10KHz, RG = 600Ω Input Impedance Voltage Gain 1 Voltage Gain Match 1 Voltage Gain 2 Voltage Gain Match 2 Output Noise Voltage 1 TON TOFF Test Condition 50 60 25.5 -1 11.5 100 26 0.5 12 130 26.5 1 12.5 KΩ dB dB dB 60 1 100 dB µV 15 20 µV -1 Rg = 600Ω; GV = 26dB filter 20Hz to 22kHz Rg = 600Ω; GV = 26dB filter 20Hz to 12kHz f = 100Hz to 10kHz; Vr = 1Vpk; Rg = 600Ω (-3dB) 0.1 50 60 dB 75 70 100 KHz dB 7 100 7.5 155 10 10 170 20 20 185 µA dB mV V V/µs ms ms °C 0 5 ±1.5 1 10 ±2 2 15 ±2.5 % % V 100 Mute & Play 70 -100 6.5 1.5 D2/D1 (IB1) 0 to 1 D2/D1 (IB1) 1 to 0 D0 (IB1) = 0 D0 (IB1) = 1 Power Amplifier = play AC Input = 0 90 165 °C I2C BUS INTERFACE Clock Frequency fSCL VIL VIH Input Low Voltage Input High Voltage 2.3 400 KHz 1.5 V V 3/10 TDA7565 ELECTRICAL CHARACTERISTICS (continua) (Refer to the test circuit, VS = 13.5V; RL = 4Ω; f = 1KHz; Voltage converter Disabled (VCOff); Tamb = 25°C; unless otherwise specified.) Symbol Parameter VMin(pin27) Mute in Threshold Voltage Test Condition Amp. Mute Min. VMout(pin27) Mute out Threshold Voltage 3.5 AM(pin 27) Mute Attenuation 80 VOLTAGE CONVERTER Vcc1, Converter Output Voltage Vcc2 (VC = ON) Fs VS = 14V D3 (IB2) = 0; D6 (IB2) = D3 (IB2) = 1; D6 (IB2) = D3 (IB2) = 0; D6 (IB2) = D3 (IB2) = 1; D6 (IB2) = D6 (IB1) = 0; D7 (IB1) = D6 (IB1) = 1; D7 (IB1) = D6 (IB1) = 0; D7 (IB1) = D6 (IB1) = 1; D7 (IB1) = Io = 250mA Io = 20mA Io = 200mA Io = 5mA Co = 1nF Co = 1nF Io = 5mA Voltage Converter Switching Frequency Vmgl Vmgh Mos Gate Output Low Voltage Mos Gate Output High Voltage Vmgclamp tf tr Vmgl (VCoff) Mos Gate Output Clamp Voltage Fall Time Rise Time Mos Gate Output Voltage with Voltage Converter Disabled Typ. Max. 1.5 V 90 0 0 1 1 0 0 1 1 15 16.5 17.5 18.5 V V V V 100 150 260 400 kHz kHz kHz kHz V V V V ns ns V 1 10.5 10 TBD 20 50 0.5 Figure 1. Demoboard Schematic C10 2.2nF VS (Vbatt) C7 2200µF R5 10 1W L1 100µH STPS30L40CT C8 220nF D1 DGND SCL SDA 23 26 VCC C12 100nF C11 3300µF C13 10µF R1 50Ω C9 10nF R4 3.3 1W Q1 R3 10Ω 2 7 5 21 OUT RF+ 18 STP60NE06 C1 220nF 20 16 IN RF OUT RFOUT RR+ 22 C2 220nF 15 IN RR 24 TDA7565 10 12 8 C4 220nF IN LR 13 MUTE 27 OUT LFOUT LR+ 6 4 11 14 17 C6 10µF 4/10 OUT RROUT LF+ C3 220nF IN LF C5 1µF 9 3 19 Unit V 25 1 OUT LR- D00AU1224B TDA7565 I2C BUS INTERFACE Data transmission from microprocessor to the TDA7565 and viceversa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown by fig. 2, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown by fig. 3 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Acknowledge The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 22). The receiver** the acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDAline is stable LOW during this clock pulse. * Transmitter master (µP) when it writes an address to the TDA7565 slave (TDA7565) when the µP reads a data byte from TDA7565 ** Receiver slave (TDA7565) when the µP writes an address to the TDA7565 master (µP) when it reads a data byte from TDA7565 Figure 2. Data Validity on the I2C BUS SDA SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED D99AU1031 Figure 3. SCL I2CBUS SDA D99AU1032 START STOP Figure 4. SCL 1 2 3 7 8 9 SDA MSB START D99AU1033 ACKNOWLEDGMENT FROM RECEIVER 5/10 TDA7565 SOFTWARE SPECIFICATIONS All the functions of the TDA7565 are activated by I2C interface. The bit 0 of the "ADDRESS BYTE" defines if the next bytes are write instruction (from µP to TDA7565) or read instruction (from TDA7565 to µP). D7 Address bit D6 Address bit D5 Address bit D4 Address bit D3 Address bit D2 Address bit D1 Address bit D0(R/W) Read/Write bit 0 = Write instruction 1 = read instruction If R/W = 0, the µP sends 2 "Instruction Bytes": IB1 and IB2. IB1 D7 Sel Freq Switch 1 D6 Sel Freq Switch 2 D5 Offset Detection start (D5 = 1) Offset Detection stop (D5 = 0) (off) D4 Front Channel Gain = 26dB (D4 = 0) Gain = 12dB (D4 = 1) D3 Rear Channel Gain = 26dB (D3 = 0) Gain = 12dB (D3 = 1) D2 Mute front channels (D2 = 0) Unmute front channels (D2 = 1) D1 Mute rear channels (D1 = 0) Unmute rear channels (D1 = 1) D0 CD 1% (D0 = 0) CD 10% (D0 = 1) D7 Voltage Converter Enabled (D7 = 1) Voltage Converter Disabled (D7 = 0) D6 Regulated voltage selection 1 D5 Test Speed D4 Stand-by on - Amplifier not working - (D4 = 0) Stand-by off - Amplifier working - (D4 = 1) D3 Regulated voltage selection 0) D2 To be forced to “Level 1” D1 Right Channel Power amplifier working in standard mode (D1 = 0) Power amplifier working in HiEff mode(D1 = 1) D0 Left Channel Power amplifier working in standard mode (D0 = 0) Power amplifier working in HiEff mode(D0 = 1) IB2 6/10 TDA7565 DB1 D7 Thermal Warning D6 X D5 X D4 X D3 X D2 Offset (LF) D1 Short Circuit Protection (CH1) D0 X D7 Off Status D6 X D5 Clip Detector Output D4 X D3 X D2 Offset (LR) D1 Short Circuit Protection (CH2) D0 X D7 St-By Status D6 X D5 X D4 X D3 X D2 Offset (RF) D1 Short Circuit Protection (CH3) D0 X D7 X D6 X D5 X D4 X D3 X D2 Offset (RR) D1 Short Circuit Protection (CH4) D0 X DB2 DB3 DB4 7/10 TDA7565 Examples of bytes sequence 1 - Turn-On of the power amplifier with 26dB gain, mute on, diagnostic defeat, HighEff mode, voltage converter disabled. Start Address byte with D0 = 0 ACK IB1 ACK IB2 XX00X000 ACK STOP ACK STOP ACK STOP 0XX1XX10 2 - Turn-Off of the power amplifier Start Address byte with D0 = 0 ACK IB1 ACK XXXXXXXX IB2 XXX0XXX0 4 - Offset detection procedure start Start Address byte with D0 = 0 ACK IB1 XX1XX11X ACK IB2 XXX1XXX0 4 - Offset detection procedure stop and reading operation. Start ■ ■ Address byte with D0 = 1 ACK DB1 STOP The purpose of this test is to check if a D.C. offset (2V typ.) is present on the outputs, produced by input capacitor with anomalous leackage current or humidity between pins. The delay from 3 to 4 can be selected by software, starting from T.B.D. ms 8/10 TDA7565 DIM. MIN. 4.45 1.80 A B C D E F (1) G G1 H (2) H1 H2 H3 L (2) L1 L2 (2) L3 L4 L5 M M1 N O R R1 R2 R3 R4 V V1 V2 V3 0.75 0.37 0.80 25.75 28.90 22.07 18.57 15.50 7.70 3.70 3.60 mm TYP. 4.50 1.90 1.40 0.90 0.39 1.00 26.00 29.23 17.00 12.80 0.80 22.47 18.97 15.70 7.85 5 3.5 4.00 4.00 2.20 2 1.70 0.5 0.3 1.25 0.50 MAX. 4.65 2.00 MIN. 0.175 0.070 1.05 0.42 0.57 1.20 26.25 29.30 0.029 0.014 22.87 19.37 15.90 7.95 0.869 0.731 0.610 0.303 4.30 4.40 0.145 0.142 0.031 1.014 1.139 inch TYP. 0.177 0.074 0.055 0.035 0.015 0.040 1.023 1.150 0.669 0.503 0.031 0.884 0.747 0.618 0.309 0.197 0.138 0.157 0.157 0.086 0.079 0.067 0.02 0.12 0.049 0.019 MAX. 0.183 0.079 OUTLINE AND MECHANICAL DATA 0.041 0.016 0.022 0.047 1.033 1.153 0.904 0.762 0.626 0.313 0.169 0.173 5˚ (Typ.) 3˚ (Typ.) 20˚ (Typ.) 45˚ (Typ.) Flexiwatt27 (vertical) (1): dam-bar protusion not included (2): molding protusion included V C B V H H1 V3 A H2 O H3 R3 L4 R4 V1 R2 L2 N L3 R L L1 V1 V2 R2 D R1 L5 Pin 1 R1 R1 E G G1 F FLEX27ME M M1 7139011 9/10 TDA7565 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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