STMICROELECTRONICS TDA7448

TDA7448
6 CHANNEL VOLUME CONTROLLER
PRODUCT PREVIEW
■
■
■
■
■
■
6 CHANNEL INPUTS
6 CHANNEL OUTPUTS
VOLUME ATTENUATION RANGE OF
0 TO -79dB
VOLUME CONTROL IN 1.0dB STEPS
6 CHANNEL INDEPENDENT CONTROL
ALL FUNCTION ARE PROGRAMMABLE VIA
SERIAL BUS
SO20
ORDERING NUMBER: TDA7448
DESCRIPTIO
The TDA7448 is a 6 channel volume controller for
quality audio applications in Multi-Channels Audio
Systems
Low Distortion, Low Noise and DC stepping are obtained.
Thanks to the used BIPOLAR/CMOS Technology,
BLOCK DIAGRAM
IN1
7
2
VOLUME
OUT1
50K
IN2
14
19
VOLUME
OUT2
50K
IN3
6
3
VOLUME
OUT3
50K
IN4
15
18
VOLUME
OUT4
50K
IN5
5
4
VOLUME
OUT5
50K
IN6
16
17
VOLUME
OUT6
50K
GND
CREF
11
I2C BUS
DECODER
SUPPLY
10
9
12
20
1
VS
SCL
SDA
ADDR
D02AU1396
December 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/13
TDA7448
ABSOLUTE MAXIMUM RATINGS
Symbol
VS
Parameter
Value
Unit
10.5
V
Operating Supply Voltage
Tamb
Operating Ambient Temperature
-10 to 85
°C
Tstg
Storage Temperature Range
-55 to 150
°C
Value
Unit
150
°C/W
PIN CONNECTION
VS
1
20
CREF
IN1
2
19
IN2
IN3
3
18
IN4
IN5
4
17
IN6
OUT5
5
16
OUT6
OUT3
6
15
OUT4
OUT1
7
14
OUT2
N.C.
8
13
N.C.
SDA
9
12
ADDR
SCL
10
11
GND
D02AU1397
THERMAL DATA
Symbol
Rth j-pin
Parameter
thermal Resistance junction-pins
QUICK REFERENCE DATA
Symbol
Parameter
Typ.
Max.
Unit
4.75
9
10
V
VS
Supply Voltage
VCL
Max Input Signal Handling
THD
Total Harmonic Distortion V = 1Vrms f =1KHz
0.01
S/N
Signal to Noise Ratio Vout = 1Vrms
100
dB
SC
Channel Separation f = 1KHz
90
dB
Volume Control (1dB step)
Mute Attenuation
2/13
Min.
2
Vrms
-79
0.1
0
90
%
dB
dB
TDA7448
ELECTRICAL CHARACTERISTCS
(refer to the test circuit Tamb = 25°C, VS = 9V, RL = 10KΩ, RG = 600Ω, unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
4.75
9
10
V
SUPPLY
VS
Supply Voltage
IS
Supply Current
7
mA
Ripple Rejection
80
dB
SVR
INPUT STAGE
RIN
Input Resistance
35
50
VCL
Clipping Level
THD = 0.3%
SIN
Input Separation
The selected input is grounded
through a 2.2µ capacitor
65
KΩ
2
2.5
Vrms
90
dB
Control Range
79
dB
AVMAX
Max. Attenuation
79
dB
ASTEP
Step Resolution
VOLUME CONTROL
CRANGE
EA
Attenuation Set Error
0.5
1
1.5
dB
-1
0
1
dB
-2.0
0
2.0
dB
AV = 0 to -24dB
-1
0
1
dB
AV = -24 to -79dB
-2
0
2
dB
adyacent attenuation steps
-3
0
3
mV
AV = 0 to -24dB
AV = -24 to -79dB
ET
VDC
Amute
Tracking Error
DC Step
Mute Attenuation
90
db
2.5
Vrms
AUDIO OUTPUTS
VCLIP
RL
VDC
Clipping Level
THD = 0.3%
Output Load Resistance
2
2
DC Voltage Level
KΩ
4.5
V
GENERAL
Output Noise
BW = 20Hz to 20KHz
All gains = 0dB, Flat
10
S/N
Signal to Noise Ratio
All gains = 0dB; VO = 1Vrms
100
dB
SC
Channel Separation left/Right
90
dB
THD
Distortion
80
AV = 0; VI = 1Vrms
0.01
15
µV
ENO
0.1
%
1
V
BUS INPUT
VIl
Input Low Voltage
VIH
Input High Voltage
IIN
Input Current
VIN = 0.4V
VO
Output Voltage SDA
Achnowledge
IO = 1.6mA
2.5
V
-5
0.4
5
µA
0.8
V
3/13
TDA7448
Figure 1. Test circuit
0.47µF
IN1
IN1
7
2
VOLUME
OUT1
50K
0.47µF
IN2
IN2
14
19
VOLUME
OUT2
50K
0.47µF
IN3
IN3
6
3
VOLUME
OUT3
50K
0.47µF
IN4
IN4
15
18
VOLUME
OUT4
50K
0.47µF
IN5
IN5
5
4
VOLUME
OUT5
50K
0.47µF
IN6
IN6
16
17
VOLUME
OUT6
50K
GND
CREF
11
I2C BUS
DECODER
SUPPLY
APPLICATION SUGGESTIONS
9
11
20
10µF
10
1
VS
SCL
SDA
ADDR
D02AU1406
Figure 3. THD vs. R LOAD
The volume control range is 0 to -79dB, by 1dB step
resolution.
The very high resolution allows the implementation of
systems free from any noise acoustical effect.
CREF
The suggested 10µF reference capacitor (CREF)
value can be reduced to 4.7µF if the application requires faster power ON.
Figure 2. THD vs. frequency
Figure 4. Channel separation vs. frequency
4/13
TDA7448
I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7448 and vice versa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected).
Data Validity
As shown in fig. 1, the data on the SDA line must be stable during the high period of the clock. The HIGH and
LOW state of the data line can only change when the clock signal on the SCL line is LOW.
Start and Stop Conditions
As shown in fig. 2 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop
condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transferred first.
Acknowledge
The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5). The
peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse.
The audio processor which has been addressed has to generate an acknowledge after the reception of each
byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master
transmitter can generate the STOP information in order to abort the transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio processor, the µP can use a simpler transmission: simply it
waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
Figure 5. Data Validity on the I2CBUS
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
Figure 6. Timing Diagram of I2CBUS
SCL
I2CBUS
SDA
D99AU1032
START
STOP
Figure 7. Acknowledge on the I2CBUS
SCL
1
2
3
7
8
9
SDA
MSB
START
D99AU1033
ACKNOWLEDGMENT
FROM RECEIVER
5/13
TDA7448
SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises:
■ A start condition (S)
■
A chip address byte, containing the TDA7448 address
■
A subaddress bytes
■
A sequence of data (N byte + acknowledge)
■
A stop condition (P))
SUBADDRESS
CHIP ADDRESS
MSB
S
1
LSB
0
0
0
1
0
0
0
MSB
ACK
X
DATA 1 to DATA n
LSB
X
X
B
DATA
MSB
ACK
LSB
DATA
ACK
P
D96AU420
ACK = Acknowledge;
S = Start;
P = Stop;
A = Address;
B = Auto Increment
EXAMPLES
No Incremental Bus
The TDA7448 receives a start condition, the correct chip address, a subaddress with the B = 0 (no incremental
bus), N-data (all these data concern the subaddress selected), a stop condition.
SUBADDRESS
CHIP ADDRESS
MSB
S
1
LSB
0
0
0
1
0
0
0
MSB
ACK
X
DATA
LSB
X
X
0 D3 D2 D1 D0
MSB
ACK
LSB
DATA
ACK
P
D96AU421
Incremental Bus
The TDA7448 receivea start conditions, the correct chip address, a subaddress with the B = 1 (incremental bus):
now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from "XXX1000"
to "XXX1111" of DATA are ignored.The DATA 1 concern the subaddress sent, and the DATA 2 concern the
subaddress sent plus one in the loop etc, and at the end it receivers the stop condition.
SUBADDRESS
CHIP ADDRESS
MSB
S
1
LSB
0
0
0
1
0
0
0
MSB
ACK
X
DATA 1 to DATA n
LSB
X
X
1 D3 D2 D1 D0
MSB
ACK
LSB
DATA
ACK
P
D96AU422
DATA BYTES
Address= 88 (HEX) (10001000): ADDR open; 8A (HEX) (10001010): connect to supply
FUNCTION SELECTION: subaddress
MSB
D7
X
X
X
X
X
X
X
X
D6
X
X
X
X
X
X
X
X
D5
X
X
X
X
X
X
X
X
B=1: INCREMENTAL BUS; ACTIVE
B=0: NO INCREMENTAL BUS
X= DON’T CARE
6/13
D4
B
B
B
B
B
B
B
B
D3
0
0
0
0
0
0
0
0
D2
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
LSB
D0
0
1
0
1
0
1
0
1
SUBADDRESS
SPEAKER ATTENUATION OUT 1
SPEAKER ATTENUATION OUT 2
SPEAKER ATTENUATION OUT 3
SPEAKER ATTENUATION OUT 4
SPEAKER ATTENUATION OUT 5
SPEAKER ATTENUATION OUT 6
NOT USED”
NOT USED
TDA7448
In Incremental Bus Mode, the three “not used” functions must be addressed in any case. For example to refresh
“ Speaker Attenuation 3 = 0dB and Speaker Attenuation 6 = -40 dB”; the following bytes must be sent:
SUBADDRESS
XXX10010
SPEAKER ATTENUATION OUT 1
XXXXXXXX
SPEAKER ATTENUATION OUT 2
XXXXXXXX
SPEAKER ATTENUATION OUT 3
00000000
SPEAKER ATTENUATION OUT 4
XXXXXXXX
SPEAKER ATTENUATION OUT 5
XXXXXXXX
SPEAKER ATTENUATION OUT 6
00101111
SPEAKER ATTENUATION SELECTION
MSB
LSB
SPEAKER ATTENUATION
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0dB
0
0
1
-1dB
0
1
0
-2dB
0
1
1
-3dB
1
0
0
-4dB
1
0
1
-5dB
1
1
0
-6dB
1
1
1
-7dB
0
0
0
0
0
-0dB
0
0
0
0
1
-8dB
0
0
0
1
0
-16dB
0
0
0
1
1
-24dB
0
0
1
0
0
-32dB
0
0
1
0
1
-40dB
0
0
1
1
0
-48dB
0
0
1
1
1
-56dB
0
1
-64dB
1
0
-72dB
1
1
MUTE
value = 0 to -79dB and MUTE
7/13
TDA7448
Figure 8. PIN:20
Figure 11. PINS: 10
VS
VS
20µA
20K
SCL
CREF
20K
D96AU424
D96AU430
Figure 9. PINS: 5, 6, 7, 14, 15, 16
Figure 12. PINS: 9
VS
20µA
24
OUT1 to
OUT6
SDA
20µA
D96AU423
D02AU1398
Figure 10. PINS: 2, 3, 4, 17, 18, 19
VS
20µA
IN
100K
VREF
8/13
D96AU425
TDA7448
Figure 13. Test and Application Circuit
J1
J2
IN1
OUT1
J3
IC1
GND
7
OUT6
C10
5
0.47µF
C12
17
C13
IN6
15
0.47µF
4
C11
+
6
OUT5
+
IN6
IN5
C8
18
C9
+
5
OUT4
0.47µF
16
OUT1
2
OUT2
3
OUT3
4
OUT4
5
OUT5
6
OUT6
7
GND
22µF 16V
22µF 16V
+
IN5
C7
IN4
C6
6
1
22µF 16V
22µF 16V
+
4
OUT3
14
0.47µF
3
22µF 16V
22µF 16V
+
IN4
IN3
C4
19
C5
OUT2
0.47µF
10µF 16V
20
8
13
CREF
SCL
N.C.
SDA
N.C.
ADDR
+ C14
100µF 16V
GND
3
IN2
7
10
9
12
J5
JP1
R1
11
IN3
C3
1
VS
2
DGND
3
SCL
4
SDA
10
C15
0.1µF
I2C
VS
1
2
OUT1
VS
IN2
IN1
1
1
J4
C2
2
+
IN1
TDA7448
0.47µF
2
C1
J6
R2
R3
1K
1K
GND
9/13
TDA7448
Figure 14. Component Layout (65 x 72mm)
Figure 15. PC Board (Component side)
10/13
TDA7448
Figure 16. PC Board (Solder side)
11/13
TDA7448
mm
inch
OUTLINE AND
MECHANICAL DATA
DIM.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.1
0.3
0.004
0.012
B
0.33
0.51
0.013
0.020
C
0.23
0.32
0.009
0.013
D
12.6
13
0.496
0.512
E
7.4
7.6
0.291
0.299
e
1.27
0.050
H
10
10.65
0.394
0.419
h
0.25
0.75
0.010
0.030
L
0.4
1.27
0.016
0.050
SO20
K
0˚ (min.)8˚ (max.)
L
h x 45˚
A
B
e
A1
K
H
D
20
11
E
1
0
1
SO20MEC
12/13
C
TDA7448
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 2002 STMicroelectronics - All Rights Reserved
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13/13