Ordering number : EN5782 CMOS IC LC4608C Printer Head Driver Overview The LC4608C is a driver for ink-jet printer heads with 64bit output. It converts 4-bit parallel input into 16-step gray scale output by regulating the transmission gate’s output time. • 16-step gray scale output from 4-bit parallel input • Built-in 64 × 2-channel transmission gate output • Transmission gate on resistance of 60 Ω (typ.) 100 Ω (max) • CMOS process with high withstand voltage (42 V) Features This 64-bit CMOS driver with 16-step gray scale output and high withstand voltage offers the following features. • Built-in 64 × 4-bit static shift register • Built-in 64 × 4-bit static latch Specifications Maximum Ratings Parameter Symbol Conditions Ratings Unit Supply voltage (logic) VDD –0.5 to +7.0 V Supply voltage (high withstand voltage circuits) VH –0.5 to +42 V Driver output breakdown voltage Driver output current Input current BVDO IDO –0.5 to +42 Peak value within allowable operating range IIN V ±400 mA –20 to +20 mA Input voltage (logic) VIN1 –0.5 to VDD +0.5 Input voltage (COM, output) VIN2 –0.5 to VH +0.5 V Operating temperature Topr –10 to +90 °C Storage temperature Tstg –65 to +150 °C Junction temperature Tj –10 to +125 °C V Allowable Operating Ranges at VDD = 5.0 V±10%, Topr = –10 to +90°C unless otherwise specified Parameter Supply voltage Input voltage Symbol Conditions VDD Ratings min typ 5.5 V 40.0 V VIN 0 VDD V COM 0 VH V 400 mA 8.0 MHz Output current DOn IDO *1 VH = 40 V *2 5.0 Unit 24.0 VH 4.5 max 200 Clock frequency fclk Data setup time tds 40 ns Data hold time tdh 40 ns Latch setup time tLs 140 ns Clock pulse width twCLK 50 ns Latch pulse width twLAT 80 ns Continued on next page. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 33198RM (OT) No. 5782-1/11 LC4608C Continued from preceding page. Parameter Symbol Conditions Ratings min typ Unit max STBCLK frequency fSTB CLK → LOAD setup time tSL 80 ns LOAD → CLK hold time tHL 80 ns LOAD pulse width tWL 80 ns STBCLK → LOAD setup time tSTBL 80 ns LOAD → STBCLK hold time tLSTB 80 1.0 MHz ns Clock rising edge time tr 35 ns Clock falling edge time tf 35 ns Latch rising edge time tlr 70 ns Latch falling edge time tlf 70 ns Operating temperature Tjopr +90 °C –1.0 Note : 1. The figures for normal operation are a load capacitance Cpzt of 1 nF, a power supply voltage VH of 30 V, and a max input level COMmax of 25 V. 2. Value for VH = 40 V, COMmax = 40 V, frequency = 35 kHz, and duty factor = 1/100. Electrical Characteristics DC Characteristics at VDD = 5.0 V±10%, Tjopr = –10 to +90°C unless otherwise specified Parameter Symbol Conditions Ratings min typ Unit max Input high-level voltage VIH VDD × 0.7 VDD +0.3 Input low-level voltage VIL –0.3 VDD × 0.3 V 0 0.5 µA Input high-level current *2 –IIH1 VDD = 5.0 V, VIH = 5.0 V –IIH2 VDD = 5.0 V, VIH = 5.0 V 0 Input low-level current *3 IIL VDD = 5.0 V 0 Output high- level voltage VOH IO = –400 µA Output low-level voltage VOL IO = 400 µA 50 V 100 µA 0.5 µA VDD – 0.5 V 0.5 V Output high-level current transmission gate voltage VOHT VDD = 5.0 V, VH = 40 V, COMn = 40 V, IOHT = 10 mA Output low-level current transmission gate voltage VOLT VDD = 5.0 V, VH = 40 V, COMn = 40 V, –IOHT = 10 mA 0.6 1.0 V Transmission gate on resistance RON VH = 40 V, VDS = 3 V 60 100 Ω Ω Transmission gate on resistance variation Rx 39 39.4 V Within chip 2 (MAX – MIN) × 100 —————————— MAX + MIN –15 +15 Current drain IDD1 VDD – GND, fclk = 3.5 MHz, fSln = 1.75 MHz –15 +15 Ω Leakage current between pins ±INL Leakage current between pins 0 10 µA Output leakage current ILEAK VDD = 5.0 V, VH = 42 V 0 100 µA Note : 1. The sign is negative for incoming current and positive for outgoing current. 2. –IIH1 applies to the following input pins: SI0 to SI3, CLK, LAT, LOAD, STBCLK, and STB1 to STB3. –IIH applies to the following input pins: STB4 and STB5. 3. IIL1 applies to the following input pins: SI0 to SI3, CLK, LAT, LOAD, STBCLK, and STB1 to STB5. Switching Characteristics at VDD = 5.0 V±10%, Tjopr = –10 to +90°C unless otherwise specified Parameter Symbol Conditions Ratings min typ max Unit SOn output rising edge time tor CL = 10 pF 50 SOn input rising edge time tof CL = 10 pF 50 ns tdor *5 1.0 µs tdof *5 1.0 µs tsor CL = 10 pF 140 ns tsof CL = 10 pF 140 ns STBn → DOn propagation delay time CLK → SOn propagation delay time ns Note : 5. The figures are for a load capacitance Cpzt of 1 nF and a power supply voltage VH of 30 V as measured with RL = 3 kΩ and COMn = 25 V DC. No. 5782-2/11 LC4608C Timing Chart 1 Timing Chart 2 Timing Chart 3 No. 5782-3/11 LC4608C Timing Chart 4 Usage Note The power on and power off sequences must use the following orders. Power on sequence: VDD → 5-V input circuits → VH → COMn Power off sequence: COMn → VH → 5-V input circuits → VDD Block Diagram Level shift circuit Gray scale control logic 4-bit counter 4-bit latche × 64 4-bit shift register × 64 No. 5782-4/11 LC4608C Pad Layout Diagram Chip size 2.67 mm × 9.48 mm Output pad PP dimensions WSM, LSM Input pad 140 µm 116 µm WM, LM 106 µm WSC, LSC 96 µm WJP, LJ 90 µm PP (min) 200 µm dimensions WSM, LSM 116 µm WM, LM 106 µm WSC, LSC 96 µm WJP, LJ 90 µm No. 5782-5/11 LC4608C Signal sequence Valid data Invalid data Valid data Invalid data Valid data No. 5782-6/11 LC4608C Pad Functions Pad Name I/O CLK I Shift register clock input Function Pin Count 1 SI0 to SI3 I Shift register serial data input. SI0 is the least significant bit of the gray scale data; SI3, the most significant bit. 4 LAT I Parallel output latch input. high level input converts serial data to parallel data; low level latches the data. 1 STB1, 2, 3 I 3-phase selector inputs. high level input turns on the corresponding output. STB1 controls output bits DO1, DO4, DO7, DO10,... DO62. STB2 controls output bits DO2, DO5, DO8, DO11,... DO63. STB3 controls output bits DO3, DO6, DO9, DO12,... DO64. 3 STB4, 5 I 2-phase selector inputs with pull-down register. high level input turns on the corresponding output. STB4 controls the odd bits: DO1, DO3, DO5,... DO63. STB5 controls the even bits: DO2, DO4, DO6,... DO64. 2 STBCLK I External clock signal input for gray scale signal generator 1 LOAD I Reset input for 4-bit counter. low level input resets the counter to “0.” 1 COM1 I Scan voltage signal input, latched when the shift register bit is “1” (DO pin pairs 1, 2, 5, 6,... 57, 58, 61, 62) 2 COM2 I Scan voltage signal input, latched when the shift register bit is “0” (DO pin pairs 1, 2, 5, 6,... 57, 58, 61, 62) 2 COM3 I Scan voltage signal input, latched when the shift register bit is “1” (DO pin pairs 3, 4, 7, 8,... 59, 60, 63, 64) 2 COM4 I Scan voltage signal input, latched when the shift register bit is “0” (DO pin pairs 3, 4, 7, 8,... 59, 60, 63, 64) 2 SO0 to SO3 O Shift register serial data output. SO0 is the least significant bit of the gray scale data; SO3, the most significant bit. 4 DO1 to DO64 O Parallel data output. Transmission gate output. 64 VDD — Power supply for logic circuits (+5 V) 2 GND — Ground for logic and level conversion circuits 4 VH — Power supply for level conversion circuits +40 V 2 No. 5782-7/11 LC4608C I/O Circuits • Logic circuit inputs Pins: SI0 to SI3, CLK, LAT, STB1 to STB3, STBCLK, LOAD The pull-down resistor *1 is only available for STB4 and STB5. • Logic circuit outputs Pins: SO0 to SO3 • DOn outputs No. 5782-8/11 LC4608C Gray Scale Timing Chart Level 0 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 Level 9 Level 10 Level 11 Level 12 Level 13 Level 14 Level 15 The rising edge is synchronized with the STBCLK falling edge. No. 5782-9/11 LC4608C Pad Coordinates Pin Name x-Coordinate DO1 –4410.0 y-Coordinate 1162.0 Pin Name DO50 x-Coordinate 2450.0 y-Coordinate 1162.0 DO2 –4270.0 1162.0 DO51 2590.0 1162.0 DO3 –4130.0 1162.0 DO52 2730.0 1162.0 DO4 –3990.0 1162.0 DO53 2870.0 1162.0 DO5 –3850.0 1162.0 DO54 3010.0 1162.0 DO6 –3710.0 1162.0 DO55 3150.0 1162.0 DO7 –3570.0 1162.0 DO56 3290.0 1162.0 DO8 –3430.0 1162.0 DO57 3430.0 1162.0 DO9 –3290.0 1162.0 DO58 3570.0 1162.0 DO10 –3150.0 1162.0 DO59 3710.0 1162.0 DO11 –3010.0 1162.0 DO60 3850.0 1162.0 DO12 –2870.0 1162.0 DO61 3990.0 1162.0 DO13 –2730.0 1162.0 DO62 4130.0 1162.0 DO14 –2590.0 1162.0 DO63 4270.0 1162.0 DO15 –2450.0 1162.0 DO64 4410.0 1162.0 DO16 –2310.0 1162.0 COM1 –4567.0 –1162.0 DO17 –2170.0 1162.0 COM2 –4367.0 –1162.0 DO18 –2030.0 1162.0 COM3 –4167.0 –1162.0 DO19 –1890.0 1162.0 COM4 –3967.0 –1162.0 DO20 –1750.0 1162.0 VH –3730.0 –1162.0 DO21 –1610.0 1162.0 GND –3457.8 –1162.0 DO22 –1470.0 1162.0 SI3 –3255.8 –1162.0 DO23 –1330.0 1162.0 SI2 –3019.8 –1162.0 DO24 –1190.0 1162.0 SI1 –2755.8 –1162.0 DO25 –1050.0 1162.0 SI0 –2519.8 –1162.0 DO26 –910.0 1162.0 GND –2215.8 –1162.0 DO27 –770.0 1162.0 VDD –1993.4 –1162.0 DO28 –630.0 1162.0 STB5 –1791.4 –1162.0 DO29 –490.0 1162.0 STB4 –1555.4 –1162.0 DO30 –350.0 1162.0 STB3 –1291.4 –1162.0 DO31 –210.0 1162.0 STB2 –1055.4 –1162.0 DO32 –70.0 1162.0 STB1 802.4 –1162.0 DO33 70.0 1162.0 STBCLK 1038.4 –1162.0 DO34 210.0 1162.0 LOAD 1302.4 –1162.0 DO35 350.0 1162.0 LAT 1538.4 –1162.0 DO36 490.0 1162.0 CLK 1802.4 –1162.0 DO37 630.0 1162.0 VDD 1990.4 –1162.0 DO38 770.0 1162.0 GND 2212.8 –1162.0 DO39 910.0 1162.0 SO0 2516.8 –1162.0 DO40 1050.0 1162.0 SO1 2752.8 –1162.0 DO41 1190.0 1162.0 SO2 3016.8 –1162.0 DO42 1330.0 1162.0 SO3 3252.8 –1162.0 DO43 1470.0 1162.0 GND 3454.8 –1162.0 DO44 1610.0 1162.0 VH 3727.8 –1162.0 DO45 1750.0 1162.0 COM4 3967.8 –1162.0 DO46 1890.0 1162.0 COM3 4167.0 –1162.0 DO47 2030.0 1162.0 COM2 4367.0 –1162.0 DO48 2170.0 1162.0 COM1 4567.0 –1162.0 DO49 2310.0 1162.0 Note: The coordinate system places the origin at the chip center, the output pads across the top, and the input pads across the bottom. No. 5782-10/11 LC4608C Note on COMn Input (Example: input data = 0100) Delay due to inverter causes both switches to turn on simultaneously. Because the chip turns the output analog switches on in pairs using the timing shown above, make sure that there are no potential differences between the pairs COM1-COM2 and COM3-COM4. ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of March, 1998. Specifications and information herein are subject to change without notice. PS No. 5782-11/11